Fixed video, kbd and buzzer
This commit is contained in:
@@ -0,0 +1,49 @@
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//============================================================================
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// Implementation of the Sinclair ZX Spectrum ULA
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//
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// This module contains the clocks section.
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//
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// TODO: Video RAM contention would cause a clock gating which would be
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// implemented in this module. RAM contention is not implemented since we are
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// using FPGA RAM cells configured in dual-port mode.
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//
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// Copyright (C) 2014-2016 Goran Devic
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//============================================================================
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module clocks
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(
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input wire clk_ula, // Input ULA clock of 14 MHz
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input wire turbo, // Turbo speed (3.5 MHz x 2 = 7.0 MHz)
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output reg clk_cpu // Output 3.5 MHz CPU clock
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);
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// Generate 3.5 MHz Z80 CPU clock by dividing input clock of 14 MHz by 4
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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reg [0:0] counter;
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// Note: In order to get to 3.5 MHz, the PLL needs to be set to generate 14 MHz
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// and then this divider-by-4 brings the effective clock down to 3.5 MHz
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// 1. always block at positive edge of clk_ula divides by 2
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// 2. counter flop further divides it by 2 unless the turbo mode is set
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always @(posedge clk_ula)
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begin
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if (counter=='0 | turbo)
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clk_cpu <= ~clk_cpu;
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counter <= counter - 1'b1;
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end
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endmodule
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@@ -0,0 +1,300 @@
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-- ZX Spectrum for Altera DE1
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--
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-- Copyright (c) 2009-2010 Mike Stirling
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
|
||||
--
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||||
-- * Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
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||||
--
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-- * Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
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||||
-- documentation and/or other materials provided with the distribution.
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--
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-- * Neither the name of the author nor the names of other contributors may
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||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
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||||
--
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||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_MISC.ALL; -- for AND_REDUCE
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use IEEE.NUMERIC_STD.ALL;
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entity i2c_loader is
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generic (
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-- Address of slave to be loaded
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device_address : integer := 16#1a#;
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-- Number of retries to allow before stopping
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num_retries : integer := 0;
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-- Length of clock divider in bits. Resulting bus frequency is
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-- CLK/2^(log2_divider + 2)
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log2_divider : integer := 6
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);
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port (
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CLK : in std_logic;
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nRESET : in std_logic;
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I2C_SCL : inout std_logic;
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I2C_SDA : inout std_logic;
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IS_DONE : out std_logic;
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IS_ERROR : out std_logic
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);
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end i2c_loader;
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architecture i2c_loader_arch of i2c_loader is
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type regs is array(0 to 19) of std_logic_vector(7 downto 0);
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constant init_regs : regs := (
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-- Left line in, 0dB, unmute
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X"00", X"17",
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-- Right line in, 0dB, unmute
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X"02", X"17",
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-- Left headphone out, 0dB
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X"04", X"79",
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-- Right headphone out, 0dB
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X"06", X"79",
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-- Audio path, DAC enabled, Line in, Bypass off, mic unmuted
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X"08", X"10",
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-- Digital path, Unmute, HP filter enabled
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X"0A", X"00",
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-- Power down mic, clkout and xtal osc
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X"0C", X"62",
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-- Format 16-bit I2S, no bit inversion or phase changes
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X"0E", X"02",
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-- Sampling control, 8 kHz USB mode (MCLK = 250fs * 6)
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X"10", X"0D",
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-- Activate
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X"12", X"01"
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);
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-- Number of bursts (i.e. total number of registers)
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constant burst_length : positive := 2;
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-- Number of bytes to transfer per burst
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constant num_bursts : positive := (init_regs'length / burst_length);
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type state_t is (Idle, Start, Data, Ack, Stop, Pause, Done);
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signal state : state_t;
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signal phase : std_logic_vector(1 downto 0);
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subtype nbit_t is integer range 0 to 7;
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signal nbit : nbit_t;
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subtype nbyte_t is integer range 0 to burst_length; -- +1 for address byte
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signal nbyte : nbyte_t;
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subtype thisbyte_t is integer range 0 to init_regs'length; -- +1 for "done"
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signal thisbyte : thisbyte_t;
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subtype retries_t is integer range 0 to num_retries;
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signal retries : retries_t;
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signal clken : std_logic;
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signal divider : std_logic_vector(log2_divider-1 downto 0);
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signal shiftreg : std_logic_vector(7 downto 0);
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signal scl_out : std_logic;
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signal sda_out : std_logic;
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signal nak : std_logic;
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begin
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-- Create open-drain outputs for I2C bus
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I2C_SCL <= '0' when scl_out = '0' else 'Z';
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I2C_SDA <= '0' when sda_out = '0' else 'Z';
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-- Status outputs are driven both ways
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IS_DONE <= '1' when state = Done else '0';
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IS_ERROR <= nak;
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-- Generate clock enable for desired bus speed
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clken <= AND_REDUCE(divider);
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process(nRESET,CLK)
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begin
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if nRESET = '0' then
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divider <= (others => '0');
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elsif falling_edge(CLK) then
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divider <= divider + '1';
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end if;
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end process;
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-- The I2C loader process
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process(nRESET,CLK,clken)
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begin
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if nRESET = '0' then
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scl_out <= '1';
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sda_out <= '1';
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state <= Idle;
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phase <= "00";
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nbit <= 0;
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nbyte <= 0;
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thisbyte <= 0;
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shiftreg <= (others => '0');
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nak <= '0'; -- No error
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retries <= num_retries;
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elsif rising_edge(CLK) and clken = '1' then
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-- Next phase by default
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phase <= phase + 1;
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-- STATE: IDLE
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if state = Idle then
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-- Start loading the device registers straight away
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-- A 'GO' bit could be polled here if required
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state <= Start;
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phase <= "00";
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scl_out <= '1';
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sda_out <= '1';
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-- STATE: START
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elsif state = Start then
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-- Generate START condition
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case phase is
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when "00" =>
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-- Drop SDA first
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sda_out <= '0';
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when "10" =>
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-- Then drop SCL
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scl_out <= '0';
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when "11" =>
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-- Advance to next state
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-- Shift register loaded with device slave address
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state <= Data;
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nbit <= 7;
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shiftreg <= std_logic_vector(to_unsigned(device_address,7)) & '0'; -- writing
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nbyte <= burst_length;
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when others =>
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null;
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end case;
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-- STATE: DATA
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elsif state = Data then
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-- Generate data
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case phase is
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when "00" =>
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-- Drop SCL
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scl_out <= '0';
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when "01" =>
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-- Output data and shift (MSb first)
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sda_out <= shiftreg(7);
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shiftreg <= shiftreg(6 downto 0) & '0';
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when "10" =>
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-- Raise SCL
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scl_out <= '1';
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when "11" =>
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-- Next bit or advance to next state when done
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if nbit = 0 then
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state <= Ack;
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else
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nbit <= nbit - 1;
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end if;
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when others =>
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null;
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end case;
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-- STATE: ACK
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elsif state = Ack then
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-- Generate ACK clock and check for error condition
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case phase is
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when "00" =>
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-- Drop SCL
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scl_out <= '0';
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when "01" =>
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-- Float data
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sda_out <= '1';
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when "10" =>
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-- Sample ack bit
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nak <= I2C_SDA;
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if I2C_SDA = '1' then
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-- Error
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nbyte <= 0; -- Close this burst and skip remaining registers
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thisbyte <= init_regs'length;
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else
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-- Hold ACK to avoid spurious stops - this seems to fix a
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-- problem with the Wolfson codec which releases the ACK
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-- right on the falling edge of the clock pulse. It looks like
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-- the device interprets this is a STOP condition and then fails
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-- to acknowledge the next byte. We can avoid this by holding the
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-- ACK condition for a little longer.
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sda_out <= '0';
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end if;
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-- Raise SCL
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scl_out <= '1';
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when "11" =>
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-- Advance to next state
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if nbyte = 0 then
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-- No more bytes in this burst - generate a STOP
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state <= Stop;
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else
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-- Generate next byte
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state <= Data;
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nbit <= 7;
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shiftreg <= init_regs(thisbyte);
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nbyte <= nbyte - 1;
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thisbyte <= thisbyte + 1;
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end if;
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when others =>
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null;
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end case;
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-- STATE: STOP
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elsif state = Stop then
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-- Generate STOP condition
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case phase is
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when "00" =>
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-- Drop SCL first
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scl_out <= '0';
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when "01" =>
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-- Drop SDA
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sda_out <= '0';
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when "10" =>
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-- Raise SCL
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scl_out <= '1';
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when "11" =>
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if thisbyte = init_regs'length then
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-- All registers done, advance to finished state. This will
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-- bring SDA high while SCL is still high, completing the STOP
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-- condition
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state <= Done;
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else
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-- Load the next register after a short delay
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state <= Pause;
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end if;
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when others =>
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null;
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end case;
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-- STATE: PAUSE
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elsif state = Pause then
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-- Delay for one cycle of 'phase' then start the next burst
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scl_out <= '1';
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sda_out <= '1';
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if phase = "11" then
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state <= Start;
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end if;
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-- STATE: DONE
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else
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-- Finished
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scl_out <= '1';
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sda_out <= '1';
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if nak = '1' and retries > 0 then
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-- We can retry in the event of a NAK in case the
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-- slave got out of sync for some reason
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retries <= retries - 1;
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state <= Idle;
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end if;
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end if;
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end if;
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end process;
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end i2c_loader_arch;
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@@ -0,0 +1,191 @@
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-- ZX Spectrum for Altera DE1
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||||
--
|
||||
-- Copyright (c) 2009-2010 Mike Stirling
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
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entity i2s_intf is
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generic(
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mclk_rate : positive := 12000000;
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sample_rate : positive := 8000;
|
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preamble : positive := 1; -- I2S
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word_length : positive := 16
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);
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port (
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||||
-- 2x MCLK in (e.g. 24 MHz for WM8731 USB mode)
|
||||
CLK : in std_logic;
|
||||
nRESET : in std_logic;
|
||||
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-- Parallel IO
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||||
PCM_INL : out std_logic_vector(word_length - 1 downto 0);
|
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PCM_INR : out std_logic_vector(word_length - 1 downto 0);
|
||||
PCM_OUTL : in std_logic_vector(word_length - 1 downto 0);
|
||||
PCM_OUTR : in std_logic_vector(word_length - 1 downto 0);
|
||||
|
||||
-- Codec interface (right justified mode)
|
||||
-- MCLK is generated at half of the CLK input
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||||
I2S_MCLK : out std_logic;
|
||||
-- LRCLK is equal to the sample rate and is synchronous to
|
||||
-- MCLK. It must be related to MCLK by the oversampling ratio
|
||||
-- given in the codec datasheet.
|
||||
I2S_LRCLK : out std_logic;
|
||||
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||||
-- Data is shifted out on the falling edge of BCLK, sampled
|
||||
-- on the rising edge. The bit rate is determined such that
|
||||
-- it is fast enough to fit preamble + word_length bits into
|
||||
-- each LRCLK half cycle. The last cycle of each word may be
|
||||
-- stretched to fit to LRCLK. This is OK at least for the
|
||||
-- WM8731 codec.
|
||||
-- The first falling edge of each timeslot is always synchronised
|
||||
-- with the LRCLK edge.
|
||||
I2S_BCLK : out std_logic;
|
||||
-- Output bitstream
|
||||
I2S_DOUT : out std_logic;
|
||||
-- Input bitstream
|
||||
I2S_DIN : in std_logic
|
||||
);
|
||||
end i2s_intf;
|
||||
|
||||
architecture i2s_intf_arch of i2s_intf is
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||||
constant ratio_mclk_fs : positive := (mclk_rate / sample_rate);
|
||||
constant lrdivider_top : positive := (ratio_mclk_fs / 2) - 1;
|
||||
constant bdivider_top : positive := (ratio_mclk_fs / 8 / (preamble + word_length) * 2) - 1;
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constant nbits : positive := preamble + word_length;
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subtype lrdivider_t is integer range 0 to lrdivider_top;
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||||
subtype bdivider_t is integer range 0 to bdivider_top;
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subtype bitcount_t is integer range 0 to nbits;
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||||
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||||
signal lrdivider : lrdivider_t := lrdivider_top;
|
||||
signal bdivider : bdivider_t := bdivider_top;
|
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signal bitcount : bitcount_t := nbits;
|
||||
|
||||
signal mclk_r : std_logic;
|
||||
signal lrclk_r : std_logic;
|
||||
signal bclk_r : std_logic;
|
||||
|
||||
-- Shift register is long enough for the number of data bits
|
||||
-- plus the preamble, plus an extra bit on the right to register
|
||||
-- the incoming data
|
||||
signal shiftreg : std_logic_vector(nbits downto 0);
|
||||
begin
|
||||
I2S_MCLK <= mclk_r;
|
||||
I2S_LRCLK <= lrclk_r;
|
||||
I2S_BCLK <= bclk_r;
|
||||
I2S_DOUT <= shiftreg(nbits); -- data goes out MSb first
|
||||
|
||||
process(nRESET,CLK)
|
||||
begin
|
||||
if nRESET = '0' then
|
||||
PCM_INL <= (others => '0');
|
||||
PCM_INR <= (others => '0');
|
||||
|
||||
-- Preload down-counters for clock generation
|
||||
lrdivider <= lrdivider_top;
|
||||
bdivider <= bdivider_top;
|
||||
bitcount <= nbits;
|
||||
|
||||
mclk_r <= '0';
|
||||
lrclk_r <= '0';
|
||||
bclk_r <= '0';
|
||||
shiftreg <= (others => '0');
|
||||
elsif rising_edge(CLK) then
|
||||
-- Generate MCLK at half input clock rate
|
||||
mclk_r <= not mclk_r;
|
||||
|
||||
-- Generate LRCLK at rate specified by codec configuration
|
||||
if lrdivider = 0 then
|
||||
-- LRCLK divider has reached 0 - start again from the top
|
||||
lrdivider <= lrdivider_top;
|
||||
|
||||
-- Generate LRCLK edge and sync the BCLK counter
|
||||
lrclk_r <= not lrclk_r;
|
||||
bclk_r <= '0';
|
||||
bitcount <= nbits; -- 1 extra required for setup
|
||||
bdivider <= bdivider_top;
|
||||
|
||||
-- Load shift register with output data padding preamble
|
||||
-- with 0s. Load output buses with input word from the
|
||||
-- previous timeslot.
|
||||
shiftreg(nbits downto nbits - preamble + 1) <= (others => '0');
|
||||
if lrclk_r = '0' then
|
||||
-- Previous channel input is LEFT. This is available in the
|
||||
-- shift register at the end of a cycle, right justified
|
||||
PCM_INL <= shiftreg(word_length - 1 downto 0);
|
||||
-- Next channel to output is RIGHT. Load this into the
|
||||
-- shift register at the start of a cycle, left justified
|
||||
shiftreg(word_length downto 1) <= PCM_OUTR;
|
||||
else
|
||||
-- Previous channel input is RIGHT
|
||||
PCM_INR <= shiftreg(word_length - 1 downto 0);
|
||||
-- Next channel is LEFT
|
||||
shiftreg(word_length downto 1) <= PCM_OUTL;
|
||||
end if;
|
||||
else
|
||||
-- Decrement the LRCLK counter
|
||||
lrdivider <= lrdivider - 1;
|
||||
|
||||
-- Generate BCLK at a suitable rate to fit the required number
|
||||
-- of bits into each timeslot. Data is changed on the falling edge,
|
||||
-- sampled on the rising edge
|
||||
if bdivider = 0 then
|
||||
-- If all bits have been output for this phase then
|
||||
-- stop and wait to sync back up with LRCLK
|
||||
if bitcount > 0 then
|
||||
-- Reset
|
||||
bdivider <= bdivider_top;
|
||||
|
||||
-- Toggle BCLK
|
||||
bclk_r <= not bclk_r;
|
||||
if bclk_r = '0' then
|
||||
-- Rising edge - shift in current bit and decrement bit counter
|
||||
bitcount <= bitcount - 1;
|
||||
shiftreg(0) <= I2S_DIN;
|
||||
else
|
||||
-- Falling edge - shift out next bit
|
||||
shiftreg(nbits downto 1) <= shiftreg(nbits - 1 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
else
|
||||
-- Decrement the BCLK counter
|
||||
bdivider <= bdivider - 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
end i2s_intf_arch;
|
||||
|
||||
+10
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone II" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="c1" direction="output" scope="external" source="clock" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
@@ -0,0 +1,5 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.0"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_inst.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
|
||||
@@ -0,0 +1,326 @@
|
||||
// megafunction wizard: %ALTPLL%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altpll
|
||||
|
||||
// ============================================================
|
||||
// File Name: pll.v
|
||||
// Megafunction Name(s):
|
||||
// altpll
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module pll (
|
||||
inclk0,
|
||||
c0,
|
||||
c1);
|
||||
|
||||
input inclk0;
|
||||
output c0;
|
||||
output c1;
|
||||
|
||||
wire [5:0] sub_wire0;
|
||||
wire [0:0] sub_wire5 = 1'h0;
|
||||
wire [1:1] sub_wire2 = sub_wire0[1:1];
|
||||
wire [0:0] sub_wire1 = sub_wire0[0:0];
|
||||
wire c0 = sub_wire1;
|
||||
wire c1 = sub_wire2;
|
||||
wire sub_wire3 = inclk0;
|
||||
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
|
||||
|
||||
altpll altpll_component (
|
||||
.inclk (sub_wire4),
|
||||
.clk (sub_wire0),
|
||||
.activeclock (),
|
||||
.areset (1'b0),
|
||||
.clkbad (),
|
||||
.clkena ({6{1'b1}}),
|
||||
.clkloss (),
|
||||
.clkswitch (1'b0),
|
||||
.configupdate (1'b0),
|
||||
.enable0 (),
|
||||
.enable1 (),
|
||||
.extclk (),
|
||||
.extclkena ({4{1'b1}}),
|
||||
.fbin (1'b1),
|
||||
.fbmimicbidir (),
|
||||
.fbout (),
|
||||
.fref (),
|
||||
.icdrclk (),
|
||||
.locked (),
|
||||
.pfdena (1'b1),
|
||||
.phasecounterselect ({4{1'b1}}),
|
||||
.phasedone (),
|
||||
.phasestep (1'b1),
|
||||
.phaseupdown (1'b1),
|
||||
.pllena (1'b1),
|
||||
.scanaclr (1'b0),
|
||||
.scanclk (1'b0),
|
||||
.scanclkena (1'b1),
|
||||
.scandata (1'b0),
|
||||
.scandataout (),
|
||||
.scandone (),
|
||||
.scanread (1'b0),
|
||||
.scanwrite (1'b0),
|
||||
.sclkout0 (),
|
||||
.sclkout1 (),
|
||||
.vcooverrange (),
|
||||
.vcounderrange ());
|
||||
defparam
|
||||
altpll_component.clk0_divide_by = 1080,
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 1007,
|
||||
altpll_component.clk0_phase_shift = "0",
|
||||
altpll_component.clk1_divide_by = 27,
|
||||
altpll_component.clk1_duty_cycle = 50,
|
||||
altpll_component.clk1_multiply_by = 14,
|
||||
altpll_component.clk1_phase_shift = "0",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.inclk0_input_frequency = 37037,
|
||||
altpll_component.intended_device_family = "Cyclone II",
|
||||
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
|
||||
altpll_component.lpm_type = "altpll",
|
||||
altpll_component.operation_mode = "NORMAL",
|
||||
altpll_component.port_activeclock = "PORT_UNUSED",
|
||||
altpll_component.port_areset = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkloss = "PORT_UNUSED",
|
||||
altpll_component.port_clkswitch = "PORT_UNUSED",
|
||||
altpll_component.port_configupdate = "PORT_UNUSED",
|
||||
altpll_component.port_fbin = "PORT_UNUSED",
|
||||
altpll_component.port_inclk0 = "PORT_USED",
|
||||
altpll_component.port_inclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_locked = "PORT_UNUSED",
|
||||
altpll_component.port_pfdena = "PORT_UNUSED",
|
||||
altpll_component.port_phasecounterselect = "PORT_UNUSED",
|
||||
altpll_component.port_phasedone = "PORT_UNUSED",
|
||||
altpll_component.port_phasestep = "PORT_UNUSED",
|
||||
altpll_component.port_phaseupdown = "PORT_UNUSED",
|
||||
altpll_component.port_pllena = "PORT_UNUSED",
|
||||
altpll_component.port_scanaclr = "PORT_UNUSED",
|
||||
altpll_component.port_scanclk = "PORT_UNUSED",
|
||||
altpll_component.port_scanclkena = "PORT_UNUSED",
|
||||
altpll_component.port_scandata = "PORT_UNUSED",
|
||||
altpll_component.port_scandataout = "PORT_UNUSED",
|
||||
altpll_component.port_scandone = "PORT_UNUSED",
|
||||
altpll_component.port_scanread = "PORT_UNUSED",
|
||||
altpll_component.port_scanwrite = "PORT_UNUSED",
|
||||
altpll_component.port_clk0 = "PORT_USED",
|
||||
altpll_component.port_clk1 = "PORT_USED",
|
||||
altpll_component.port_clk2 = "PORT_UNUSED",
|
||||
altpll_component.port_clk3 = "PORT_UNUSED",
|
||||
altpll_component.port_clk4 = "PORT_UNUSED",
|
||||
altpll_component.port_clk5 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena2 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena3 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena4 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena5 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk0 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk2 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk3 = "PORT_UNUSED";
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.174999"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "14.000000"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "0"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "50.000"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
|
||||
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.17500000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "14.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1080"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1007"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "14"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
|
||||
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
// Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
+110
@@ -0,0 +1,110 @@
|
||||
//============================================================================
|
||||
// PS/2 keyboard scan-code reader
|
||||
//
|
||||
// Copyright (C) 2014-2016 Goran Devic
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License along
|
||||
// with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
//============================================================================
|
||||
module ps2_keyboard
|
||||
(
|
||||
input wire clk,
|
||||
input wire nreset, // Active low reset
|
||||
input wire PS2_CLK, // PS/2 keyboard clock line
|
||||
input wire PS2_DAT, // PS/2 keyboard data line
|
||||
|
||||
output wire [7:0] scan_code,// Completed keyboard scan code
|
||||
output reg scan_code_ready, // Active for 1 clock: scan code is ready
|
||||
output reg scan_code_error // Error receiving keyboard data
|
||||
);
|
||||
|
||||
reg [7:0] clk_filter;
|
||||
reg ps2_clk_in;
|
||||
|
||||
reg clk_edge;
|
||||
reg [3:0] bit_count;
|
||||
|
||||
// Shift register contains all the bits that are read so far; scan_code simply
|
||||
// mirrors it and becomes valid only when "scan_code_ready" is set
|
||||
reg [8:0] shiftreg;
|
||||
assign scan_code = shiftreg[7:0];
|
||||
|
||||
// Compute parity on the fly; we only need it after the last bit is stored
|
||||
wire parity;
|
||||
assign parity = ^shiftreg[8:0];
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// Filter the PS/2 clock signal since it might have a noise (false '1')
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
always @(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset) begin
|
||||
ps2_clk_in <= 1;
|
||||
clk_filter <= 8'b1;
|
||||
clk_edge <= 0;
|
||||
end
|
||||
else begin
|
||||
// Filter in a new keyboard clock sample
|
||||
clk_filter <= { PS2_CLK, clk_filter[7:1] };
|
||||
clk_edge <= 0;
|
||||
|
||||
if (clk_filter==8'b1)
|
||||
ps2_clk_in <= 1;
|
||||
else if (clk_filter==8'b0) begin
|
||||
// Filter clock is low, check for edge
|
||||
if (ps2_clk_in==1)
|
||||
clk_edge <= 1;
|
||||
ps2_clk_in <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// State machine to process bits of PS/2 data
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
always @(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset) begin
|
||||
bit_count <= '0;
|
||||
shiftreg <= '0;
|
||||
scan_code_ready <= 0;
|
||||
scan_code_error <= 0;
|
||||
end
|
||||
else begin
|
||||
scan_code_ready <= 0;
|
||||
scan_code_error <= 0;
|
||||
// We have a new valid clocked bit from the keyboard
|
||||
if (clk_edge==1) begin
|
||||
// Start condition, the bit count is 0
|
||||
if (bit_count==0 && PS2_DAT==0)
|
||||
bit_count <= bit_count + 4'h1;
|
||||
else begin
|
||||
// Collecting up to 8 data bits and a parity bit
|
||||
if (bit_count < 10) begin
|
||||
bit_count <= bit_count + 4'h1;
|
||||
shiftreg <= { PS2_DAT, shiftreg[8:1] };
|
||||
end
|
||||
else
|
||||
// Finalize: both the calculated parity and the stop bits should be '1'
|
||||
begin
|
||||
bit_count <= '0;
|
||||
scan_code_ready <= { PS2_DAT, parity} == 2'b11;
|
||||
scan_code_error <= { PS2_DAT, parity} != 2'b11;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.0"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram8.v"]
|
||||
+177
@@ -0,0 +1,177 @@
|
||||
// megafunction wizard: %RAM: 1-PORT%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altsyncram
|
||||
|
||||
// ============================================================
|
||||
// File Name: ram8.v
|
||||
// Megafunction Name(s):
|
||||
// altsyncram
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module ram8 (
|
||||
address,
|
||||
clock,
|
||||
data,
|
||||
wren,
|
||||
q);
|
||||
|
||||
input [12:0] address;
|
||||
input clock;
|
||||
input [7:0] data;
|
||||
input wren;
|
||||
output [7:0] q;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri1 clock;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire [7:0] sub_wire0;
|
||||
wire [7:0] q = sub_wire0[7:0];
|
||||
|
||||
altsyncram altsyncram_component (
|
||||
.address_a (address),
|
||||
.clock0 (clock),
|
||||
.data_a (data),
|
||||
.wren_a (wren),
|
||||
.q_a (sub_wire0),
|
||||
.aclr0 (1'b0),
|
||||
.aclr1 (1'b0),
|
||||
.address_b (1'b1),
|
||||
.addressstall_a (1'b0),
|
||||
.addressstall_b (1'b0),
|
||||
.byteena_a (1'b1),
|
||||
.byteena_b (1'b1),
|
||||
.clock1 (1'b1),
|
||||
.clocken0 (1'b1),
|
||||
.clocken1 (1'b1),
|
||||
.clocken2 (1'b1),
|
||||
.clocken3 (1'b1),
|
||||
.data_b (1'b1),
|
||||
.eccstatus (),
|
||||
.q_b (),
|
||||
.rden_a (1'b1),
|
||||
.rden_b (1'b1),
|
||||
.wren_b (1'b0));
|
||||
defparam
|
||||
altsyncram_component.clock_enable_input_a = "BYPASS",
|
||||
altsyncram_component.clock_enable_output_a = "BYPASS",
|
||||
`ifdef NO_PLI
|
||||
altsyncram_component.init_file = "test_scr.rif"
|
||||
`else
|
||||
altsyncram_component.init_file = "test_scr.hex"
|
||||
`endif
|
||||
,
|
||||
altsyncram_component.intended_device_family = "Cyclone II",
|
||||
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
|
||||
altsyncram_component.lpm_type = "altsyncram",
|
||||
altsyncram_component.numwords_a = 8192,
|
||||
altsyncram_component.operation_mode = "SINGLE_PORT",
|
||||
altsyncram_component.outdata_aclr_a = "NONE",
|
||||
altsyncram_component.outdata_reg_a = "UNREGISTERED",
|
||||
altsyncram_component.power_up_uninitialized = "FALSE",
|
||||
altsyncram_component.widthad_a = 13,
|
||||
altsyncram_component.width_a = 8,
|
||||
altsyncram_component.width_byteena_a = 1;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Clken NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
|
||||
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
|
||||
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
||||
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: MIFfilename STRING "test_scr.hex"
|
||||
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
|
||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
|
||||
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: RegData NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: WidthAddr NUMERIC "13"
|
||||
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: rden NUMERIC "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: INIT_FILE STRING "test_scr.hex"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
|
||||
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
||||
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
|
||||
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
|
||||
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
|
||||
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
|
||||
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
|
||||
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
|
||||
// Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]"
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
|
||||
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
|
||||
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
|
||||
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
|
||||
// Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0
|
||||
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
|
||||
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
|
||||
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL ram8.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL ram8.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL ram8.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL ram8.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL ram8_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL ram8_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
@@ -0,0 +1,217 @@
|
||||
:20000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00
|
||||
:20002000C1C1C00000000003800000000000000380000000000003800000000000038383EC
|
||||
:20004000C181C0000000000003FFFFFFFFFE0000E00000008000F00000000080000381C38A
|
||||
:20006000CC3300000002804000000000FFE000FFFF0000FFFFE0000080000000C000CC33C5
|
||||
:20008000CC3300002042877F0000FEEE00FFF000F1FFE1000381FE0FFFFFFF0000C0CC3300
|
||||
:2000A000CC3301004000001E00FFFF80240FFC000080000000000000000000FF0000CC33B7
|
||||
:2000C000CC3304000000003F7C00F080000003F800E0630C31AEC3CF639FFF0FC000CC3368
|
||||
:2000E000CC33040007800001FFF800C0001001FF00E080FE64791C871998300F8000CC3361
|
||||
:20010000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
|
||||
:20012000C386E000000000076000000000000007600000000000076000000000000761C336
|
||||
:20014000C7638000000004001FFFFFFFFFF80000F8000000F800FE00000000C00001C6E386
|
||||
:20016000CC330000000104A0801000007FF000F7FF0080FFFFF07800BF000000E000CC3362
|
||||
:20018000CC330000015101FE0001FC5E007FF800FC3F800001007807FFFFFFC000C0CC3386
|
||||
:2001A000CC3300011000001E00FFFF801007FE000000000000600000000F007F0000CC3391
|
||||
:2001C000CC3300200000001FFC00E1D0000001F800E0630C63DD8F0F779FFB0FC000CC332F
|
||||
:2001E000CC3300003FF80001FFF180D0004401FF80F081DC663938FF1D9C70078000CC33F2
|
||||
:20020000C0000000000000000000000000000000000000000000000000000000000000031B
|
||||
:20022000C70E7FFFFFFFFFFE7FFFFFFFFFFFFFFE7FFFFFFFFFFFFE7FFFFFFFFFFFFE70E3B6
|
||||
:20024000CE73000000000A007FFFFFFFF8000000FC000000FE00FF80000000E00000CE7345
|
||||
:20026000CC33000001000A41402800007FF000FBFF0080FFFFFFFE00FFC00000F000CC3339
|
||||
:20028000CC330000004000FC4007FEDE001FFC00FF07000000003007C07FFFE000E0CC33AB
|
||||
:2002A000CC3300004000003F01FF01C0AB07FF0000000000007FFFFFFFFF003F0000CC3395
|
||||
:2002C000CC3340000000001FFE00C6D8000021F800E06308C3B1BC0F3C00030FC000CC3374
|
||||
:2002E000CC330800E0FE0001FFC200B0001000FFC0F0E0E7E73938FF1FCEF0070000CC33E7
|
||||
:20030000C0000000000000000000000000000000000000000000000000000000000000031A
|
||||
:20032000CE1C3FFFFFFFFFFC3FFFFFFFFFFFFFFC3FFFFFFFFFFFFC3FFFFFFFFFFFFC387350
|
||||
:20034000CC33000000000400FFFFFFF0E0000000FE000000FF00FFE0000000E00000CC3312
|
||||
:20036000CC33000002800400801000003FF800FCFF00C0FFFFFFFF80FFF00000F000CC331C
|
||||
:20038000CC33004403B8203CA00EFFDF001FFE00FF02000000000003000FFFF000E0CC3379
|
||||
:2003A000CC330012A800003F01F800001007FF8000800000005FFFFFFFEE003F0000CC33AE
|
||||
:2003C000CC33A0000000000FFE008818000051F800E063798019F04F1C00031FC000CC33F7
|
||||
:2003E000CC3314019F1F0001FF0400B000AA00FFE0F86060E7991CC303C7B0078000CC33D7
|
||||
:20040000C01C3FFFFFFFFFFC3FFFFFFFFFFFFFFC3FFFFFFFFFFFFC3FFFFFFFFFFFFC3803ED
|
||||
:20042000CC38000000000000000000000000000000000000000000000000000000001C3369
|
||||
:20044000CC33000000000000FFFFFDFE00000000FF000000FF80FFF8000000F00000CC3340
|
||||
:20046000CC33000001000000000000000FF800FF3F00F8FFFFFFFFC0FFF80000F000CC339D
|
||||
:20048000CC33000A0840501C401EF7E1001FFE00FF800000000000000003FFF800F0CC33E4
|
||||
:2004A000CC3300284000003F01C000004403FFC000C0000700C00000001C001F8000CC338E
|
||||
:2004C000CC33400000000007FE009C38000023FC00E063F1FC19E1EF0F9FFB1FC000CC3345
|
||||
:2004E000CC330807FFE78003FC0410700010007FF0F8623066998EE731E330078000CC33BE
|
||||
:20050000C03E7FFFFFFFFFFE7FFFFFFFFFFFFFFE7FFFFFFFFFFFFE7FFFFFFFFFFFFE7C037E
|
||||
:20052000CE70000000000000000000000000000000000000000000000000000000000E73FC
|
||||
:20054000CC33000000000003F7EFF9FFC0000000FF000000FFC0FFFC000000F00000CC3353
|
||||
:20056000CC330000000000440000003C01FC00FFDF00FCFFFFFFFFE0FFF80000F8F0CC336B
|
||||
:20058000CC3300041550201C003839C0001FFE00FF800000000000000001FFFC00F8CC33F7
|
||||
:2005A000CC3300111000003F008003009001FFE000E0FFCFFEC000000018001F8000CC33C7
|
||||
:2005C000CC33010000000007FF187F98020003FC00E06381CF19C3FF179FFF3FC000CC33C4
|
||||
:2005E000CE73001C00F9C003F80421F80044003FF0F86331E699C7E73CF83007C000CE7335
|
||||
:20060000C077600000000006E000000000000006E0000000000006E0000000000006EE039A
|
||||
:20062000C6E07FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE076347
|
||||
:20064000CC33000000000007E383C0FFE0000000FFF80000FFC0FFFE000000F00000CC33ED
|
||||
:20066000CC33000020000125C0000FFC01FC00FFEF00FEF03FFFFFE0FFFC0000FF00CC337B
|
||||
:20068000CC3301000840001E007EFE80100FFC00FF800000000000000000FFFE00FCCC3366
|
||||
:2006A000CC3304004000003F100004401000FFF000E0FF8CFC9FFFFFFE18031F8000CC33AA
|
||||
:2006C000CC33000000000003FFE6FFD0050003FC00C06201E399873F1F98071FC000CC335F
|
||||
:2006E000C6E303E00F1EF003F00840FC0010001FF0FC63B3E699E1E73E7F3007E000C763A4
|
||||
:20070000C0E3800000000001C000000000000001C0000000000001C0000000000001C703A8
|
||||
:20072000C1C0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0383CE
|
||||
:20074000CC3300000001000F8000003FE0000000FFFE0000FFE0FFFF000000FF0000CC3313
|
||||
:20076000CC3300005001008380003FFC00FFC0FFF700FFC007FFFFF0FFFDF800FF80CC3310
|
||||
:20078000CC3302800000001E007EF900000FFC00FF80000000000000000003FE00FECC33BB
|
||||
:2007A000CC330A000000003F3900056000003FF000E0C10C19B7FFEFFF18070FC000CC33CD
|
||||
:2007C000CC33000000000001FFF8FFD0020003FC00C0E03F60D90E031998010FC000CC33A9
|
||||
:2007E000C1C300003FEF7F03801082FC0000000FF8FC63F3C699F0C7373FB007E000C383F5
|
||||
:20080000C38300007FF3BFFF0061040300000407F8FC6323C698BC073399F007F000C1C31D
|
||||
:20082000CC3300000000007FFFF0FFDE7F77FE00F8F006361E1E00E7FF0C000100F8CC3330
|
||||
:20084000CC33400000003FE4FF0024EEFF7E0007C0F018F1D9843C7063F0007FE0F8CC3336
|
||||
:20086000CC3305000007FFFEFBC47E7F7F0000FF00000C7F8060FC3FFEC0003F0000CC3394
|
||||
:20088000CC330400400FFF7EFFB7FDEF004001000000FF007FE038FF0F00000100E0CC3322
|
||||
:2008A000C38300A00801F7BF84FE91F8111000FF000000FF8000000000001FBFFFC0C1C3C8
|
||||
:2008C000CC33220020000F3FFF8FFFE006200300000000FF00000000000000EFF800CC330E
|
||||
:2008E000CC333BF80FFFFFFFC1FFF80009E0007F000000EF00000000000000000000CC33AC
|
||||
:20090000C7630000F801CFFFCF810803C0000A01F8FC636773976F07319C7007F000C6E3A5
|
||||
:20092000CC330000040000FFFFC7FFDDFEF7E001F8F00E6C07300001DF8E000100F8CC333E
|
||||
:20094000CC33A08000007FE8FF0024EEFEFC0207C0F018F8C1E61CE1F1FC007FE0F8CC3356
|
||||
:20096000CC3302000007FFFDF7C47F7EFE0000FF00800C7FFE60761FFFC0001F0080CC3363
|
||||
:20098000CC330000010FFF7DFF8FFDEE102001000000F0C003F87877FE00000700E0CC33A4
|
||||
:2009A000C76320408000F7BF95FE90F81120007F000000FF8003E00000001FBFFFC0C6E304
|
||||
:2009C000CC33320000001EFFFF0FFFC009400300000000F7C0000000000000EFF000CC331B
|
||||
:2009E000CC333C1C0FFFFFFF03FFF00004C0003F000000F700000000000000000000CC33A9
|
||||
:200A0000CE730003C01EF0FF30061803F0000401F8FC63663F9FE7E7318C3007F000CE73F1
|
||||
:200A2000CC330000000001FFF9FFFFBBFEF7FE01F0F80C78E36FFF0387C7000380F8CC3389
|
||||
:200A4000CC33400000007FE0FF0024FDFDFC050780E018DC03E78DC3F838007FE0F0CC33C7
|
||||
:200A6000CC3300000007FFFBEFEC7FBFFC4000FF00C01C00FFE4330E1FE0001F0080CC3385
|
||||
:200A8000CC3300200007FEFBFF7FCAF6084803000000C0E0006CEC7DF800000F00E0CC334B
|
||||
:200AA000CE73F00022002F7FC1FDA0F81120003F000000FFC00FF819E0003FBFFF80CE73F2
|
||||
:200AC000CC333200000039FFFF1FFF8001400300000000FBE0000000000000FFE000CC3313
|
||||
:200AE000CC3379CE0FFFFFFE03FFF00004C0001F000000FB00000000000000000000CC33D6
|
||||
:200B0000CC33000E01FF3FFF0C083003F8000001FCFCC3C70F0FC1E7318C0007FE00CC3341
|
||||
:200B2000CC334000040003FFF1FFFFBBFDEF3001F0F81CD1F1FFFFC700F3000780FCCC33A9
|
||||
:200B4000CC3300000000FFD1FC0024FDFBF8020700E018EE1F658F8719F000FFF0F0CC3346
|
||||
:200B6000CC330008200FFFF7DFCEFFBFF81000FF00C0180007E6191719F0001F0080CC333B
|
||||
:200B8000CC3310000803FEFBE0FFC0F600400300000000F00066C60E0000001F00E0CC3342
|
||||
:200BA000CC333000A8002EFFABFD90F808A0007F000000FFC03FFE7FF80E3FBFFF80CC33DD
|
||||
:200BC000CC333300000067FFFE3FFF0000000300000000FBF01C0000000000FFC000CC3379
|
||||
:200BE000CC3363F20FFFFFFC07FFE0000AE00007000000FB00000000000000000000CC33C7
|
||||
:200C0000CC3301F007FFDFFF03F0E007F6000000FCFCDDCD83E60067398C0007FF80CC3374
|
||||
:200C2000CC3300000A0007FFCFFFFF77F3EF0003F0F818F319BE01FFF87F000FC0FCCC3371
|
||||
:200C4000CC3301010000FFBFF3FFDBFDF7F0001FC0E01C67FE670F0E1FC000FFFCF0CC3397
|
||||
:200C6000CC330000020FFFEFDF847EDFF10000FF00E0380000F77F3CF838000F00C0CC33FE
|
||||
:200C8000CC3300000003FDF7C07FE1F408800300000000F800678307000000DF00E0CC3318
|
||||
:200CA000CC33140020002DFED7F981F0089000FF000000FEE07FFFFFFC3FBFDFFF00CC33CC
|
||||
:200CC000CC33190004001FFFFC3FFE000FC00300000000FBF07FF0C0000000FFC000CC33F7
|
||||
:200CE000CC3347FF07FFFFF80FFFE00018F00001000000FD00000000000000000000CC33BF
|
||||
:200D0000CC330000180FEFFF0007C00FF7600000FCF8FF8DBFBF0066198C0003FFC0CC33C8
|
||||
:200D2000CC33000004000FFFBCFFFF77CFDF0003E0F818F30CF7807FFC1F001FE0FCCC33C6
|
||||
:200D4000CC3300000001FFFFCFC442FBEFE0003FF0C00C63F0661F1FFFC000FFFEF8CC3351
|
||||
:200D6000CC330000000FFFDFBF8C7EDFE040007F00E07000001FC7E1F1F0000F00C0CC337A
|
||||
:200D8000CE7320408003FBEFC07FF1F400900300000000FC00C30199800003DF00E0CE73B2
|
||||
:200DA000CC335C01DC000DFDFFF3C1F0049801FF000000FEE0FFFFFFFE7FFFDFFF00CC337E
|
||||
:200DC000CC331D600401FFFFF87FFE0018300100000000F7F9FFBFF0000000FF8000CC33BA
|
||||
:200DE000CC33CC0003FFFFF01FFFC00031F80000000000FD00000000000000000000CC3334
|
||||
:200E0000CC3300002000F1FF003F001FEFF600E0FCF8FB99FFDFFFE78D9C0003FFE0CC334A
|
||||
:200E2000CC33404000001FFF63FFC2F7BFBF0003E0F818B34CE3E00F0E03003FF0FCCC337D
|
||||
:200E4000CC3300000003FFFFBEEC7EFBDFC0007FFCC00C6000643E3FFEC000FFFEFCCC3392
|
||||
:200E6000CC330010000FFFDF7FDAFEEFC000003F00F063FFC00701F063E0000700C0CC331E
|
||||
:200E8000C6E350000003FBEFC07FEFF409100300000000FE00FF03FFC00007DF00E0C7637F
|
||||
:200EA000CC33260020000BF3FFE3E3F00C8801FF000000FEF1FFFFFFFFFFFFDFFE00CC33E1
|
||||
:200EC000CC3315F00607FFFFF07FFC0010100100000000F7FBFFFFFC000000FF8000CC330D
|
||||
:200EE000CC33186200FFFFC03FFFC00061FC0000000000FD00FFFFFFFFFFFFFFFF00CC336C
|
||||
:200F0000CC33200040000EFF03FC007F9F7F0780F8F8C71BF8C7FFE7E78C0001FFFDCC335C
|
||||
:200F2000CC33000000001FF11FFFDBEF7F7F0007E0F018B3F8C0F8C30700007FF0FCCC3336
|
||||
:200F4000CC3302000003FFFF7DC6C0FFBF80007FFE800C600060700000C0007FFFFECC33DA
|
||||
:200F6000CC330000000FFFBEFFB1FEEF804000FF00F87FFFFE001FFC0780000300C0CC3372
|
||||
:200F8000C1C320400203FBDF987FC3F809100100000000FF00FF03E0C0000FDF00C0C3830D
|
||||
:200FA000CC332200A80017CFFFC7FFF0151803FF000000FCFBFFFFFFFFFFFFDFFC00CC33D3
|
||||
:200FC000CC333E100F1FFFFFE0FFFC001FF00000000000F7FFFFFFFE000000FF8000CC333E
|
||||
:200FE000CC3321FC0007FC00FFFF8000E3FE0000000000FB01FFFFFFFFFFFFFFFF80CC3300
|
||||
:20100000CC3343FBC03FFF01FFFF8000C7407000FF0000FB038000000000000001C0CC3362
|
||||
:20102000CC3337FC1C03C0400000011C100040201FFF0000033FDFB8EEEEEF38FCC0CC331D
|
||||
:20104000CC33004F9B8FC6373047C047B03800300007FF0003FFFFFFFFFFFFFFFF80CC3305
|
||||
:20106000C380FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0383C3
|
||||
:20108000C0E1C0000000000001C0000000000001C0000000000001C0000000000001C703E1
|
||||
:2010A000000000000000000000000000000000000000000000000000000000000000000030
|
||||
:2010C000000000000000000000000000000000000000000000000000000000000000000010
|
||||
:2010E0000000000000000000000000000000000000000000000000000000000000000000F0
|
||||
:20110000CC330361810FFF03FFFF1000C7B0B8E0FF0000F7030000000000000000C0CC3305
|
||||
:20112000CC3367F83C3F01801FC1EE384C7EC0200FFF0000031F9FB8EE4EE738FCC0CC3308
|
||||
:20114000CC33004F0A3FCE36101F089E607000000007FF0001FFFFFFFFFFFFFFFF00CC3351
|
||||
:20116000C7607FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE07637B
|
||||
:20118000C076E0000000000006E0000000000006E0000000000006E0000000000006EE0390
|
||||
:2011A00000000000000000000000000000000000000000000000000000000000000000002F
|
||||
:2011C00000000000000000000000000000000000000000000000000000000000000000000F
|
||||
:2011E0000000000000000000000000000000000000000000000000000000000000000000EF
|
||||
:20120000CC3306018207FF0FFFFF3000C73F8F00FF0000EF0339DCFEEF1EFCFEFCC0CC33A8
|
||||
:20122000CC33E2187C7F5E010FFFE070673D803007FF0000030000000000000000C0CC33E1
|
||||
:20124000CC33009C60FD9C76187C387840E000000003FF0000000000000000000000CC331F
|
||||
:20126000CE70000000000000000000000000000000000000000000000000000000000E73AF
|
||||
:20128000C03E7FFFFFFFFFFFFE7FFFFFFFFFFFFE7FFFFFFFFFFFFE7FFFFFFFFFFFFE7C03F1
|
||||
:2012A00000000000000000000000000000000000000000000000000000000000000000002E
|
||||
:2012C00000000000000000000000000000000000000000000000000000000000000000000E
|
||||
:2012E0000000000000000000000000000000000000000000000000000000000000000000EE
|
||||
:20130000CC330C878603FF3FFFFCF03BC7C060E0FF0000FF0339DCFEEF1EFCFEFCC0CC33B1
|
||||
:20132000CC33C231F8603E0E271F80F8739F807803FF0000033D8F68F6BC7BDFBCC0CC338F
|
||||
:20134000CC3300B9C1FB90CC09E070E2418000000003FF0000000000000000000000CC33C0
|
||||
:20136000CC38000000000000000000000000000000000000000000000000000000001C331A
|
||||
:20138000C01C3FFFFFFFFFFFFC3FFFFFFFFFFFFC3FFFFFFFFFFFFC3FFFFFFFFFFFFC38035E
|
||||
:2013A00000000000000000000000000000000000000000000000000000000000000000002D
|
||||
:2013C00000000000000000000000000000000000000000000000000000000000000000000D
|
||||
:2013E0000000000000000000000000000000000000000000000000000000000000000000ED
|
||||
:20140000CC33191F8C047EFFFFC0E07E47C07FE0FF0000FF0339DC38EFBEEC38E0C0CC3347
|
||||
:20142000CC33C633F060387C631307FB8717007801FF000003358D7867B8635AB8C0CC3392
|
||||
:20144000CC33007B87E331DC0980E384870000000100FF0000000000000000000000CC3325
|
||||
:20146000CE1C3FFFFFFFFFFFFC3FFFFFFFFFFFFC3FFFFFFFFFFFFC3FFFFFFFFFFFFC3873FF
|
||||
:20148000C00000000000000000000000000000000000000000000000000000000000000389
|
||||
:2014A00000000000000000000000000000000000000000000000000000000000000000002C
|
||||
:2014C00000000000000000000000000000000000000000000000000000000000000000000C
|
||||
:2014E0000000000000000000000000000000000000000000000000000000000000000000EC
|
||||
:20150000CC33223F0C0101FFFC00E0FC07C07FE07F0000FF0339DC38EFFEFE38F8C0CC33B8
|
||||
:20152000CC338421F0C0E0FFCFCE0FF2170F0058007F0000033D8F1867B06BDAB0C0CC332B
|
||||
:20154000CE7300798F8723BC10838E1C1C0000000000FF0000000000000000000000CE7343
|
||||
:20156000C70E7FFFFFFFFFFFFE7FFFFFFFFFFFFE7FFFFFFFFFFFFE7FFFFFFFFFFFFE70E363
|
||||
:20158000C00000000000000000000000000000000000000000000000000000000000000388
|
||||
:2015A00000000000000000000000000000000000000000000000000000000000000000002B
|
||||
:2015C00000000000000000000000000000000000000000000000000000000000000000000B
|
||||
:2015E0000000000000000000000000000000000000000000000000000000000000000000EB
|
||||
:20160000CC334CFE0C00FFFFF800C0FE01FFF8E07F0000FF0339DC38EFFEFE38F8C0CC3341
|
||||
:20162000CC330461F8C7F9FF8C187FCDFF0F0058001F00000331ED7866BC7B58BCC0CC3311
|
||||
:20164000C6E380199F064778108610787000000000003F0000000000000000000001C6E36D
|
||||
:20166000C3876000000000000760000000000007600000000000076000000000000761C360
|
||||
:20168000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6A
|
||||
:2016A00000000000000000000000000000000000000000000000000000000000000000002A
|
||||
:2016C00000000000000000000000000000000000000000000000000000000000000000000A
|
||||
:2016E0000000000000000000000000000000000000000000000000000000000000000000EA
|
||||
:20170000CC3319F80C0007FFE00080FE00FFF0003F0000FF0339DC38EEEEEE38E0C0CC332B
|
||||
:20172000CC330063BC1FF27F9021FF31FE3C007800070000038000000000000001C0CC331E
|
||||
:20174000C1C1C00CBE0E0F40208821F8E000000000000F000000000000000000000381C329
|
||||
:20176000C1C3800000000000038000000000000380000000000003800000000000038383D3
|
||||
:20178000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF69
|
||||
:2017A000000000000000000000000000000000000000000000000000000000000000000029
|
||||
:2017C000000000000000000000000000000000000000000000000000000000000000000009
|
||||
:2017E0000000000000000000000000000000000000000000000000000000000000000000E9
|
||||
:20180000565656565656565656565656565656565656565656565656565656565656565608
|
||||
:201820005656565656565656565656565656565656565656565656565656565656565656E8
|
||||
:2018400056564600004747444444445C5C5C58586B6B686855555A5A5858584B494F565699
|
||||
:20186000565600004747464646464343445C5C4B4B586B4D4D5555555A5A5A584B495656FC
|
||||
:2018800056564646474746464743434346445C584B4B4B494D4D4D4A4A4A4A5A584B5656C6
|
||||
:2018A0005656464747000046437B7B4747445C5C584B4F4F4F4F4F4F4F4F4F4A5A5856568D
|
||||
:2018C00056564647000000467B7B47474600445C584B4F4F4F4F4F4F4F4F4F4A5A5856560D
|
||||
:2018E00056564747474747437B7B7B47004744445C4B4F4F4F4F4F4F4F4F4F4A5A585656F9
|
||||
:2019000056564747474747477B7B7B7B434346445C4B4F4F4F4F4F4F4F4F4F4A5A5A56565D
|
||||
:20192000565647474700436B6B7B4343434346445C4B4F4F4F4F4F4F4F4F494D555A5656EC
|
||||
:20194000565646470043436B43434343434347445C4B4F4F4F4F4F4F4F4F494D555A565630
|
||||
:2019600056564646464343434343434343450044604C4F4F4F4F4F4F4F4F494D6855565625
|
||||
:20198000565647474743434373736B43454544606060674C4F4F4F4F4F494D4D68555656F1
|
||||
:2019A000565641464700434373536B43454544446060606C4D4D4D4D4D4D4D4D5555565657
|
||||
:2019C00056564141434343435353737344444460606060446C6C6C6C6868684D555056562B
|
||||
:2019E0005656414143434353534373704444004460606044676767676F6F6F6F5757565642
|
||||
:201A00005656414141424253636374714C46464644606044674545454545454545575656DD
|
||||
:201A2000565641414141414141414141414141464444606067444444444444444457565695
|
||||
:201A4000565641414141414141414141414100460044446067676767676F6F6F57575656F6
|
||||
:201A60005656565656565656565656565656565656565656565656565656565656565656A6
|
||||
:201A8000565656565656565656565656565656565656565656565656565656565656565686
|
||||
:201AA000000000000000000000000000000000000000000000000000000000000000000026
|
||||
:201AC000070707070707070707070707070707070707070707070707070707070707070726
|
||||
:201AE000070707070707070707070707070707070707070707070707070707070707070706
|
||||
:00000001FF
|
||||
Binary file not shown.
@@ -0,0 +1,30 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
# Date created = 18:31:55 October 13, 2014
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "13.0"
|
||||
DATE = "18:31:55 October 13, 2014"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "test_ula"
|
||||
@@ -0,0 +1,578 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
# Date created = 18:31:55 October 13, 2014
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# ula_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
set_global_assignment -name FAMILY "Cyclone II"
|
||||
set_global_assignment -name DEVICE EP2C20F484C7
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY test_ula
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:31:55 OCTOBER 13, 2014"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||
|
||||
###########################################################################
|
||||
# System Clocks
|
||||
###########################################################################
|
||||
set_location_assignment PIN_D12 -to CLOCK_27
|
||||
set_location_assignment PIN_E12 -to CLOCK_27_1
|
||||
set_location_assignment PIN_B12 -to CLOCK_24
|
||||
set_location_assignment PIN_A12 -to CLOCK_24_1
|
||||
set_location_assignment PIN_L1 -to CLOCK_50
|
||||
set_location_assignment PIN_M21 -to EXT_CLOCK
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_27
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_27_1
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24_1
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_50
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to EXT_CLOCK
|
||||
|
||||
###########################################################################
|
||||
# Pushbuttons
|
||||
###########################################################################
|
||||
set_location_assignment PIN_R22 -to KEY0
|
||||
set_location_assignment PIN_R21 -to KEY1
|
||||
set_location_assignment PIN_T22 -to KEY2
|
||||
set_location_assignment PIN_T21 -to KEY3
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to KEY0
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to KEY1
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to KEY2
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to KEY3
|
||||
|
||||
###########################################################################
|
||||
# Toggle switches
|
||||
###########################################################################
|
||||
set_location_assignment PIN_L22 -to SW0
|
||||
set_location_assignment PIN_L21 -to SW1
|
||||
set_location_assignment PIN_M22 -to SW2
|
||||
set_location_assignment PIN_V12 -to SW3
|
||||
set_location_assignment PIN_W12 -to SW4
|
||||
set_location_assignment PIN_U12 -to SW5
|
||||
set_location_assignment PIN_U11 -to SW6
|
||||
set_location_assignment PIN_M2 -to SW7
|
||||
set_location_assignment PIN_M1 -to SW8
|
||||
set_location_assignment PIN_L2 -to SW9
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to SW0
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to SW1
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to SW2
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to SW3
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to SW4
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to SW5
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to SW6
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to SW7
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to SW8
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to SW9
|
||||
|
||||
###########################################################################
|
||||
# LEDs
|
||||
###########################################################################
|
||||
set_location_assignment PIN_R20 -to LEDR[0]
|
||||
set_location_assignment PIN_R19 -to LEDR[1]
|
||||
set_location_assignment PIN_U19 -to LEDR[2]
|
||||
set_location_assignment PIN_Y19 -to LEDR[3]
|
||||
set_location_assignment PIN_T18 -to LEDR[4]
|
||||
set_location_assignment PIN_V19 -to LEDR[5]
|
||||
set_location_assignment PIN_Y18 -to LEDR[6]
|
||||
set_location_assignment PIN_U18 -to LEDR[7]
|
||||
set_location_assignment PIN_R18 -to LEDR[8]
|
||||
set_location_assignment PIN_R17 -to LEDR[9]
|
||||
set_location_assignment PIN_U22 -to LEDG[0]
|
||||
set_location_assignment PIN_U21 -to LEDG[1]
|
||||
set_location_assignment PIN_V22 -to LEDG[2]
|
||||
set_location_assignment PIN_V21 -to LEDG[3]
|
||||
set_location_assignment PIN_W22 -to LEDG[4]
|
||||
set_location_assignment PIN_W21 -to LEDG[5]
|
||||
set_location_assignment PIN_Y22 -to LEDG[6]
|
||||
set_location_assignment PIN_Y21 -to LEDG[7]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[0]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[1]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[2]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[3]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[4]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[5]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[6]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[7]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[8]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[9]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[0]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[1]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[2]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[3]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[4]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[5]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[6]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[7]
|
||||
|
||||
###########################################################################
|
||||
# 7-Segment displays
|
||||
###########################################################################
|
||||
set_location_assignment PIN_J2 -to HEX0[0]
|
||||
set_location_assignment PIN_J1 -to HEX0[1]
|
||||
set_location_assignment PIN_H2 -to HEX0[2]
|
||||
set_location_assignment PIN_H1 -to HEX0[3]
|
||||
set_location_assignment PIN_F2 -to HEX0[4]
|
||||
set_location_assignment PIN_F1 -to HEX0[5]
|
||||
set_location_assignment PIN_E2 -to HEX0[6]
|
||||
set_location_assignment PIN_E1 -to HEX1[0]
|
||||
set_location_assignment PIN_H6 -to HEX1[1]
|
||||
set_location_assignment PIN_H5 -to HEX1[2]
|
||||
set_location_assignment PIN_H4 -to HEX1[3]
|
||||
set_location_assignment PIN_G3 -to HEX1[4]
|
||||
set_location_assignment PIN_D2 -to HEX1[5]
|
||||
set_location_assignment PIN_D1 -to HEX1[6]
|
||||
set_location_assignment PIN_G5 -to HEX2[0]
|
||||
set_location_assignment PIN_G6 -to HEX2[1]
|
||||
set_location_assignment PIN_C2 -to HEX2[2]
|
||||
set_location_assignment PIN_C1 -to HEX2[3]
|
||||
set_location_assignment PIN_E3 -to HEX2[4]
|
||||
set_location_assignment PIN_E4 -to HEX2[5]
|
||||
set_location_assignment PIN_D3 -to HEX2[6]
|
||||
set_location_assignment PIN_F4 -to HEX3[0]
|
||||
set_location_assignment PIN_D5 -to HEX3[1]
|
||||
set_location_assignment PIN_D6 -to HEX3[2]
|
||||
set_location_assignment PIN_J4 -to HEX3[3]
|
||||
set_location_assignment PIN_L8 -to HEX3[4]
|
||||
set_location_assignment PIN_F3 -to HEX3[5]
|
||||
set_location_assignment PIN_D4 -to HEX3[6]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]
|
||||
|
||||
###########################################################################
|
||||
# VGA
|
||||
###########################################################################
|
||||
set_location_assignment PIN_D9 -to VGA_R[0]
|
||||
set_location_assignment PIN_C9 -to VGA_R[1]
|
||||
set_location_assignment PIN_A7 -to VGA_R[2]
|
||||
set_location_assignment PIN_B7 -to VGA_R[3]
|
||||
set_location_assignment PIN_B8 -to VGA_G[0]
|
||||
set_location_assignment PIN_C10 -to VGA_G[1]
|
||||
set_location_assignment PIN_B9 -to VGA_G[2]
|
||||
set_location_assignment PIN_A8 -to VGA_G[3]
|
||||
set_location_assignment PIN_A9 -to VGA_B[0]
|
||||
set_location_assignment PIN_D11 -to VGA_B[1]
|
||||
set_location_assignment PIN_A10 -to VGA_B[2]
|
||||
set_location_assignment PIN_B10 -to VGA_B[3]
|
||||
set_location_assignment PIN_A11 -to VGA_HS
|
||||
set_location_assignment PIN_B11 -to VGA_VS
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[0]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[1]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[2]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[3]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[0]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[1]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[2]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[3]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[0]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[1]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[2]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[3]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_HS
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_VS
|
||||
|
||||
###########################################################################
|
||||
# Audio Codec
|
||||
###########################################################################
|
||||
set_location_assignment PIN_A3 -to I2C_SCLK
|
||||
set_location_assignment PIN_B3 -to I2C_SDAT
|
||||
set_location_assignment PIN_A6 -to AUD_ADCLRCK
|
||||
set_location_assignment PIN_B6 -to AUD_ADCDAT
|
||||
set_location_assignment PIN_A5 -to AUD_DACLRCK
|
||||
set_location_assignment PIN_B5 -to AUD_DACDAT
|
||||
set_location_assignment PIN_B4 -to AUD_XCK
|
||||
set_location_assignment PIN_A4 -to AUD_BCLK
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK
|
||||
|
||||
###########################################################################
|
||||
# Serial (UART)
|
||||
###########################################################################
|
||||
set_location_assignment PIN_F14 -to UART_RXD
|
||||
set_location_assignment PIN_G12 -to UART_TXD
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to UART_RXD
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to UART_TXD
|
||||
|
||||
###########################################################################
|
||||
# PS/2
|
||||
###########################################################################
|
||||
set_location_assignment PIN_H15 -to PS2_CLK
|
||||
set_location_assignment PIN_J14 -to PS2_DAT
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to PS2_CLK
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to PS2_DAT
|
||||
|
||||
###########################################################################
|
||||
# SD Card
|
||||
###########################################################################
|
||||
set_location_assignment PIN_E8 -to TDI
|
||||
set_location_assignment PIN_D8 -to TCS
|
||||
set_location_assignment PIN_C7 -to TCK
|
||||
set_location_assignment PIN_D7 -to TDO
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to TDI
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to TCS
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to TCK
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to TDO
|
||||
|
||||
###########################################################################
|
||||
# SDRAM
|
||||
###########################################################################
|
||||
set_location_assignment PIN_W4 -to DRAM_ADDR[0]
|
||||
set_location_assignment PIN_W5 -to DRAM_ADDR[1]
|
||||
set_location_assignment PIN_Y3 -to DRAM_ADDR[2]
|
||||
set_location_assignment PIN_Y4 -to DRAM_ADDR[3]
|
||||
set_location_assignment PIN_R6 -to DRAM_ADDR[4]
|
||||
set_location_assignment PIN_R5 -to DRAM_ADDR[5]
|
||||
set_location_assignment PIN_P6 -to DRAM_ADDR[6]
|
||||
set_location_assignment PIN_P5 -to DRAM_ADDR[7]
|
||||
set_location_assignment PIN_P3 -to DRAM_ADDR[8]
|
||||
set_location_assignment PIN_N4 -to DRAM_ADDR[9]
|
||||
set_location_assignment PIN_W3 -to DRAM_ADDR[10]
|
||||
set_location_assignment PIN_N6 -to DRAM_ADDR[11]
|
||||
set_location_assignment PIN_U1 -to DRAM_DQ[0]
|
||||
set_location_assignment PIN_U2 -to DRAM_DQ[1]
|
||||
set_location_assignment PIN_V1 -to DRAM_DQ[2]
|
||||
set_location_assignment PIN_V2 -to DRAM_DQ[3]
|
||||
set_location_assignment PIN_W1 -to DRAM_DQ[4]
|
||||
set_location_assignment PIN_W2 -to DRAM_DQ[5]
|
||||
set_location_assignment PIN_Y1 -to DRAM_DQ[6]
|
||||
set_location_assignment PIN_Y2 -to DRAM_DQ[7]
|
||||
set_location_assignment PIN_N1 -to DRAM_DQ[8]
|
||||
set_location_assignment PIN_N2 -to DRAM_DQ[9]
|
||||
set_location_assignment PIN_P1 -to DRAM_DQ[10]
|
||||
set_location_assignment PIN_P2 -to DRAM_DQ[11]
|
||||
set_location_assignment PIN_R1 -to DRAM_DQ[12]
|
||||
set_location_assignment PIN_R2 -to DRAM_DQ[13]
|
||||
set_location_assignment PIN_T1 -to DRAM_DQ[14]
|
||||
set_location_assignment PIN_T2 -to DRAM_DQ[15]
|
||||
set_location_assignment PIN_U3 -to DRAM_BA_0
|
||||
set_location_assignment PIN_V4 -to DRAM_BA_1
|
||||
set_location_assignment PIN_R7 -to DRAM_LDQM
|
||||
set_location_assignment PIN_M5 -to DRAM_UDQM
|
||||
set_location_assignment PIN_T5 -to DRAM_RAS_N
|
||||
set_location_assignment PIN_T3 -to DRAM_CAS_N
|
||||
set_location_assignment PIN_N3 -to DRAM_CKE
|
||||
set_location_assignment PIN_U4 -to DRAM_CLK
|
||||
set_location_assignment PIN_R8 -to DRAM_WE_N
|
||||
set_location_assignment PIN_T6 -to DRAM_CS_N
|
||||
|
||||
###########################################################################
|
||||
# SRAM
|
||||
###########################################################################
|
||||
set_location_assignment PIN_AA3 -to SRAM_ADDR[0]
|
||||
set_location_assignment PIN_AB3 -to SRAM_ADDR[1]
|
||||
set_location_assignment PIN_AA4 -to SRAM_ADDR[2]
|
||||
set_location_assignment PIN_AB4 -to SRAM_ADDR[3]
|
||||
set_location_assignment PIN_AA5 -to SRAM_ADDR[4]
|
||||
set_location_assignment PIN_AB10 -to SRAM_ADDR[5]
|
||||
set_location_assignment PIN_AA11 -to SRAM_ADDR[6]
|
||||
set_location_assignment PIN_AB11 -to SRAM_ADDR[7]
|
||||
set_location_assignment PIN_V11 -to SRAM_ADDR[8]
|
||||
set_location_assignment PIN_W11 -to SRAM_ADDR[9]
|
||||
set_location_assignment PIN_R11 -to SRAM_ADDR[10]
|
||||
set_location_assignment PIN_T11 -to SRAM_ADDR[11]
|
||||
set_location_assignment PIN_Y10 -to SRAM_ADDR[12]
|
||||
set_location_assignment PIN_U10 -to SRAM_ADDR[13]
|
||||
set_location_assignment PIN_R10 -to SRAM_ADDR[14]
|
||||
set_location_assignment PIN_T7 -to SRAM_ADDR[15]
|
||||
set_location_assignment PIN_Y6 -to SRAM_ADDR[16]
|
||||
set_location_assignment PIN_Y5 -to SRAM_ADDR[17]
|
||||
set_location_assignment PIN_AA6 -to SRAM_DQ[0]
|
||||
set_location_assignment PIN_AB6 -to SRAM_DQ[1]
|
||||
set_location_assignment PIN_AA7 -to SRAM_DQ[2]
|
||||
set_location_assignment PIN_AB7 -to SRAM_DQ[3]
|
||||
set_location_assignment PIN_AA8 -to SRAM_DQ[4]
|
||||
set_location_assignment PIN_AB8 -to SRAM_DQ[5]
|
||||
set_location_assignment PIN_AA9 -to SRAM_DQ[6]
|
||||
set_location_assignment PIN_AB9 -to SRAM_DQ[7]
|
||||
set_location_assignment PIN_Y9 -to SRAM_DQ[8]
|
||||
set_location_assignment PIN_W9 -to SRAM_DQ[9]
|
||||
set_location_assignment PIN_V9 -to SRAM_DQ[10]
|
||||
set_location_assignment PIN_U9 -to SRAM_DQ[11]
|
||||
set_location_assignment PIN_R9 -to SRAM_DQ[12]
|
||||
set_location_assignment PIN_W8 -to SRAM_DQ[13]
|
||||
set_location_assignment PIN_V8 -to SRAM_DQ[14]
|
||||
set_location_assignment PIN_U8 -to SRAM_DQ[15]
|
||||
set_location_assignment PIN_AA10 -to SRAM_WE_N
|
||||
set_location_assignment PIN_T8 -to SRAM_OE_N
|
||||
set_location_assignment PIN_W7 -to SRAM_UB_N
|
||||
set_location_assignment PIN_Y7 -to SRAM_LB_N
|
||||
set_location_assignment PIN_AB5 -to SRAM_CE_N
|
||||
|
||||
###########################################################################
|
||||
# FLASH
|
||||
###########################################################################
|
||||
set_location_assignment PIN_AB20 -to FL_ADDR[0]
|
||||
set_location_assignment PIN_AA14 -to FL_ADDR[1]
|
||||
set_location_assignment PIN_Y16 -to FL_ADDR[2]
|
||||
set_location_assignment PIN_R15 -to FL_ADDR[3]
|
||||
set_location_assignment PIN_T15 -to FL_ADDR[4]
|
||||
set_location_assignment PIN_U15 -to FL_ADDR[5]
|
||||
set_location_assignment PIN_V15 -to FL_ADDR[6]
|
||||
set_location_assignment PIN_W15 -to FL_ADDR[7]
|
||||
set_location_assignment PIN_R14 -to FL_ADDR[8]
|
||||
set_location_assignment PIN_Y13 -to FL_ADDR[9]
|
||||
set_location_assignment PIN_R12 -to FL_ADDR[10]
|
||||
set_location_assignment PIN_T12 -to FL_ADDR[11]
|
||||
set_location_assignment PIN_AB14 -to FL_ADDR[12]
|
||||
set_location_assignment PIN_AA13 -to FL_ADDR[13]
|
||||
set_location_assignment PIN_AB13 -to FL_ADDR[14]
|
||||
set_location_assignment PIN_AA12 -to FL_ADDR[15]
|
||||
set_location_assignment PIN_AB12 -to FL_ADDR[16]
|
||||
set_location_assignment PIN_AA20 -to FL_ADDR[17]
|
||||
set_location_assignment PIN_U14 -to FL_ADDR[18]
|
||||
set_location_assignment PIN_V14 -to FL_ADDR[19]
|
||||
set_location_assignment PIN_U13 -to FL_ADDR[20]
|
||||
set_location_assignment PIN_R13 -to FL_ADDR[21]
|
||||
set_location_assignment PIN_AB16 -to FL_DQ[0]
|
||||
set_location_assignment PIN_AA16 -to FL_DQ[1]
|
||||
set_location_assignment PIN_AB17 -to FL_DQ[2]
|
||||
set_location_assignment PIN_AA17 -to FL_DQ[3]
|
||||
set_location_assignment PIN_AB18 -to FL_DQ[4]
|
||||
set_location_assignment PIN_AA18 -to FL_DQ[5]
|
||||
set_location_assignment PIN_AB19 -to FL_DQ[6]
|
||||
set_location_assignment PIN_AA19 -to FL_DQ[7]
|
||||
set_location_assignment PIN_AB15 -to FL_CE_N
|
||||
set_location_assignment PIN_AA15 -to FL_OE_N
|
||||
set_location_assignment PIN_W14 -to FL_RST_N
|
||||
set_location_assignment PIN_Y14 -to FL_WE_N
|
||||
|
||||
###########################################################################
|
||||
# GPIO-0 Expansion Header 1
|
||||
###########################################################################
|
||||
set_location_assignment PIN_A13 -to GPIO_0[0]
|
||||
set_location_assignment PIN_B13 -to GPIO_0[1]
|
||||
set_location_assignment PIN_A14 -to GPIO_0[2]
|
||||
set_location_assignment PIN_B14 -to GPIO_0[3]
|
||||
set_location_assignment PIN_A15 -to GPIO_0[4]
|
||||
set_location_assignment PIN_B15 -to GPIO_0[5]
|
||||
set_location_assignment PIN_A16 -to GPIO_0[6]
|
||||
set_location_assignment PIN_B16 -to GPIO_0[7]
|
||||
set_location_assignment PIN_A17 -to GPIO_0[8]
|
||||
set_location_assignment PIN_B17 -to GPIO_0[9]
|
||||
set_location_assignment PIN_A18 -to GPIO_0[10]
|
||||
set_location_assignment PIN_B18 -to GPIO_0[11]
|
||||
set_location_assignment PIN_A19 -to GPIO_0[12]
|
||||
set_location_assignment PIN_B19 -to GPIO_0[13]
|
||||
set_location_assignment PIN_A20 -to GPIO_0[14]
|
||||
set_location_assignment PIN_B20 -to GPIO_0[15]
|
||||
set_location_assignment PIN_C21 -to GPIO_0[16]
|
||||
set_location_assignment PIN_C22 -to GPIO_0[17]
|
||||
set_location_assignment PIN_D21 -to GPIO_0[18]
|
||||
set_location_assignment PIN_D22 -to GPIO_0[19]
|
||||
set_location_assignment PIN_E21 -to GPIO_0[20]
|
||||
set_location_assignment PIN_E22 -to GPIO_0[21]
|
||||
set_location_assignment PIN_F21 -to GPIO_0[22]
|
||||
set_location_assignment PIN_F22 -to GPIO_0[23]
|
||||
set_location_assignment PIN_G21 -to GPIO_0[24]
|
||||
set_location_assignment PIN_G22 -to GPIO_0[25]
|
||||
set_location_assignment PIN_J21 -to GPIO_0[26]
|
||||
set_location_assignment PIN_J22 -to GPIO_0[27]
|
||||
set_location_assignment PIN_K21 -to GPIO_0[28]
|
||||
set_location_assignment PIN_K22 -to GPIO_0[29]
|
||||
set_location_assignment PIN_J19 -to GPIO_0[30]
|
||||
set_location_assignment PIN_J20 -to GPIO_0[31]
|
||||
set_location_assignment PIN_J18 -to GPIO_0[32]
|
||||
set_location_assignment PIN_K20 -to GPIO_0[33]
|
||||
set_location_assignment PIN_L19 -to GPIO_0[34]
|
||||
set_location_assignment PIN_L18 -to GPIO_0[35]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[0]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[1]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[2]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[3]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[4]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[5]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[6]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[7]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[8]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[9]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[10]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[11]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[12]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[13]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[14]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[15]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[16]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[17]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[18]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[19]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[20]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[21]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[22]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[23]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[24]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[25]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[26]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[27]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[28]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[29]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[30]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[31]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[32]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[33]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[34]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[35]
|
||||
|
||||
###########################################################################
|
||||
# GPIO-1 Expansion Header 2
|
||||
###########################################################################
|
||||
set_location_assignment PIN_H12 -to GPIO_1[0]
|
||||
set_location_assignment PIN_H13 -to GPIO_1[1]
|
||||
set_location_assignment PIN_H14 -to GPIO_1[2]
|
||||
set_location_assignment PIN_G15 -to GPIO_1[3]
|
||||
set_location_assignment PIN_E14 -to GPIO_1[4]
|
||||
set_location_assignment PIN_E15 -to GPIO_1[5]
|
||||
set_location_assignment PIN_F15 -to GPIO_1[6]
|
||||
set_location_assignment PIN_G16 -to GPIO_1[7]
|
||||
set_location_assignment PIN_F12 -to GPIO_1[8]
|
||||
set_location_assignment PIN_F13 -to GPIO_1[9]
|
||||
set_location_assignment PIN_C14 -to GPIO_1[10]
|
||||
set_location_assignment PIN_D14 -to GPIO_1[11]
|
||||
set_location_assignment PIN_D15 -to GPIO_1[12]
|
||||
set_location_assignment PIN_D16 -to GPIO_1[13]
|
||||
set_location_assignment PIN_C17 -to GPIO_1[14]
|
||||
set_location_assignment PIN_C18 -to GPIO_1[15]
|
||||
set_location_assignment PIN_C19 -to GPIO_1[16]
|
||||
set_location_assignment PIN_C20 -to GPIO_1[17]
|
||||
set_location_assignment PIN_D19 -to GPIO_1[18]
|
||||
set_location_assignment PIN_D20 -to GPIO_1[19]
|
||||
set_location_assignment PIN_E20 -to GPIO_1[20]
|
||||
set_location_assignment PIN_F20 -to GPIO_1[21]
|
||||
set_location_assignment PIN_E19 -to GPIO_1[22]
|
||||
set_location_assignment PIN_E18 -to GPIO_1[23]
|
||||
set_location_assignment PIN_G20 -to GPIO_1[24]
|
||||
set_location_assignment PIN_G18 -to GPIO_1[25]
|
||||
set_location_assignment PIN_G17 -to GPIO_1[26]
|
||||
set_location_assignment PIN_H17 -to GPIO_1[27]
|
||||
set_location_assignment PIN_J15 -to GPIO_1[28]
|
||||
set_location_assignment PIN_H18 -to GPIO_1[29]
|
||||
set_location_assignment PIN_N22 -to GPIO_1[30]
|
||||
set_location_assignment PIN_N21 -to GPIO_1[31]
|
||||
set_location_assignment PIN_P15 -to GPIO_1[32]
|
||||
set_location_assignment PIN_N15 -to GPIO_1[33]
|
||||
set_location_assignment PIN_P17 -to GPIO_1[34]
|
||||
set_location_assignment PIN_P18 -to GPIO_1[35]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[0]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[1]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[2]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[3]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[4]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[5]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[6]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[7]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[8]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[9]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[10]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[11]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[12]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[13]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[14]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[15]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[16]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[17]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[18]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[19]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[20]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[21]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[22]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[23]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[24]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[25]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[26]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[27]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[28]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[29]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[30]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[31]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35]
|
||||
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
|
||||
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
|
||||
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
|
||||
set_global_assignment -name SMART_RECOMPILE ON
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
|
||||
set_global_assignment -name FITTER_EFFORT "FAST FIT"
|
||||
set_global_assignment -name QIP_FILE ram8.qip
|
||||
set_global_assignment -name QIP_FILE pll.qip
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE test_ula.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE clocks.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE video.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE zx_kbd.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE ps2_kbd.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE uart_core.sv
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
+124
@@ -0,0 +1,124 @@
|
||||
//============================================================================
|
||||
// Test Sinclair ZX Spectrum ULA
|
||||
//
|
||||
// Copyright (C) 2014-2016 Goran Devic
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License along
|
||||
// with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
//============================================================================
|
||||
module test_ula
|
||||
(
|
||||
input wire CLOCK_50, // Input clock 50 MHz
|
||||
input wire CLOCK_27, // Input clock 27 MHz
|
||||
input wire KEY0, // Button 0 is reset
|
||||
|
||||
output wire [3:0] VGA_R,
|
||||
output wire [3:0] VGA_G,
|
||||
output wire [3:0] VGA_B,
|
||||
output reg VGA_HS,
|
||||
output reg VGA_VS,
|
||||
|
||||
output wire [21:0] FL_ADDR,
|
||||
input wire [7:0] FL_DQ,
|
||||
output wire FL_CE_N,
|
||||
output wire FL_OE_N,
|
||||
output wire FL_RST_N,
|
||||
output wire FL_WE_N,
|
||||
|
||||
input wire PS2_CLK,
|
||||
input wire PS2_DAT,
|
||||
output wire UART_TXD,
|
||||
|
||||
output wire [6:0] GPIO_0, // Scope test points
|
||||
input wire SW0,
|
||||
input wire SW1,
|
||||
input wire SW2
|
||||
);
|
||||
`default_nettype none
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// Instantiate PLL and clocks block
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
wire clk_pix; // VGA pixel clock (25.175 MHz)
|
||||
wire clk_ula; // ULA master clock (14 MHz)
|
||||
pll pll_( .inclk0(CLOCK_27), .c0(clk_pix), .c1(clk_ula) );
|
||||
|
||||
wire clk_cpu; // Clocks generates CPU clocks of 3.5 MHz
|
||||
clocks clocks_( .* );
|
||||
|
||||
// Various scope test points, connect as needed:
|
||||
//assign GPIO_0[0] = CLOCK_27;
|
||||
//assign GPIO_0[1] = clk_pix;
|
||||
//assign GPIO_0[2] = clk_ula;
|
||||
//assign GPIO_0[3] = clk_cpu;
|
||||
assign GPIO_0[4] = VGA_VS;
|
||||
assign GPIO_0[5] = VGA_HS;
|
||||
assign GPIO_0[6] = VGA_B[0];
|
||||
|
||||
assign GPIO_0[0] = PS2_CLK;
|
||||
assign GPIO_0[1] = PS2_DAT;
|
||||
assign GPIO_0[2] = UART_TXD;
|
||||
assign GPIO_0[3] = vs_nintr;
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// Instantiate RAM that contains a sample screen image
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
reg [12:0] vram_address;
|
||||
reg [7:0] vram_data;
|
||||
ram8 ram8_( .address(vram_address), .clock(clk_pix), .data(0), .wren(0), .q(vram_data));
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// State register containing the border color index
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
reg [7:0] state;
|
||||
|
||||
// Testing: assign the border color index based on the board switches
|
||||
wire [2:0] border; // Border color index value
|
||||
assign border = { SW2, SW1, SW0 };
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// Instantiate ULA's video subsystem
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
wire vs_nintr; // Vertical retrace interrupt
|
||||
|
||||
video video_( .*, .vram_address(vram_address), .vram_data(vram_data) );
|
||||
|
||||
// Use flash interface instead of the internal RAM
|
||||
assign FL_CE_N = 0;
|
||||
assign FL_OE_N = 0;
|
||||
assign FL_RST_N = KEY0;
|
||||
assign FL_WE_N = 1;
|
||||
assign FL_ADDR[21:13] = 'b10;
|
||||
//video video_( .*, .vram_address(FL_ADDR[12:0]), .vram_data(FL_DQ) );
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// Instantiate keyboard support
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
wire [7:0] scan_code;
|
||||
wire scan_code_ready;
|
||||
wire scan_code_error;
|
||||
|
||||
ps2_keyboard ps2_keyboard_( .*, .clk(CLOCK_50), .reset(KEY0) );
|
||||
|
||||
reg [15:0] A = 16'hFEFE;
|
||||
wire [4:0] key_row;
|
||||
zx_keyboard zx_keyboard_( .*, .clk(CLOCK_50), .reset(KEY0) );
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// Add UART so we can echo keyboard through the serial port out
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
wire busy_tx;
|
||||
uart_core uart_core_( .*, .reset(!KEY0), .clk(CLOCK_50), .uart_tx(UART_TXD), .data_in(scan_code), .data_in_wr(scan_code_ready) );
|
||||
|
||||
endmodule
|
||||
+179
@@ -0,0 +1,179 @@
|
||||
//============================================================================
|
||||
// Sinclair ZX Spectrum ULA
|
||||
//
|
||||
// Copyright (C) 2014-2016 Goran Devic
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License along
|
||||
// with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
//============================================================================
|
||||
module ula
|
||||
(
|
||||
//-------- Clocks and reset -----------------
|
||||
input wire CLOCK_50, // Input clock 50 MHz
|
||||
input wire turbo, // Turbo speed (3.5 MHz x 2 = 7.0 MHz)
|
||||
output wire clk_vram,
|
||||
input wire nreset, // Active low reset
|
||||
output wire locked, // PLL is locked signal
|
||||
|
||||
//-------- CPU control ----------------------
|
||||
output wire clk_cpu, // Generates CPU clock of 3.5 MHz
|
||||
output wire vs_nintr, // Generates a vertical retrace interrupt
|
||||
|
||||
//-------- Address and data buses -----------
|
||||
input wire [15:0] A, // Input address bus
|
||||
input wire [7:0] D, // Input data bus
|
||||
output wire [7:0] ula_data, // Output data
|
||||
input wire io_we, // Write enable to data register through IO
|
||||
|
||||
output wire [12:0] vram_address,// ULA video block requests a byte from the video RAM
|
||||
input wire [7:0] vram_data, // ULA video block reads a byte from the video RAM
|
||||
|
||||
//-------- PS/2 Keyboard --------------------
|
||||
input wire PS2_CLK,
|
||||
input wire PS2_DAT,
|
||||
output wire pressed,
|
||||
|
||||
//-------- Audio (Tape player) --------------
|
||||
inout wire I2C_SCLK,
|
||||
inout wire I2C_SDAT,
|
||||
output wire AUD_XCK,
|
||||
output wire AUD_ADCLRCK,
|
||||
output wire AUD_DACLRCK,
|
||||
output wire AUD_BCLK,
|
||||
output wire AUD_DACDAT,
|
||||
input wire AUD_ADCDAT,
|
||||
output reg beeper,
|
||||
output reg beep,
|
||||
|
||||
//-------- VGA connector --------------------
|
||||
output wire [3:0] VGA_R,
|
||||
output wire [3:0] VGA_G,
|
||||
output wire [3:0] VGA_B,
|
||||
output reg VGA_HS,
|
||||
output reg VGA_VS
|
||||
);
|
||||
`default_nettype none
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// Instantiate PLL and clocks block
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
wire clk_pix; // VGA pixel clock (25.175 MHz)
|
||||
wire clk_ula; // ULA master clock (14 MHz)
|
||||
wire clk_i2s;
|
||||
|
||||
assign clk_vram = clk_pix;
|
||||
pll pll_(
|
||||
.locked(locked),
|
||||
.inclk0(CLOCK_50),
|
||||
.c0(clk_pix),
|
||||
.c1(clk_ula),
|
||||
.c2(clk_i2s)
|
||||
);
|
||||
|
||||
clocks clocks_( .* );
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// The border color index
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
reg [2:0] border; // Border color index value
|
||||
|
||||
always @(posedge clk_cpu)
|
||||
begin
|
||||
if (A[0]==0 && io_we==1) begin
|
||||
border <= D[2:0];
|
||||
// EAR output (produces a louder sound)
|
||||
pcm_outl[14] <= D[4]; // Why [14] and not [15]? Less loud.
|
||||
pcm_outr[14] <= D[4];
|
||||
// MIC (echoes the input)
|
||||
pcm_outl[13] <= D[3];
|
||||
pcm_outr[13] <= D[3];
|
||||
// Let us hear the tape loading!
|
||||
pcm_outl[12] <= pcm_inl[14] | pcm_inr[14];
|
||||
pcm_outr[12] <= pcm_inl[14] | pcm_inr[14];
|
||||
// Let us see the tape loading!
|
||||
beep <= (pcm_inl[14] | pcm_inr[14]) ^ D[4] ^ D[3];
|
||||
end
|
||||
end
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// Instantiate audio interface
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
wire audio_done;
|
||||
wire audio_error;
|
||||
|
||||
i2c_loader i2c_loader_(
|
||||
.CLK(clk_i2s),
|
||||
.nRESET(nreset),
|
||||
.I2C_SCL(I2C_SCLK),
|
||||
.I2C_SDA(I2C_SDAT),
|
||||
.IS_DONE(audio_done),
|
||||
.IS_ERROR(audio_error)
|
||||
);
|
||||
|
||||
assign AUD_DACLRCK = AUD_ADCLRCK;
|
||||
wire [15:0] pcm_inl;
|
||||
wire [15:0] pcm_inr;
|
||||
reg [15:0] pcm_outl;
|
||||
reg [15:0] pcm_outr;
|
||||
|
||||
i2s_intf i2s_intf_(
|
||||
.CLK(clk_i2s),
|
||||
.nRESET(nreset),
|
||||
.PCM_INL(pcm_inl[15:0]),
|
||||
.PCM_INR(pcm_inr[15:0]),
|
||||
.PCM_OUTL(pcm_outl[15:0]),
|
||||
.PCM_OUTR(pcm_outr[15:0]),
|
||||
.I2S_MCLK(AUD_XCK),
|
||||
.I2S_LRCLK(AUD_ADCLRCK),
|
||||
.I2S_BCLK(AUD_BCLK),
|
||||
.I2S_DOUT(AUD_DACDAT),
|
||||
.I2S_DIN(AUD_ADCDAT)
|
||||
);
|
||||
|
||||
// Show the beeper visually by dividing the frequency with some factor to generate LED blinks
|
||||
//reg beep; // Beeper latch
|
||||
reg [6:0] beepcnt; // Beeper counter
|
||||
always @(posedge beep)
|
||||
begin
|
||||
beepcnt <= beepcnt - '1;
|
||||
if (beepcnt==0) beeper <= ~beeper;
|
||||
end
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// Instantiate ULA's video subsystem
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
video video_( .* );
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// Instantiate keyboard support
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
wire [7:0] scan_code;
|
||||
wire scan_code_ready;
|
||||
wire scan_code_error;
|
||||
|
||||
ps2_keyboard ps2_keyboard_( .*, .clk(clk_cpu) );
|
||||
|
||||
wire [4:0] key_row;
|
||||
zx_keyboard zx_keyboard_( .*, .clk(clk_cpu) );
|
||||
|
||||
always_comb
|
||||
begin
|
||||
ula_data = 8'hFF;
|
||||
// Regular IO at every odd address: line-in and keyboard
|
||||
if (A[0]==0) begin
|
||||
ula_data = { 1'b1, pcm_inl[14] | pcm_inr[14], 1'b1, key_row[4:0] };
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
+154
@@ -0,0 +1,154 @@
|
||||
//============================================================================
|
||||
// Sinclair ZX Spectrum ULA
|
||||
//
|
||||
// Copyright (C) 2014-2016 Goran Devic
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License along
|
||||
// with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
//============================================================================
|
||||
module ula
|
||||
(
|
||||
//-------- Clocks and reset -----------------
|
||||
input wire CLOCK_27, // Input clock 27 MHz
|
||||
input wire CLOCK_24, // Input clock 24 MHz
|
||||
input wire turbo, // Turbo speed (3.5 MHz x 2 = 7.0 MHz)
|
||||
output wire clk_vram,
|
||||
input wire nreset, // Active low reset
|
||||
output wire locked, // PLL is locked signal
|
||||
|
||||
//-------- CPU control ----------------------
|
||||
output wire clk_cpu, // Generates CPU clock of 3.5 MHz
|
||||
output wire vs_nintr, // Generates a vertical retrace interrupt
|
||||
|
||||
//-------- Address and data buses -----------
|
||||
input wire [15:0] A, // Input address bus
|
||||
input wire [7:0] D, // Input data bus
|
||||
output wire [7:0] ula_data, // Output data
|
||||
input wire io_we, // Write enable to data register through IO
|
||||
|
||||
output wire [12:0] vram_address,// ULA video block requests a byte from the video RAM
|
||||
input wire [7:0] vram_data, // ULA video block reads a byte from the video RAM
|
||||
|
||||
//-------- PS/2 Keyboard --------------------
|
||||
input wire PS2_CLK,
|
||||
input wire PS2_DAT,
|
||||
output wire pressed,
|
||||
|
||||
//-------- Audio (Tape player) --------------
|
||||
inout wire I2C_SCLK,
|
||||
inout wire I2C_SDAT,
|
||||
output wire AUD_XCK,
|
||||
output wire AUD_ADCLRCK,
|
||||
output wire AUD_DACLRCK,
|
||||
output wire AUD_BCLK,
|
||||
output wire AUD_DACDAT,
|
||||
input wire AUD_ADCDAT,
|
||||
output reg beeper,
|
||||
|
||||
//-------- VGA connector --------------------
|
||||
output wire [3:0] VGA_R,
|
||||
output wire [3:0] VGA_G,
|
||||
output wire [3:0] VGA_B,
|
||||
output reg VGA_HS,
|
||||
output reg VGA_VS
|
||||
);
|
||||
`default_nettype none
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// Instantiate PLL and clocks block
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
wire clk_pix; // VGA pixel clock (25.175 MHz)
|
||||
wire clk_ula; // ULA master clock (14 MHz)
|
||||
assign clk_vram = clk_pix;
|
||||
pll pll_( .locked(locked), .inclk0(CLOCK_27), .c0(clk_pix), .c1(clk_ula) );
|
||||
|
||||
clocks clocks_( .* );
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// The border color index
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
reg [2:0] border; // Border color index value
|
||||
|
||||
always @(posedge clk_cpu)
|
||||
begin
|
||||
if (A[0]==0 && io_we==1) begin
|
||||
border <= D[2:0];
|
||||
// EAR output (produces a louder sound)
|
||||
pcm_outl[14] <= D[4]; // Why [14] and not [15]? Less loud.
|
||||
pcm_outr[14] <= D[4];
|
||||
// MIC (echoes the input)
|
||||
pcm_outl[13] <= D[3];
|
||||
pcm_outr[13] <= D[3];
|
||||
// Let us hear the tape loading!
|
||||
pcm_outl[12] <= pcm_inl[14] | pcm_inr[14];
|
||||
pcm_outr[12] <= pcm_inl[14] | pcm_inr[14];
|
||||
// Let us see the tape loading!
|
||||
beep <= (pcm_inl[14] | pcm_inr[14]) ^ D[4] ^ D[3];
|
||||
end
|
||||
end
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// Instantiate audio interface
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
wire audio_done;
|
||||
wire audio_error;
|
||||
|
||||
i2c_loader i2c_loader_( .CLK(CLOCK_24), .nRESET(nreset), .I2C_SCL(I2C_SCLK), .I2C_SDA(I2C_SDAT), .IS_DONE(audio_done), .IS_ERROR(audio_error) );
|
||||
|
||||
assign AUD_DACLRCK = AUD_ADCLRCK;
|
||||
wire [15:0] pcm_inl;
|
||||
wire [15:0] pcm_inr;
|
||||
reg [15:0] pcm_outl;
|
||||
reg [15:0] pcm_outr;
|
||||
|
||||
i2s_intf i2s_intf_( .CLK(CLOCK_24), .nRESET(nreset),
|
||||
.PCM_INL(pcm_inl[15:0]), .PCM_INR(pcm_inr[15:0]), .PCM_OUTL(pcm_outl[15:0]), .PCM_OUTR(pcm_outr[15:0]),
|
||||
.I2S_MCLK(AUD_XCK), .I2S_LRCLK(AUD_ADCLRCK), .I2S_BCLK(AUD_BCLK), .I2S_DOUT(AUD_DACDAT), .I2S_DIN(AUD_ADCDAT) );
|
||||
|
||||
// Show the beeper visually by dividing the frequency with some factor to generate LED blinks
|
||||
reg beep; // Beeper latch
|
||||
reg [6:0] beepcnt; // Beeper counter
|
||||
always @(posedge beep)
|
||||
begin
|
||||
beepcnt <= beepcnt - '1;
|
||||
if (beepcnt==0) beeper <= ~beeper;
|
||||
end
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// Instantiate ULA's video subsystem
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
video video_( .* );
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// Instantiate keyboard support
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
wire [7:0] scan_code;
|
||||
wire scan_code_ready;
|
||||
wire scan_code_error;
|
||||
|
||||
ps2_keyboard ps2_keyboard_( .*, .clk(clk_cpu) );
|
||||
|
||||
wire [4:0] key_row;
|
||||
zx_keyboard zx_keyboard_( .*, .clk(clk_cpu) );
|
||||
|
||||
always_comb
|
||||
begin
|
||||
ula_data = 8'hFF;
|
||||
// Regular IO at every odd address: line-in and keyboard
|
||||
if (A[0]==0) begin
|
||||
ula_data = { 1'b1, pcm_inl[14] | pcm_inr[14], 1'b1, key_row[4:0] };
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
+201
@@ -0,0 +1,201 @@
|
||||
//============================================================================
|
||||
// Sinclair ZX Spectrum ULA
|
||||
//
|
||||
// This module contains video support.
|
||||
//
|
||||
// Note: There is no reset signal in this VGA design since all relevant
|
||||
// counters will reset themselves within one display frame as the
|
||||
// pixel clock keeps ticking.
|
||||
//
|
||||
// Copyright (C) 2014-2016 Goran Devic
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License along
|
||||
// with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
//============================================================================
|
||||
module video
|
||||
(
|
||||
input wire clk_pix, // Input VGA pixel clock of 25.175 MHz
|
||||
|
||||
output wire [3:0] VGA_R, // Output VGA R component
|
||||
output wire [3:0] VGA_G, // Output VGA G component
|
||||
output wire [3:0] VGA_B, // Output VGA B component
|
||||
output reg VGA_HS, // Output VGA horizontal sync
|
||||
output reg VGA_VS, // Output VGA vertical sync
|
||||
output wire vs_nintr, // Vertical retrace interrupt
|
||||
|
||||
output wire [12:0] vram_address,// Address request to the video RAM
|
||||
input wire [7:0] vram_data, // Data read from the video RAM
|
||||
|
||||
input wire [2:0] border // Border color index value
|
||||
);
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// VGA 640x480 Sync pulses generator
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
reg [9:0] vga_hc; // Horizontal counter
|
||||
reg [9:0] vga_vc; // Vertical counter
|
||||
reg [4:0] frame; // Frame counter, used for the flash attribute
|
||||
|
||||
always @(posedge clk_pix)
|
||||
begin
|
||||
vga_hc <= vga_hc + 10'b1; // With each pixel clock, advance the horizontal counter
|
||||
//---------------------------------------------------------------
|
||||
// Horizontal sync and line end timings
|
||||
//---------------------------------------------------------------
|
||||
case (vga_hc)
|
||||
96: VGA_HS <= 1;
|
||||
800: begin
|
||||
VGA_HS <= 0;
|
||||
vga_hc <= 0;
|
||||
vga_vc <= vga_vc + 10'b1;
|
||||
end
|
||||
endcase
|
||||
//---------------------------------------------------------------
|
||||
// Vertical sync and display end timings
|
||||
//---------------------------------------------------------------
|
||||
case (vga_vc)
|
||||
2: VGA_VS <= 1;
|
||||
525: begin
|
||||
VGA_VS <= 0;
|
||||
vga_vc <= 0;
|
||||
frame <= frame + 5'b1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// Generate interrupt at around the time of the vertical retrace start
|
||||
assign vs_nintr = (vga_vc=='0 && vga_hc[9:7]=='0)? '0 : '1;
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// VGA active display area 640x480
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
wire disp_enable;
|
||||
assign disp_enable = vga_hc>=144 && vga_hc<784 && vga_vc>=35 && vga_vc<515;
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// Fetch screen data from RAM based on the current video counters
|
||||
// Spectrum resolution of 256x192 is line-doubled to 512x384 sub-frame
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
wire screen_en;
|
||||
assign screen_en = vga_hc>=208 && vga_hc<720 && vga_vc>=83 && vga_vc<467;
|
||||
|
||||
reg [7:0] bits_prefetch; // Line bitmap data prefetch register
|
||||
reg [7:0] attr_prefetch; // Attribute data prefetch register
|
||||
|
||||
// At the first clock of each new character, prefetch values are latched into these:
|
||||
reg [7:0] bits; // Current line bitmap data register
|
||||
reg [7:0] attr; // Current attribute data register
|
||||
|
||||
wire [4:0] pix_x; // Column 0-31
|
||||
wire [7:0] pix_y; // Active display pixel Y coordinate
|
||||
// We use 16 clocks for 1 byte of display; also prefetch 1 byte (+16)
|
||||
wire [9:0] xd = vga_hc-10'd192; // =vga_hc-208+16
|
||||
assign pix_x = xd[8:4]; // Effectively divide by 16
|
||||
wire [9:0] yd = vga_vc-10'd83; // Lines are (also) doubled vertically
|
||||
assign pix_y = yd[8:1]; // Effectively divide by 2
|
||||
|
||||
always @(posedge clk_pix)
|
||||
begin
|
||||
case (vga_hc[3:0])
|
||||
// Format the address into the bitmap which is a swizzle of coordinate parts
|
||||
10: vram_address <= {pix_y[7:6], pix_y[2:0], pix_y[5:3], pix_x};
|
||||
12: begin
|
||||
bits_prefetch <= vram_data;
|
||||
// Format the address into the attribute map
|
||||
vram_address <= {3'b110, pix_y[7:3], pix_x};
|
||||
end
|
||||
14: attr_prefetch <= vram_data;
|
||||
// Last tick before a new character: load working bitmap and attribute registers
|
||||
15: begin
|
||||
attr <= attr_prefetch;
|
||||
bits <= bits_prefetch;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// Pixel data generator
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
wire [2:0] ink; // INK color (index into the palette)
|
||||
wire [2:0] paper; // PAPER color
|
||||
wire bright; // BRIGHT attribute bit
|
||||
wire flash; // FLASH attribute bit
|
||||
wire pixbit; // Current pixel to render
|
||||
wire inverted; // Are the pixel's attributes inverted?
|
||||
|
||||
// Output a pixel bit based on the VGA horizontal counter. This could have been
|
||||
// a shift register but a mux works as well since we are writing out each pixel
|
||||
// twice (required by this VGA clock rate)
|
||||
always @(*) // always_comb
|
||||
begin
|
||||
case (vga_hc[3:1])
|
||||
0: pixbit = bits[7];
|
||||
1: pixbit = bits[6];
|
||||
2: pixbit = bits[5];
|
||||
3: pixbit = bits[4];
|
||||
4: pixbit = bits[3];
|
||||
5: pixbit = bits[2];
|
||||
6: pixbit = bits[1];
|
||||
7: pixbit = bits[0];
|
||||
endcase
|
||||
end
|
||||
|
||||
assign flash = attr[7];
|
||||
assign bright = attr[6];
|
||||
assign inverted = flash & frame[4];
|
||||
assign ink = inverted? attr[5:3] : attr[2:0];
|
||||
assign paper = inverted? attr[2:0] : attr[5:3];
|
||||
|
||||
// The final color index depends on where we are (active display area, border) and
|
||||
// whether we are rendering INK or PAPER color, including the brightness bit
|
||||
assign cindex = screen_en? pixbit? {bright,ink} : {bright,paper} : {1'b0,border[2:0]};
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// Color lookup table
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
wire [3:0] cindex;
|
||||
wire [11:0] pix_rgb;
|
||||
|
||||
always @(*) // always_comb
|
||||
begin
|
||||
case (cindex[3:0])
|
||||
// Normal color
|
||||
0: pix_rgb = 12'h000; // BLACK
|
||||
1: pix_rgb = 12'h00D; // BLUE
|
||||
2: pix_rgb = 12'hD00; // RED
|
||||
3: pix_rgb = 12'hD0D; // MAGENTA
|
||||
4: pix_rgb = 12'h0D0; // GREEN
|
||||
5: pix_rgb = 12'h0DD; // CYAN
|
||||
6: pix_rgb = 12'hDD0; // YELLOW
|
||||
7: pix_rgb = 12'hDDD; // WHITE
|
||||
// "Bright" bit is set
|
||||
8: pix_rgb = 12'h000; // BLACK remains black
|
||||
9: pix_rgb = 12'h00F;
|
||||
10: pix_rgb = 12'hF00;
|
||||
11: pix_rgb = 12'hF0F;
|
||||
12: pix_rgb = 12'h0F0;
|
||||
13: pix_rgb = 12'h0FF;
|
||||
14: pix_rgb = 12'hFF0;
|
||||
15: pix_rgb = 12'hFFF;
|
||||
endcase
|
||||
end
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// VGA RGB output drivers
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
assign VGA_R[3:0] = disp_enable? pix_rgb[11:8] : '0;
|
||||
assign VGA_G[3:0] = disp_enable? pix_rgb[7:4] : '0;
|
||||
assign VGA_B[3:0] = disp_enable? pix_rgb[3:0] : '0;
|
||||
|
||||
endmodule
|
||||
+230
@@ -0,0 +1,230 @@
|
||||
//============================================================================
|
||||
// ZX Spectrum keyboard input
|
||||
//
|
||||
// This module takes scan-codes from the attached PS/2 keyboard and sets
|
||||
// corresponding ZX key bitfields which are read by the 'IN' instructions.
|
||||
//
|
||||
// PS/2 | ZX Spectrum
|
||||
// ----------+-----------------
|
||||
// CTRL | CAPS SHIFT
|
||||
// ALT | SYMBOL SHIFT
|
||||
//
|
||||
// For convenience, in addition to regular alpha-numeric keys, this code
|
||||
// simulates several other standard symbols on the PS/2 keyboard.
|
||||
//
|
||||
// PS/2 | ZX Spectrum
|
||||
// ----------+-----------------
|
||||
// BACKSPACE | DELETE
|
||||
// Arrows Left, Right, Up, Down
|
||||
// ESC | BREAK (CAPS+SPACE)
|
||||
// SHIFT => PS/2 shift for additional keys: -_ += ;: "' <, >. ?/
|
||||
//
|
||||
// Copyright (C) 2014-2016 Goran Devic
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License along
|
||||
// with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
//============================================================================
|
||||
module zx_keyboard
|
||||
(
|
||||
input wire clk,
|
||||
input wire nreset, // Active low reset
|
||||
|
||||
// Output ZX-specific keyboard codes when requested by the ULA access
|
||||
input wire [15:0] A, // Address bus
|
||||
output wire [4:0] key_row, // Output the state of a requested row of keys
|
||||
|
||||
// Input key scan codes from the PS/2 keyboard
|
||||
input wire [7:0] scan_code, // PS/2 scan-code
|
||||
input wire scan_code_ready, // Active for 1 clock: a scan code is ready
|
||||
input wire scan_code_error, // Error receiving PS/2 keyboard data
|
||||
output wire pressed // Signal that a key is pressed
|
||||
);
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
//
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
reg [4:0] keys [0:7]; // 8 rows of 5 bits each: contains 0 for a pressed key at a specific location, 1 otherwise
|
||||
|
||||
reg released; // Tracks "released" scan code (F0): contains 0 when a key is pressed, 1 otherwise
|
||||
reg extended; // Tracks "extended" scan code (E0)
|
||||
reg shifted; // Tracks local "shifted" state
|
||||
|
||||
// Calculate a "key is pressed" signal
|
||||
assign pressed = ~(&keys[7] & &keys[6] & &keys[5] & &keys[4] & &keys[3] & &keys[2] & &keys[1] & &keys[0]);
|
||||
|
||||
// Output requested row of keys continously
|
||||
assign key_row =
|
||||
(~A[8] ? keys[0] : 5'b11111) &
|
||||
(~A[9] ? keys[1] : 5'b11111) &
|
||||
(~A[10] ? keys[2] : 5'b11111) &
|
||||
(~A[11] ? keys[3] : 5'b11111) &
|
||||
(~A[12] ? keys[4] : 5'b11111) &
|
||||
(~A[13] ? keys[5] : 5'b11111) &
|
||||
(~A[14] ? keys[6] : 5'b11111) &
|
||||
(~A[15] ? keys[7] : 5'b11111);
|
||||
|
||||
always @(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset) begin
|
||||
released <= 0;
|
||||
extended <= 0;
|
||||
shifted <= 0;
|
||||
|
||||
keys[0] <= '1;
|
||||
keys[1] <= '1;
|
||||
keys[2] <= '1;
|
||||
keys[3] <= '1;
|
||||
keys[4] <= '1;
|
||||
keys[5] <= '1;
|
||||
keys[6] <= '1;
|
||||
keys[7] <= '1;
|
||||
end else
|
||||
if (scan_code_ready) begin
|
||||
if (scan_code==8'hE0) // Extended code prefix byte
|
||||
extended <= 1;
|
||||
else if (scan_code==8'hF0) // Break code prefix byte
|
||||
released <= 1;
|
||||
else begin
|
||||
// Cancel release/extended flags for the next clock
|
||||
extended <= 0;
|
||||
released <= 0;
|
||||
|
||||
if (extended) begin
|
||||
// Extended keys
|
||||
case (scan_code)
|
||||
8'h6B: begin // LEFT
|
||||
keys[0][0] <= released; // CAPS SHIFT
|
||||
keys[3][4] <= released; // 5
|
||||
end
|
||||
8'h72: begin // DOWN
|
||||
keys[0][0] <= released; // CAPS SHIFT
|
||||
keys[4][4] <= released; // 6
|
||||
end
|
||||
8'h75: begin // UP
|
||||
keys[0][0] <= released; // CAPS SHIFT
|
||||
keys[4][3] <= released; // 7
|
||||
end
|
||||
8'h74: begin // RIGHT
|
||||
keys[0][0] <= released; // CAPS SHIFT
|
||||
keys[4][2] <= released; // 8
|
||||
end
|
||||
endcase
|
||||
end
|
||||
else begin
|
||||
// For each PS/2 scan-code, set the ZX keyboard matrix state
|
||||
case (scan_code)
|
||||
8'h12: shifted <= !released; // Local SHIFT key (left)
|
||||
8'h59: shifted <= !released; // Local SHIFT key (right)
|
||||
|
||||
8'h14: keys[0][0] <= released; // CAPS SHIFT = Left or right Ctrl
|
||||
|
||||
8'h1A: keys[0][1] <= released; // Z
|
||||
8'h22: keys[0][2] <= released; // X
|
||||
8'h21: keys[0][3] <= released; // C
|
||||
8'h2A: keys[0][4] <= released; // V
|
||||
|
||||
8'h1C: keys[1][0] <= released; // A
|
||||
8'h1B: keys[1][1] <= released; // S
|
||||
8'h23: keys[1][2] <= released; // D
|
||||
8'h2B: keys[1][3] <= released; // F
|
||||
8'h34: keys[1][4] <= released; // G
|
||||
|
||||
8'h15: keys[2][0] <= released; // Q
|
||||
8'h1D: keys[2][1] <= released; // W
|
||||
8'h24: keys[2][2] <= released; // E
|
||||
8'h2D: keys[2][3] <= released; // R
|
||||
8'h2C: keys[2][4] <= released; // T
|
||||
|
||||
8'h16: keys[3][0] <= released; // 1
|
||||
8'h1E: keys[3][1] <= released; // 2
|
||||
8'h26: keys[3][2] <= released; // 3
|
||||
8'h25: keys[3][3] <= released; // 4
|
||||
8'h2E: keys[3][4] <= released; // 5
|
||||
|
||||
8'h45: keys[4][0] <= released; // 0
|
||||
8'h46: keys[4][1] <= released; // 9
|
||||
8'h3E: keys[4][2] <= released; // 8
|
||||
8'h3D: keys[4][3] <= released; // 7
|
||||
8'h36: keys[4][4] <= released; // 6
|
||||
|
||||
8'h4D: keys[5][0] <= released; // P
|
||||
8'h44: keys[5][1] <= released; // O
|
||||
8'h43: keys[5][2] <= released; // I
|
||||
8'h3C: keys[5][3] <= released; // U
|
||||
8'h35: keys[5][4] <= released; // Y
|
||||
|
||||
8'h5A: keys[6][0] <= released; // ENTER
|
||||
8'h4B: keys[6][1] <= released; // L
|
||||
8'h42: keys[6][2] <= released; // K
|
||||
8'h3B: keys[6][3] <= released; // J
|
||||
8'h33: keys[6][4] <= released; // H
|
||||
|
||||
8'h29: keys[7][0] <= released; // SPACE
|
||||
8'h11: keys[7][1] <= released; // SYMBOL SHIFT (Red) = Left and right Alt
|
||||
8'h3A: keys[7][2] <= released; // M
|
||||
8'h31: keys[7][3] <= released; // N
|
||||
8'h32: keys[7][4] <= released; // B
|
||||
|
||||
8'h66: begin // BACKSPACE
|
||||
keys[0][0] <= released;
|
||||
keys[4][0] <= released;
|
||||
end
|
||||
8'h76: begin // ESC -> BREAK
|
||||
keys[0][0] <= released; // CAPS SHIFT
|
||||
keys[7][0] <= released; // SPACE
|
||||
end
|
||||
// With shifted keys, we need to make inactive (set to 1) other corresponding key
|
||||
// Otherwise, it will stay active if the shift was released first
|
||||
8'h4E: begin // - or (shifted) _
|
||||
keys[7][1] <= released; // SYMBOL SHIFT (Red)
|
||||
keys[4][0] <= shifted ? released : 1'b1; // 0
|
||||
keys[6][3] <= shifted ? 1'b1 : released; // J
|
||||
end
|
||||
8'h55: begin // = or (shifted) +
|
||||
keys[7][1] <= released; // SYMBOL SHIFT (Red)
|
||||
keys[6][2] <= shifted ? released : 1'b1; // K
|
||||
keys[6][1] <= shifted ? 1'b1 : released; // L
|
||||
end
|
||||
8'h52: begin // ' or (shifted) "
|
||||
keys[7][1] <= released; // SYMBOL SHIFT (Red)
|
||||
keys[5][0] <= shifted ? released : 1'b1; // P
|
||||
keys[4][3] <= shifted ? 1'b1 : released; // 7
|
||||
end
|
||||
8'h4C: begin // ; or (shifted) :
|
||||
keys[7][1] <= released; // SYMBOL SHIFT (Red)
|
||||
keys[0][1] <= shifted ? released : 1'b1; // Z
|
||||
keys[5][1] <= shifted ? 1'b1 : released; // O
|
||||
end
|
||||
8'h41: begin // , or (shifted) <
|
||||
keys[7][1] <= released; // SYMBOL SHIFT (Red)
|
||||
keys[2][3] <= shifted ? released : 1'b1; // R
|
||||
keys[7][3] <= shifted ? 1'b1 : released; // N
|
||||
end
|
||||
8'h49: begin // . or (shifted) >
|
||||
keys[7][1] <= released; // SYMBOL SHIFT (Red)
|
||||
keys[2][4] <= shifted ? released : 1'b1; // T
|
||||
keys[7][2] <= shifted ? 1'b1 : released; // M
|
||||
end
|
||||
8'h4A: begin // / or (shifted) ?
|
||||
keys[7][1] <= released; // SYMBOL SHIFT (Red)
|
||||
keys[0][3] <= shifted ? released : 1'b1; // C
|
||||
keys[0][4] <= shifted ? 1'b1 : released; // V
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user