Fixed video, kbd and buzzer
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+248
@@ -0,0 +1,248 @@
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module spectrum(output wire[7:0] LED,
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output wire[33:0] GPIO_0,
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input wire CLOCK_50, // Input clock 50 MHz
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input wire[1:0] KEY, // 0 = RESET button; active low, 1 = NMI button
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input wire PS2_CLK,
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input wire PS2_DAT,
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inout wire I2C_SCLK,
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inout wire I2C_SDAT,
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output wire AUD_XCK,
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output wire AUD_ADCLRCK,
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output wire AUD_DACLRCK,
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output wire AUD_BCLK,
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output wire AUD_DACDAT,
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input wire AUD_ADCDAT,
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output wire [3:0] VGA_R,
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output wire [3:0] VGA_G,
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output wire [3:0] VGA_B,
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output reg VGA_HS,
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output reg VGA_VS,
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input wire[3:0] SW, // 0 = ROM selection, 1 = enable/disable interrupts, 2 = turbo speed
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output wire[33:0] GPIO_1 // Exports CPU chip pins
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);
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`default_nettype none
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wire reset;
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wire locked;
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assign reset = locked & KEY[0:0];
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// Export selected pins to the extension connector
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assign GPIO_1[15:0] = A[15:0];
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assign GPIO_1[23:16] = D[7:0];
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assign GPIO_1[31:24] = {nM1,nMREQ,nIORQ,nRD,nWR,nRFSH,nHALT,nBUSACK};
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// Internal buses and address map selection logic
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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wire [15:0] A; // Global address bus
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wire [7:0] D; // CPU data bus
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wire [7:0] ram_data; // Internal 16K RAM data
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wire RamWE;
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assign RamWE = A[15:14]==2'b01 && nIORQ==1 && nRD==1 && nWR==0;
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wire ExtRamWE; // Extended (and external) 32K RAM
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assign ExtRamWE = A[15]==1 && nIORQ==1 && nRD==1 && nWR==0;
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wire [7:0] ula_data; // ULA
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wire io_we;
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assign io_we = nIORQ==0 && nRD==1 && nWR==0;
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// Memory map:
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// 0000 - 3FFF 16K ROM (mapped to rom0)
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// 4000 - 7FFF 16K dual-port ram0
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// 8000 - FFFF 32K RAM (mapped to ram1)
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always @(*) // always_comb
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begin
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case ({nIORQ,nRD,nWR})
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// -------------------------------- Memory read --------------------------------
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3'b101: begin
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casez (A[15:14])
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2'b00: D[7:0] = rom_data;
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2'b01: D[7:0] = ram0_data;
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2'b1?: D[7:0] = ram1_data;
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endcase
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end
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// ---------------------------------- IO read ----------------------------------
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3'b001: begin
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// Normally data supplied by the ULA
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D[7:0] = ula_data;
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// Kempston joystick at the IO address 0x1F; active bits are high:
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// FIRE UP DOWN LEFT RIGHT
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// if (A[7:0]==8'h1F) begin
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// D[7:0] = { 3'b0, !kempston[4],!kempston[0],!kempston[1],!kempston[2],!kempston[3] };
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// end
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end
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default:
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D[7:0] = {8{1'bz}};
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endcase
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end
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// ----------------------------------------------------
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// Instantiate ROM, 16K
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// ----------------------------------------------------
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wire[7:0] rom_data;
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rom0 rom(
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.clock(clk_cpu),
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.address(A),
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.q(rom_data)
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);
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// ----------------------------------------------------
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// Instantiate RAM0, 16K, dual port
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// ----------------------------------------------------
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wire clk_vram;
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wire[7:0] ram0_data;
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// "A" port is the CPU side, "B" port is the VGA image generator in the ULA
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ram16 ram0(
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.clock(clk_vram),
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.address_a(A[13:0]),
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.data_a(D),
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.q_a(ram0_data),
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.wren_a(RamWE),
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.address_b({1'b0, vram_address}),
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.data_b(8'b0),
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.q_b(vram_data),
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.wren_b(0)
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);
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// Rest of RAM, 32K
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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wire[7:0] ram1_data;
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ram32 ram1(
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.clock(clk_cpu),
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.address(A[14:0]),
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.data(D),
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.q(ram1_data),
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.wren(0)
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);
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// Instantiate ULA
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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wire clk_cpu; // Global CPU clock of 3.5 MHz
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assign LED[2:2] = SW[2:2]; // Glow red when in turbo mode (7.0 MHz)
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wire [12:0] vram_address; // ULA video block requests a byte from the video RAM
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wire [7:0] vram_data; // ULA video block reads a byte from the video RAM
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wire vs_nintr; // Generates a vertical retrace interrupt
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wire pressed; // Show that a key is being pressed
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wire beeper; // Show the beeper state
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ula ula_(
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//-------- Clocks and reset -----------------
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.CLOCK_50 (CLOCK_50), // Input clock 50 MHz
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.turbo (SW[2:2]), // Turbo speed (3.5 MHz x 2 = 7.0 MHz)
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.clk_vram (clk_vram),
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.nreset (reset), // KEY0 is reset; on DE1, keys are active low!
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.locked (locked), // PLL is locked signal
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//-------- CPU control ----------------------
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.clk_cpu (clk_cpu), // Generates CPU clock of 3.5 MHz
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.vs_nintr (vs_nintr), // Generates a vertical retrace interrupt
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//-------- Address and data buses -----------
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.A (A), // Input address bus
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.D (D), // Input data bus
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.ula_data (ula_data), // Output data
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.io_we (io_we), // Write enable to data register through IO
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.vram_address (vram_address),// ULA video block requests a byte from the video RAM
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.vram_data (vram_data), // ULA video block reads a byte from the video RAM
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//-------- PS/2 Keyboard --------------------
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.PS2_CLK (PS2_CLK),
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.PS2_DAT (PS2_DAT),
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.pressed (pressed),
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//-------- Audio (Tape player) --------------
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.I2C_SCLK (I2C_SCLK),
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.I2C_SDAT (I2C_SDAT),
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.AUD_XCK (AUD_XCK),
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.AUD_ADCLRCK (AUD_ADCLRCK),
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.AUD_DACLRCK (AUD_DACLRCK),
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.AUD_BCLK (AUD_BCLK),
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.AUD_DACDAT (AUD_DACDAT),
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.AUD_ADCDAT (AUD_ADCDAT),
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.beeper (beeper),
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//-------- VGA connector --------------------
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.VGA_R (VGA_R),
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.VGA_G (VGA_G),
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.VGA_B (VGA_B),
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.VGA_HS (VGA_HS),
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.VGA_VS (VGA_VS)
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);
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// Instantiate A-Z80 CPU
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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wire nM1;
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wire nMREQ;
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wire nIORQ;
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wire nRD;
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wire nWR;
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wire nRFSH;
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wire nHALT;
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wire nBUSACK;
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wire nWAIT = 1;
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wire nINT = (SW[1:1]==0)? vs_nintr : 1'b1;// SW1 disables interrupts and, hence, keyboard
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assign LED[0] = SW[1:1]; // Glow red when interrupts are *disabled*
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wire nNMI = KEY[1:1]; // Pressing KEY1 issues a NMI
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wire nBUSRQ = 1;
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z80_top_direct_n z80_(
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.nM1 (nM1),
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.nMREQ (nMREQ),
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.nIORQ (nIORQ),
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.nRD (nRD),
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.nWR (nWR),
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.nRFSH (nRFSH),
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.nHALT (nHALT),
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.nBUSACK (nBUSACK),
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.nWAIT (nWAIT),
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.nINT (nINT),
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.nNMI (nNMI),
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.nRESET (reset),
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.nBUSRQ (nBUSRQ),
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.CLK (clk_cpu),
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.A (A),
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.D (D)
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);
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// reg[21:0] counter;
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// always @(posedge CLOCK_50)
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// begin
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// counter <= counter + 1;
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// if (counter == 0)
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// begin
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// A <= A + 1;
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// end
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// end
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// // make the leds blink with rom and ram0 data
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// assign LED[3:0] = rom_data[3:0];
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// assign LED[7:4] = ram0_data[7:4];
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// // expose memories at A to GPIO_0
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// assign GPIO_0[7:0] = rom_data;
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// assign GPIO_0[15:8] = ram0_data;
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// assign GPIO_0[23:16] = ram1_data;
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// assign GPIO_0[31:24] = vram_data;
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endmodule
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