Fixed video, kbd and buzzer
This commit is contained in:
@@ -0,0 +1,76 @@
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These files are part of the Fuse emulator Z80 test vectors:
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http://fuse-emulator.sourceforge.net/
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File formats
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============
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tests.in
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--------
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Each test has the format:
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<arbitrary test description>
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AF BC DE HL AF' BC' DE' HL' IX IY SP PC
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I R IFF1 IFF2 IM <halted> <tstates>
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<halted> specifies whether the Z80 is halted.
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<tstates> specifies the number of tstates to run the test for, in
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decimal; the number actually executed may be higher, as the final
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instruction is allowed to complete.
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Then followed by lines specifying the initial memory setup. Each has
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the format:
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<start address> <byte1> <byte2> ... -1
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eg
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1234 56 78 9a -1
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says to put 0x56 at 0x1234, 0x78 at 0x1235 and 0x9a at 0x1236.
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Finally, -1 to end the test. Blank lines may follow before the next test.
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tests.expected
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--------------
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Each test output starts with the test description, followed by a list
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of 'events': each has the format
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<time> <type> <address> <data>
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<time> is simply the time at which the event occurs.
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<type> is one of MR (memory read), MW (memory write), MC (memory
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contend), PR (port read), PW (port write) or PC (port contend).
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<address> is the address (or IO port) affected.
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<data> is the byte written or read. Missing for contentions.
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After that, lines specifying AF, BC etc as for .in files. <tstates>
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now specifies the final time.
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After that, lines specifying which bits of memory have changed since
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the initial setup. Same format as for .in files.
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Why some specific tests are here
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================================
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37_{1,2,3}: check the behaviour of SCF with respect to bits 3 and 5
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(bug fixed on 20040225).
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cb{4,5,6,7}{7,f}_1: designed to check that bits 3 and 5 are copied to
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F only for BIT 3,<arg> and BIT 5,<arg> respectively
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(bug fixed on 20040225).
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However, later research has revealed the bits 3
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and 5 are copied on all BIT instructions, so these
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tests are now essentially redundant.
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d{3,b}_{1,2,3}: check for correct port contention on IO in the four
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relevant states (port high byte in 0x40 to 0x7f or not,
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port low bit set or reset).
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dd00.in, ddfd00.in: test timings of "extended NOP" opcodes DD 00 and
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DD FD 00; the extra 00 at the end is to check the
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next opcode executes at the right time (bug fixed
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on 20060722).
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@@ -0,0 +1,263 @@
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00 NOP
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0 MC 0000
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4 MR 0000 00
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0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001
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00 01 0 0 0 0 4
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ed67 RRD
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0 MC 0000
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4 MR 0000 ed
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4 MC 0001
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8 MR 0001 67
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8 MC b9de
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11 MR b9de 93
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11 MC b9de
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12 MC b9de
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13 MC b9de
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14 MC b9de
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15 MC b9de
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18 MW b9de 69
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3324 b16a a4db b9de 0000 0000 0000 0000 0000 0000 0000 0002
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00 02 0 0 0 0 18
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b9de 69 -1
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ed6f RLD
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0 MC 0000
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4 MR 0000 ed
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4 MC 0001
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8 MR 0001 6f
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8 MC 403c
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11 MR 403c c4
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11 MC 403c
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12 MC 403c
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13 MC 403c
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14 MC 403c
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15 MC 403c
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18 MW 403c 45
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6c2d 7a7a ecf0 403c 0000 0000 0000 0000 0000 0000 0000 0002
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00 02 0 0 0 0 18
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403c 45 -1
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81 ADD A,C
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0 MC 0000
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4 MR 0000 81
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3031 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001
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00 01 0 0 0 0 4
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cb41 BIT 0,C
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0 MC 0000
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4 MR 0000 cb
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4 MC 0001
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8 MR 0001 41
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9e10 1b43 954e 7be9 0000 0000 0000 0000 0000 0000 0000 0002
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00 02 0 0 0 0 8
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cb93 RES 2,E
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0 MC 0000
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4 MR 0000 cb
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4 MC 0001
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8 MR 0001 93
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c200 4e05 b3f8 2234 0000 0000 0000 0000 0000 0000 0000 0002
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00 02 0 0 0 0 8
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cbe5 SET 4,L
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0 MC 0000
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4 MR 0000 cb
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4 MC 0001
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8 MR 0001 e5
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ca00 df0d d588 b49f 0000 0000 0000 0000 0000 0000 0000 0002
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00 02 0 0 0 0 8
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8c ADC A,H
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0 MC 0000
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4 MR 0000 8c
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d191 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001
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00 01 0 0 0 0 4
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92 SUB D
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0 MC 0000
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4 MR 0000 92
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d582 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001
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00 01 0 0 0 0 4
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9d SBC A,L
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0 MC 0000
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4 MR 0000 9d
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4f1a 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001
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00 01 0 0 0 0 4
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a3 AND E
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0 MC 0000
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4 MR 0000 a3
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0514 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001
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00 01 0 0 0 0 4
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ae XOR (HL)
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0 MC 0000
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4 MR 0000 ae
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4 MC dca6
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7 MR dca6 49
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bca8 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001
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00 01 0 0 0 0 7
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b4 OR H
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0 MC 0000
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4 MR 0000 b4
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fda8 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001
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00 01 0 0 0 0 4
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bf CP A
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0 MC 0000
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4 MR 0000 bf
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f562 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001
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00 01 0 0 0 0 4
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43 LD B,E
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0 MC 0000
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4 MR 0000 43
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0200 d898 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001
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00 01 0 0 0 0 4
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6e LD L,(HL)
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0 MC 0000
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4 MR 0000 6e
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4 MC a169
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7 MR a169 50
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0200 cf98 90d8 a150 0000 0000 0000 0000 0000 0000 0000 0001
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00 01 0 0 0 0 7
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e3 EX (SP),HL
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0 MC 0000
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4 MR 0000 e3
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4 MC 0373
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7 MR 0373 8e
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7 MC 0374
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10 MR 0374 e1
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10 MC 0374
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11 MC 0374
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14 MW 0374 4d
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14 MC 0373
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17 MW 0373 22
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17 MC 0373
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18 MC 0373
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0000 0000 0000 e18e 0000 0000 0000 0000 0000 0000 0373 0001
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00 01 0 0 0 0 19
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0373 22 4d -1
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03 INC BC
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0 MC 0000
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4 MR 0000 03
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4 MC 0001
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5 MC 0001
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0000 789b 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001
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00 01 0 0 0 0 6
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3b DEC SP
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0 MC 0000
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4 MR 0000 3b
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4 MC 0001
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5 MC 0001
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0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 9d35 0001
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00 01 0 0 0 0 6
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07 RLCA
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0 MC 0000
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4 MR 0000 07
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1101 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001
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00 01 0 0 0 0 4
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1f RRA
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0 MC 0000
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4 MR 0000 1f
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00c5 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001
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00 01 0 0 0 0 4
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cb09 RRC C
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0 MC 0000
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4 MR 0000 cb
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4 MC 0001
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8 MR 0001 09
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182c 122e dd97 59c6 0000 0000 0000 0000 0000 0000 0000 0002
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00 02 0 0 0 0 8
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cb11 RL C
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0 MC 0000
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4 MR 0000 cb
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4 MC 0001
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8 MR 0001 11
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65ac e2b8 4b8a ed42 0000 0000 0000 0000 0000 0000 0000 0002
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00 02 0 0 0 0 8
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cb36 SLL (HL)*
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0 MC 0000
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4 MR 0000 cb
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4 MC 0001
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8 MR 0001 36
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8 MC 6d38
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11 MR 6d38 f1
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11 MC 6d38
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12 MC 6d38
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15 MW 6d38 e3
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8aa1 1185 1dde 6d38 0000 0000 0000 0000 0000 0000 0000 0002
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00 02 0 0 0 0 15
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6d38 e3 -1
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cb52 BIT 2,D
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0 MC 0000
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4 MR 0000 cb
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4 MC 0001
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8 MR 0001 52
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8b74 ff7a b0ff ac44 0000 0000 0000 0000 0000 0000 0000 0002
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00 02 0 0 0 0 8
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cb93 RES 2,E
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0 MC 0000
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4 MR 0000 cb
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4 MC 0001
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8 MR 0001 93
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c200 4e05 b3f8 2234 0000 0000 0000 0000 0000 0000 0000 0002
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00 02 0 0 0 0 8
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cbc4 SET 0,H
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0 MC 0000
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4 MR 0000 cb
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4 MC 0001
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8 MR 0001 c4
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7e00 545a 6ecf 5976 0000 0000 0000 0000 0000 0000 0000 0002
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00 02 0 0 0 0 8
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dd75 LD (IX+d),L
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0 MC 0000
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4 MR 0000 dd
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4 MC 0001
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8 MR 0001 75
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8 MC 0002
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11 MR 0002 30
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11 MC 0002
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12 MC 0002
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13 MC 0002
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14 MC 0002
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15 MC 0002
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16 MC ae7c
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19 MW ae7c 4f
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5772 e833 b63e 734f 0000 0000 0000 0000 ae4c e8c2 0000 0003
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00 02 0 0 0 0 19
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ae7c 4f -1
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dd4e LD C,(IX+d)
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0 MC 0000
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4 MR 0000 dd
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4 MC 0001
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8 MR 0001 4e
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8 MC 0002
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11 MR 0002 2e
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11 MC 0002
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12 MC 0002
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13 MC 0002
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14 MC 0002
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15 MC 0002
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16 MC d979
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19 MR d979 76
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7bf7 6676 8d55 def2 0000 0000 0000 0000 d94b 17fb 0000 0003
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00 02 0 0 0 0 19
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@@ -0,0 +1,197 @@
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00 NOP
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0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
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00 00 0 0 0 0 1
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0000 00 -1
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-1
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ed67 RRD
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3624 b16a a4db b9de 0000 0000 0000 0000 0000 0000 0000 0000
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00 00 0 0 0 0 1
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0000 ed 67 -1
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b9de 93 -1
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-1
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ed6f RLD
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658b 7a7a ecf0 403c 0000 0000 0000 0000 0000 0000 0000 0000
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00 00 0 0 0 0 1
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0000 ed 6f -1
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403c c4 -1
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-1
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81 ADD A,C
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f500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000
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00 00 0 0 0 0 1
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0000 81 -1
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dca6 49 -1
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-1
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cb41 BIT 0,C
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9e00 1b43 954e 7be9 0000 0000 0000 0000 0000 0000 0000 0000
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00 00 0 0 0 0 1
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0000 cb 41 -1
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7be9 f7 -1
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-1
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cb93 RES 2,E
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c200 4e05 b3f8 2234 0000 0000 0000 0000 0000 0000 0000 0000
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00 00 0 0 0 0 1
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0000 cb 93 -1
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2234 a0 -1
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-1
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cbe5 SET 4,L
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ca00 df0d d588 b48f 0000 0000 0000 0000 0000 0000 0000 0000
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00 00 0 0 0 0 1
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0000 cb e5 -1
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b48f cf -1
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-1
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8c ADC A,H
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f500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000
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00 00 0 0 0 0 1
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0000 8c -1
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dca6 49 -1
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-1
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92 SUB D
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f500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000
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00 00 0 0 0 0 1
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0000 92 -1
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dca6 49 -1
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-1
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9d SBC A,L
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f500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000
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00 00 0 0 0 0 1
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0000 9d -1
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dca6 49 -1
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-1
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a3 AND E
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f500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000
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00 00 0 0 0 0 1
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0000 a3 -1
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dca6 49 -1
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-1
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ae XOR (HL)
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f500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000
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00 00 0 0 0 0 1
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0000 ae -1
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dca6 49 -1
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-1
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b4 OR H
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f500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000
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00 00 0 0 0 0 1
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0000 b4 -1
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dca6 49 -1
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-1
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bf CP A
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f500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000
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00 00 0 0 0 0 1
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0000 bf -1
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dca6 49 -1
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-1
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43 LD B,E
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0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000
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00 00 0 0 0 0 1
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0000 43 -1
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a169 50 -1
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-1
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6e LD L,(HL)
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0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000
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00 00 0 0 0 0 1
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0000 6e -1
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a169 50 -1
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-1
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e3 EX (SP),HL
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0000 0000 0000 4d22 0000 0000 0000 0000 0000 0000 0373 0000
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00 00 0 0 0 0 1
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0000 e3 -1
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0373 8e e1 -1
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-1
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03 INC BC
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0000 789a 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
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00 00 0 0 0 0 1
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0000 03 -1
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-1
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3b DEC SP
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0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 9d36 0000
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00 00 0 0 0 0 1
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0000 3b -1
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-1
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07 RLCA
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8800 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
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00 00 0 0 0 0 1
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0000 07 -1
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-1
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1f RRA
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01c4 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
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00 00 0 0 0 0 1
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0000 1f -1
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-1
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cb09 RRC C
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1800 125c dd97 59c6 0000 0000 0000 0000 0000 0000 0000 0000
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00 00 0 0 0 0 1
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0000 cb 09 -1
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59c6 9e -1
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-1
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cb11 RL C
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6500 e25c 4b8a ed42 0000 0000 0000 0000 0000 0000 0000 0000
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00 00 0 0 0 0 1
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0000 cb 11 -1
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ed42 b7 -1
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-1
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cb36 SLL (HL)*
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8a00 1185 1dde 6d38 0000 0000 0000 0000 0000 0000 0000 0000
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00 00 0 0 0 0 1
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0000 cb 36 -1
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6d38 f1 -1
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-1
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cb52 BIT 2,D
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8b00 ff7a b0ff ac44 0000 0000 0000 0000 0000 0000 0000 0000
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00 00 0 0 0 0 1
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0000 cb 52 -1
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ac44 00 -1
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-1
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cb93 RES 2,E
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c200 4e05 b3f8 2234 0000 0000 0000 0000 0000 0000 0000 0000
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00 00 0 0 0 0 1
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0000 cb 93 -1
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2234 a0 -1
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-1
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cbc4 SET 0,H
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7e00 545a 6ecf 5876 0000 0000 0000 0000 0000 0000 0000 0000
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00 00 0 0 0 0 1
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0000 cb c4 -1
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5876 9d -1
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-1
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dd75 LD (IX+d),L
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5772 e833 b63e 734f 0000 0000 0000 0000 ae4c e8c2 0000 0000
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00 00 0 0 0 0 1
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0000 dd 75 30 -1
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-1
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dd4e LD C,(IX+d)
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7bf7 6605 8d55 def2 0000 0000 0000 0000 d94b 17fb 0000 0000
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00 00 0 0 0 0 1
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0000 dd 4e 2e -1
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d979 76 -1
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-1
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user