Fixed video, kbd and buzzer
This commit is contained in:
@@ -0,0 +1,72 @@
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//============================================================================
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// A-Z80 core, instantiates and connects all internal blocks.
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//
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// This file is included by the "z80_top_ifc_n" and "z80_top_direct" providing
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// interface binding and direct (no interface) binding.
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//============================================================================
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// Include a list of top-level signal wires
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`include "globals.vh"
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// Specific to simulation, some modules in the schematics need to be pre-initialized
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// to avoid starting simulations with unknown values in selected flip flops.
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reg fpga_reset = 1;
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always @(posedge clk)
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begin
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fpga_reset <= 0;
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end
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// Define internal data bus partitions segmented by data bus switches
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wire [7:0] db0; // Segment connecting data pins and IR
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wire [7:0] db1; // Segment leading to the ALU
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wire [7:0] db2; // Segment with msb part of the register address-side interface
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wire [7:0] db_hi_as; // Register file data bus segment high byte
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wire [7:0] db_lo_as; // Register file data bus segment low byte
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wire [6:0] prefix; // Instruction decode PLA prefix bitfield
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assign prefix = { ~use_ixiy, use_ixiy, ~in_halt, in_alu, table_xx, table_cb, table_ed };
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wire nM1_int; // External pins timing control
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assign nM1_int = !(setM1 | (fFetch & T1));
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`include "coremodules.vh"
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// Data path within the CPU in various forms, ending with data pins
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data_switch sw2_( .sw_up_en(bus_sw_2u), .sw_down_en(bus_sw_2d), .db_up(db1[7:0]), .db_down(db2[7:0]) );
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// Data switch SW1 with the data mask
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data_switch_mask sw1_( .sw_mask543_en(bus_sw_mask543_en), .sw_up_en(bus_sw_1u), .sw_down_en(bus_sw_1d), .db_up(db0[7:0]), .db_down(db1[7:0]) );
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/* This SystemVerilog-style code is kept for future reference
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// Control block
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clk_delay clk_delay_( .* );
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decode_state decode_state_( .* );
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execute execute_( .* );
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interrupts interrupts_( .*, .db(db0[4:3]) );
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ir ir_( .*, .db(db0[7:0]) );
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pin_control pin_control_( .* );
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pla_decode pla_decode_( .* );
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resets resets_( .* );
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sequencer sequencer_( .* );
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// ALU and ALU control, including the flags
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alu_control alu_control_( .*, .db(db1[7:0]), .op543({pla[104],pla[103],pla[102]}) );
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alu_select alu_select_( .* );
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alu_flags alu_flags_( .*, .db(db1[7:0]) );
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alu alu_( .*, .db(db2[7:0]), .bsel(db0[5:3]) );
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// Register file and register control
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reg_file reg_file_( .*, .db_hi_ds(db2[7:0]), .db_lo_ds(db1[7:0]), .db_hi_as(db_hi_as[7:0]), .db_lo_as(db_lo_as[7:0]) );
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reg_control reg_control_( .* );
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// Address latch and the incrementer
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address_latch address_latch_( .*, .abus({db_hi_as[7:0], db_lo_as[7:0]}) );
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// Misc bus
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bus_control bus_control_( .*, .db(db0[7:0]) );
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bus_switch bus_switch_( .* );
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// Timing control of the external pins
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memory_ifc memory_ifc_( .* );
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*/
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@@ -0,0 +1,566 @@
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// Automatically generated by gencoremodules.py
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clk_delay clk_delay_(
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.clk (clk),
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.in_intr (in_intr),
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.nreset (nreset),
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.T1 (T1),
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.latch_wait (latch_wait),
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.mwait (mwait),
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.M1 (M1),
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.busrq (busrq),
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.setM1 (setM1),
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.hold_clk_iorq (hold_clk_iorq),
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.hold_clk_wait (hold_clk_wait),
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.iorq_Tw (iorq_Tw),
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.busack (busack),
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.pin_control_oe (pin_control_oe),
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.hold_clk_busrq (hold_clk_busrq),
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.nhold_clk_wait (nhold_clk_wait)
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);
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decode_state decode_state_(
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.ctl_state_iy_set (ctl_state_iy_set),
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.ctl_state_ixiy_clr (ctl_state_ixiy_clr),
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.ctl_state_ixiy_we (ctl_state_ixiy_we),
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.ctl_state_halt_set (ctl_state_halt_set),
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.ctl_state_tbl_ed_set (ctl_state_tbl_ed_set),
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.ctl_state_tbl_cb_set (ctl_state_tbl_cb_set),
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.ctl_state_alu (ctl_state_alu),
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.clk (clk),
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.address_is_1 (address_is_1),
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.ctl_repeat_we (ctl_repeat_we),
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.in_intr (in_intr),
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.in_nmi (in_nmi),
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.nreset (nreset),
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.ctl_state_tbl_we (ctl_state_tbl_we),
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.nhold_clk_wait (nhold_clk_wait),
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.in_halt (in_halt),
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.table_cb (table_cb),
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.table_ed (table_ed),
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.table_xx (table_xx),
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.use_ix (use_ix),
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.use_ixiy (use_ixiy),
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.in_alu (in_alu),
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.repeat_en (repeat_en)
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);
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execute execute_(
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.ctl_state_iy_set (ctl_state_iy_set),
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.ctl_state_ixiy_clr (ctl_state_ixiy_clr),
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.ctl_state_ixiy_we (ctl_state_ixiy_we),
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.ctl_state_halt_set (ctl_state_halt_set),
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.ctl_state_tbl_ed_set (ctl_state_tbl_ed_set),
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.ctl_state_tbl_cb_set (ctl_state_tbl_cb_set),
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.ctl_state_alu (ctl_state_alu),
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.ctl_repeat_we (ctl_repeat_we),
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.ctl_state_tbl_we (ctl_state_tbl_we),
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.ctl_iff1_iff2 (ctl_iff1_iff2),
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.ctl_iffx_we (ctl_iffx_we),
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.ctl_iffx_bit (ctl_iffx_bit),
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.ctl_im_we (ctl_im_we),
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.ctl_no_ints (ctl_no_ints),
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.ctl_ir_we (ctl_ir_we),
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.ctl_mRead (ctl_mRead),
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.ctl_mWrite (ctl_mWrite),
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.ctl_iorw (ctl_iorw),
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.ctl_shift_en (ctl_shift_en),
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.ctl_daa_oe (ctl_daa_oe),
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.ctl_alu_op_low (ctl_alu_op_low),
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.ctl_cond_short (ctl_cond_short),
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.ctl_alu_core_hf (ctl_alu_core_hf),
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.ctl_eval_cond (ctl_eval_cond),
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.ctl_66_oe (ctl_66_oe),
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.ctl_pf_sel (ctl_pf_sel),
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.ctl_alu_oe (ctl_alu_oe),
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.ctl_alu_shift_oe (ctl_alu_shift_oe),
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.ctl_alu_op2_oe (ctl_alu_op2_oe),
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.ctl_alu_res_oe (ctl_alu_res_oe),
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.ctl_alu_op1_oe (ctl_alu_op1_oe),
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.ctl_alu_bs_oe (ctl_alu_bs_oe),
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.ctl_alu_op1_sel_bus (ctl_alu_op1_sel_bus),
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.ctl_alu_op1_sel_low (ctl_alu_op1_sel_low),
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.ctl_alu_op1_sel_zero (ctl_alu_op1_sel_zero),
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.ctl_alu_op2_sel_zero (ctl_alu_op2_sel_zero),
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.ctl_alu_op2_sel_bus (ctl_alu_op2_sel_bus),
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.ctl_alu_op2_sel_lq (ctl_alu_op2_sel_lq),
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.ctl_alu_sel_op2_neg (ctl_alu_sel_op2_neg),
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.ctl_alu_sel_op2_high (ctl_alu_sel_op2_high),
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.ctl_alu_core_R (ctl_alu_core_R),
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.ctl_alu_core_V (ctl_alu_core_V),
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.ctl_alu_core_S (ctl_alu_core_S),
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.ctl_flags_oe (ctl_flags_oe),
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.ctl_flags_bus (ctl_flags_bus),
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.ctl_flags_alu (ctl_flags_alu),
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.ctl_flags_nf_set (ctl_flags_nf_set),
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.ctl_flags_cf_set (ctl_flags_cf_set),
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.ctl_flags_cf_cpl (ctl_flags_cf_cpl),
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.ctl_flags_cf_we (ctl_flags_cf_we),
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.ctl_flags_sz_we (ctl_flags_sz_we),
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.ctl_flags_xy_we (ctl_flags_xy_we),
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.ctl_flags_hf_we (ctl_flags_hf_we),
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.ctl_flags_pf_we (ctl_flags_pf_we),
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.ctl_flags_nf_we (ctl_flags_nf_we),
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.ctl_flags_cf2_we (ctl_flags_cf2_we),
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.ctl_flags_hf_cpl (ctl_flags_hf_cpl),
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.ctl_flags_use_cf2 (ctl_flags_use_cf2),
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.ctl_flags_hf2_we (ctl_flags_hf2_we),
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.ctl_flags_nf_clr (ctl_flags_nf_clr),
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.ctl_alu_zero_16bit (ctl_alu_zero_16bit),
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.ctl_flags_cf2_sel_shift (ctl_flags_cf2_sel_shift),
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.ctl_flags_cf2_sel_daa (ctl_flags_cf2_sel_daa),
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.ctl_sw_4u (ctl_sw_4u),
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.ctl_reg_in_hi (ctl_reg_in_hi),
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.ctl_reg_in_lo (ctl_reg_in_lo),
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.ctl_reg_out_lo (ctl_reg_out_lo),
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.ctl_reg_out_hi (ctl_reg_out_hi),
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.ctl_reg_exx (ctl_reg_exx),
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.ctl_reg_ex_af (ctl_reg_ex_af),
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.ctl_reg_ex_de_hl (ctl_reg_ex_de_hl),
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.ctl_reg_use_sp (ctl_reg_use_sp),
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.ctl_reg_sel_pc (ctl_reg_sel_pc),
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.ctl_reg_sel_ir (ctl_reg_sel_ir),
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.ctl_reg_sel_wz (ctl_reg_sel_wz),
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.ctl_reg_gp_we (ctl_reg_gp_we),
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.ctl_reg_not_pc (ctl_reg_not_pc),
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.ctl_reg_sys_we_lo (ctl_reg_sys_we_lo),
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.ctl_reg_sys_we_hi (ctl_reg_sys_we_hi),
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.ctl_reg_sys_we (ctl_reg_sys_we),
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.ctl_sw_4d (ctl_sw_4d),
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.ctl_reg_gp_hilo (ctl_reg_gp_hilo),
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.ctl_reg_gp_sel (ctl_reg_gp_sel),
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.ctl_reg_sys_hilo (ctl_reg_sys_hilo),
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.ctl_inc_cy (ctl_inc_cy),
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.ctl_inc_dec (ctl_inc_dec),
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.ctl_al_we (ctl_al_we),
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.ctl_inc_limit6 (ctl_inc_limit6),
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.ctl_bus_inc_oe (ctl_bus_inc_oe),
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.ctl_apin_mux (ctl_apin_mux),
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.ctl_apin_mux2 (ctl_apin_mux2),
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.ctl_bus_ff_oe (ctl_bus_ff_oe),
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.ctl_bus_zero_oe (ctl_bus_zero_oe),
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.ctl_sw_1u (ctl_sw_1u),
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.ctl_sw_1d (ctl_sw_1d),
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.ctl_sw_2u (ctl_sw_2u),
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.ctl_sw_2d (ctl_sw_2d),
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.ctl_sw_mask543_en (ctl_sw_mask543_en),
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.ctl_bus_db_we (ctl_bus_db_we),
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.ctl_bus_db_oe (ctl_bus_db_oe),
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.nextM (nextM),
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.setM1 (setM1),
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.fFetch (fFetch),
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.fMRead (fMRead),
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.fMWrite (fMWrite),
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.fIORead (fIORead),
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.fIOWrite (fIOWrite),
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.pla (pla),
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.in_intr (in_intr),
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.in_nmi (in_nmi),
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.in_halt (in_halt),
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.im1 (im1),
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.im2 (im2),
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.use_ixiy (use_ixiy),
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.flags_cond_true (flags_cond_true),
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.repeat_en (repeat_en),
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.flags_zf (flags_zf),
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.flags_nf (flags_nf),
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.flags_sf (flags_sf),
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.flags_cf (flags_cf),
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.M1 (M1),
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.M2 (M2),
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.M3 (M3),
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.M4 (M4),
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.M5 (M5),
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.T1 (T1),
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.T2 (T2),
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.T3 (T3),
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.T4 (T4),
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.T5 (T5),
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.T6 (T6)
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);
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interrupts interrupts_(
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.ctl_iff1_iff2 (ctl_iff1_iff2),
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.nmi (nmi),
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.setM1 (setM1),
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.intr (intr),
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.ctl_iffx_we (ctl_iffx_we),
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.ctl_iffx_bit (ctl_iffx_bit),
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.ctl_im_we (ctl_im_we),
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.clk (clk),
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.ctl_no_ints (ctl_no_ints),
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.nreset (nreset),
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.db (db0[4:3]),
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.iff2 (iff2),
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.im1 (im1),
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.im2 (im2),
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.in_nmi (in_nmi),
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.in_intr (in_intr)
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);
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ir ir_(
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.ctl_ir_we (ctl_ir_we),
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.clk (clk),
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.nreset (nreset),
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.nhold_clk_wait (nhold_clk_wait),
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.db (db0[7:0]),
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.opcode (opcode)
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);
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pin_control pin_control_(
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.fFetch (fFetch),
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.fMRead (fMRead),
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.fMWrite (fMWrite),
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.fIORead (fIORead),
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.fIOWrite (fIOWrite),
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.T1 (T1),
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.T2 (T2),
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.T3 (T3),
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.T4 (T4),
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.bus_ab_pin_we (bus_ab_pin_we),
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.bus_db_pin_oe (bus_db_pin_oe),
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.bus_db_pin_re (bus_db_pin_re)
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);
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pla_decode pla_decode_(
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.prefix (prefix),
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.opcode (opcode),
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.pla (pla)
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);
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resets resets_(
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.reset_in (reset_in),
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.clk (clk),
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.M1 (M1),
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.T2 (T2),
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.fpga_reset (fpga_reset),
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.nhold_clk_wait (nhold_clk_wait),
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.clrpc (clrpc),
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.nreset (nreset)
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);
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memory_ifc memory_ifc_(
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.clk (clk),
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.nM1_int (nM1_int),
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.ctl_mRead (ctl_mRead),
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.ctl_mWrite (ctl_mWrite),
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.in_intr (in_intr),
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.nreset (nreset),
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.fIORead (fIORead),
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.fIOWrite (fIOWrite),
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.setM1 (setM1),
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.ctl_iorw (ctl_iorw),
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.timings_en (timings_en),
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.iorq_Tw (iorq_Tw),
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.nhold_clk_wait (nhold_clk_wait),
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.nM1_out (nM1_out),
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.nRFSH_out (nRFSH_out),
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.nMREQ_out (nMREQ_out),
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.nRD_out (nRD_out),
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.nWR_out (nWR_out),
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.nIORQ_out (nIORQ_out),
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.latch_wait (latch_wait),
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.wait_m1 (wait_m1)
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);
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sequencer sequencer_(
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.clk (clk),
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.nextM (nextM),
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.setM1 (setM1),
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.nreset (nreset),
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.hold_clk_iorq (hold_clk_iorq),
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.hold_clk_wait (hold_clk_wait),
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.hold_clk_busrq (hold_clk_busrq),
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.M1 (M1),
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.M2 (M2),
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.M3 (M3),
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.M4 (M4),
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.M5 (M5),
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.T1 (T1),
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.T2 (T2),
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.T3 (T3),
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.T4 (T4),
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.T5 (T5),
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.T6 (T6),
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.timings_en (timings_en)
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);
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alu_control alu_control_(
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.alu_shift_db0 (alu_shift_db0),
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.alu_shift_db7 (alu_shift_db7),
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.ctl_shift_en (ctl_shift_en),
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.alu_low_gt_9 (alu_low_gt_9),
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.alu_high_gt_9 (alu_high_gt_9),
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.alu_high_eq_9 (alu_high_eq_9),
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.ctl_daa_oe (ctl_daa_oe),
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.ctl_alu_op_low (ctl_alu_op_low),
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.alu_parity_out (alu_parity_out),
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.flags_cf (flags_cf),
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.flags_zf (flags_zf),
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.flags_pf (flags_pf),
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.flags_sf (flags_sf),
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.ctl_cond_short (ctl_cond_short),
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.alu_vf_out (alu_vf_out),
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.iff2 (iff2),
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.ctl_alu_core_hf (ctl_alu_core_hf),
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.ctl_eval_cond (ctl_eval_cond),
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.repeat_en (repeat_en),
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.flags_cf_latch (flags_cf_latch),
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.flags_hf2 (flags_hf2),
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.flags_hf (flags_hf),
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.ctl_66_oe (ctl_66_oe),
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.clk (clk),
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.ctl_pf_sel (ctl_pf_sel),
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.op543 ({pla[104],pla[103],pla[102]}),
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.alu_shift_in (alu_shift_in),
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.alu_shift_right (alu_shift_right),
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.alu_shift_left (alu_shift_left),
|
||||
.shift_cf_out (shift_cf_out),
|
||||
.alu_parity_in (alu_parity_in),
|
||||
.flags_cond_true (flags_cond_true),
|
||||
.daa_cf_out (daa_cf_out),
|
||||
.pf_sel (pf_sel),
|
||||
.alu_op_low (alu_op_low),
|
||||
.alu_core_cf_in (alu_core_cf_in),
|
||||
.db (db1[7:0])
|
||||
);
|
||||
|
||||
alu_select alu_select_(
|
||||
.ctl_alu_oe (ctl_alu_oe),
|
||||
.ctl_alu_shift_oe (ctl_alu_shift_oe),
|
||||
.ctl_alu_op2_oe (ctl_alu_op2_oe),
|
||||
.ctl_alu_res_oe (ctl_alu_res_oe),
|
||||
.ctl_alu_op1_oe (ctl_alu_op1_oe),
|
||||
.ctl_alu_bs_oe (ctl_alu_bs_oe),
|
||||
.ctl_alu_op1_sel_bus (ctl_alu_op1_sel_bus),
|
||||
.ctl_alu_op1_sel_low (ctl_alu_op1_sel_low),
|
||||
.ctl_alu_op1_sel_zero (ctl_alu_op1_sel_zero),
|
||||
.ctl_alu_op2_sel_zero (ctl_alu_op2_sel_zero),
|
||||
.ctl_alu_op2_sel_bus (ctl_alu_op2_sel_bus),
|
||||
.ctl_alu_op2_sel_lq (ctl_alu_op2_sel_lq),
|
||||
.ctl_alu_sel_op2_neg (ctl_alu_sel_op2_neg),
|
||||
.ctl_alu_sel_op2_high (ctl_alu_sel_op2_high),
|
||||
.ctl_alu_core_R (ctl_alu_core_R),
|
||||
.ctl_alu_core_V (ctl_alu_core_V),
|
||||
.ctl_alu_core_S (ctl_alu_core_S),
|
||||
.alu_oe (alu_oe),
|
||||
.alu_shift_oe (alu_shift_oe),
|
||||
.alu_op2_oe (alu_op2_oe),
|
||||
.alu_res_oe (alu_res_oe),
|
||||
.alu_op1_oe (alu_op1_oe),
|
||||
.alu_bs_oe (alu_bs_oe),
|
||||
.alu_op1_sel_bus (alu_op1_sel_bus),
|
||||
.alu_op1_sel_low (alu_op1_sel_low),
|
||||
.alu_op1_sel_zero (alu_op1_sel_zero),
|
||||
.alu_op2_sel_zero (alu_op2_sel_zero),
|
||||
.alu_op2_sel_bus (alu_op2_sel_bus),
|
||||
.alu_op2_sel_lq (alu_op2_sel_lq),
|
||||
.alu_sel_op2_neg (alu_sel_op2_neg),
|
||||
.alu_sel_op2_high (alu_sel_op2_high),
|
||||
.alu_core_R (alu_core_R),
|
||||
.alu_core_V (alu_core_V),
|
||||
.alu_core_S (alu_core_S)
|
||||
);
|
||||
|
||||
alu_flags alu_flags_(
|
||||
.ctl_flags_oe (ctl_flags_oe),
|
||||
.ctl_flags_bus (ctl_flags_bus),
|
||||
.ctl_flags_alu (ctl_flags_alu),
|
||||
.alu_sf_out (alu_sf_out),
|
||||
.alu_yf_out (alu_yf_out),
|
||||
.alu_xf_out (alu_xf_out),
|
||||
.ctl_flags_nf_set (ctl_flags_nf_set),
|
||||
.alu_zero (alu_zero),
|
||||
.shift_cf_out (shift_cf_out),
|
||||
.alu_core_cf_out (alu_core_cf_out),
|
||||
.daa_cf_out (daa_cf_out),
|
||||
.ctl_flags_cf_set (ctl_flags_cf_set),
|
||||
.ctl_flags_cf_cpl (ctl_flags_cf_cpl),
|
||||
.pf_sel (pf_sel),
|
||||
.ctl_flags_cf_we (ctl_flags_cf_we),
|
||||
.ctl_flags_sz_we (ctl_flags_sz_we),
|
||||
.ctl_flags_xy_we (ctl_flags_xy_we),
|
||||
.ctl_flags_hf_we (ctl_flags_hf_we),
|
||||
.ctl_flags_pf_we (ctl_flags_pf_we),
|
||||
.ctl_flags_nf_we (ctl_flags_nf_we),
|
||||
.ctl_flags_cf2_we (ctl_flags_cf2_we),
|
||||
.ctl_flags_hf_cpl (ctl_flags_hf_cpl),
|
||||
.ctl_flags_use_cf2 (ctl_flags_use_cf2),
|
||||
.ctl_flags_hf2_we (ctl_flags_hf2_we),
|
||||
.ctl_flags_nf_clr (ctl_flags_nf_clr),
|
||||
.ctl_alu_zero_16bit (ctl_alu_zero_16bit),
|
||||
.clk (clk),
|
||||
.ctl_flags_cf2_sel_shift (ctl_flags_cf2_sel_shift),
|
||||
.ctl_flags_cf2_sel_daa (ctl_flags_cf2_sel_daa),
|
||||
.nhold_clk_wait (nhold_clk_wait),
|
||||
.flags_sf (flags_sf),
|
||||
.flags_zf (flags_zf),
|
||||
.flags_hf (flags_hf),
|
||||
.flags_pf (flags_pf),
|
||||
.flags_cf (flags_cf),
|
||||
.flags_nf (flags_nf),
|
||||
.flags_cf_latch (flags_cf_latch),
|
||||
.flags_hf2 (flags_hf2),
|
||||
.db (db1[7:0])
|
||||
);
|
||||
|
||||
alu alu_(
|
||||
.alu_core_R (alu_core_R),
|
||||
.alu_core_V (alu_core_V),
|
||||
.alu_core_S (alu_core_S),
|
||||
.alu_bs_oe (alu_bs_oe),
|
||||
.alu_parity_in (alu_parity_in),
|
||||
.alu_oe (alu_oe),
|
||||
.alu_shift_oe (alu_shift_oe),
|
||||
.alu_core_cf_in (alu_core_cf_in),
|
||||
.alu_op2_oe (alu_op2_oe),
|
||||
.alu_op1_oe (alu_op1_oe),
|
||||
.alu_res_oe (alu_res_oe),
|
||||
.alu_op1_sel_low (alu_op1_sel_low),
|
||||
.alu_op1_sel_zero (alu_op1_sel_zero),
|
||||
.alu_op1_sel_bus (alu_op1_sel_bus),
|
||||
.alu_op2_sel_zero (alu_op2_sel_zero),
|
||||
.alu_op2_sel_bus (alu_op2_sel_bus),
|
||||
.alu_op2_sel_lq (alu_op2_sel_lq),
|
||||
.alu_op_low (alu_op_low),
|
||||
.alu_shift_in (alu_shift_in),
|
||||
.alu_sel_op2_neg (alu_sel_op2_neg),
|
||||
.alu_sel_op2_high (alu_sel_op2_high),
|
||||
.alu_shift_left (alu_shift_left),
|
||||
.alu_shift_right (alu_shift_right),
|
||||
.clk (clk),
|
||||
.bsel (db0[5:3]),
|
||||
.alu_zero (alu_zero),
|
||||
.alu_parity_out (alu_parity_out),
|
||||
.alu_high_eq_9 (alu_high_eq_9),
|
||||
.alu_high_gt_9 (alu_high_gt_9),
|
||||
.alu_low_gt_9 (alu_low_gt_9),
|
||||
.alu_shift_db0 (alu_shift_db0),
|
||||
.alu_shift_db7 (alu_shift_db7),
|
||||
.alu_core_cf_out (alu_core_cf_out),
|
||||
.alu_sf_out (alu_sf_out),
|
||||
.alu_yf_out (alu_yf_out),
|
||||
.alu_xf_out (alu_xf_out),
|
||||
.alu_vf_out (alu_vf_out),
|
||||
.db (db2[7:0]),
|
||||
.test_db_high (test_db_high),
|
||||
.test_db_low (test_db_low)
|
||||
);
|
||||
|
||||
reg_file reg_file_(
|
||||
.reg_sel_sys_lo (reg_sel_sys_lo),
|
||||
.reg_sel_gp_lo (reg_sel_gp_lo),
|
||||
.reg_sel_sys_hi (reg_sel_sys_hi),
|
||||
.reg_sel_gp_hi (reg_sel_gp_hi),
|
||||
.reg_sel_ir (reg_sel_ir),
|
||||
.reg_sel_pc (reg_sel_pc),
|
||||
.ctl_sw_4u (ctl_sw_4u),
|
||||
.reg_sel_wz (reg_sel_wz),
|
||||
.reg_sel_sp (reg_sel_sp),
|
||||
.reg_sel_iy (reg_sel_iy),
|
||||
.reg_sel_ix (reg_sel_ix),
|
||||
.reg_sel_hl2 (reg_sel_hl2),
|
||||
.reg_sel_hl (reg_sel_hl),
|
||||
.reg_sel_de2 (reg_sel_de2),
|
||||
.reg_sel_de (reg_sel_de),
|
||||
.reg_sel_bc2 (reg_sel_bc2),
|
||||
.reg_sel_bc (reg_sel_bc),
|
||||
.reg_sel_af2 (reg_sel_af2),
|
||||
.reg_sel_af (reg_sel_af),
|
||||
.reg_gp_we (reg_gp_we),
|
||||
.reg_sys_we_lo (reg_sys_we_lo),
|
||||
.reg_sys_we_hi (reg_sys_we_hi),
|
||||
.ctl_reg_in_hi (ctl_reg_in_hi),
|
||||
.ctl_reg_in_lo (ctl_reg_in_lo),
|
||||
.ctl_reg_out_lo (ctl_reg_out_lo),
|
||||
.ctl_reg_out_hi (ctl_reg_out_hi),
|
||||
.clk (clk),
|
||||
.reg_sw_4d_lo (reg_sw_4d_lo),
|
||||
.reg_sw_4d_hi (reg_sw_4d_hi),
|
||||
.db_hi_as (db_hi_as[7:0]),
|
||||
.db_hi_ds (db2[7:0]),
|
||||
.db_lo_as (db_lo_as[7:0]),
|
||||
.db_lo_ds (db1[7:0])
|
||||
);
|
||||
|
||||
reg_control reg_control_(
|
||||
.ctl_reg_exx (ctl_reg_exx),
|
||||
.ctl_reg_ex_af (ctl_reg_ex_af),
|
||||
.ctl_reg_ex_de_hl (ctl_reg_ex_de_hl),
|
||||
.ctl_reg_use_sp (ctl_reg_use_sp),
|
||||
.nreset (nreset),
|
||||
.ctl_reg_sel_pc (ctl_reg_sel_pc),
|
||||
.ctl_reg_sel_ir (ctl_reg_sel_ir),
|
||||
.ctl_reg_sel_wz (ctl_reg_sel_wz),
|
||||
.ctl_reg_gp_we (ctl_reg_gp_we),
|
||||
.ctl_reg_not_pc (ctl_reg_not_pc),
|
||||
.use_ixiy (use_ixiy),
|
||||
.use_ix (use_ix),
|
||||
.ctl_reg_sys_we_lo (ctl_reg_sys_we_lo),
|
||||
.ctl_reg_sys_we_hi (ctl_reg_sys_we_hi),
|
||||
.ctl_reg_sys_we (ctl_reg_sys_we),
|
||||
.clk (clk),
|
||||
.ctl_sw_4d (ctl_sw_4d),
|
||||
.nhold_clk_wait (nhold_clk_wait),
|
||||
.ctl_reg_gp_hilo (ctl_reg_gp_hilo),
|
||||
.ctl_reg_gp_sel (ctl_reg_gp_sel),
|
||||
.ctl_reg_sys_hilo (ctl_reg_sys_hilo),
|
||||
.reg_sel_bc (reg_sel_bc),
|
||||
.reg_sel_bc2 (reg_sel_bc2),
|
||||
.reg_sel_ix (reg_sel_ix),
|
||||
.reg_sel_iy (reg_sel_iy),
|
||||
.reg_sel_de (reg_sel_de),
|
||||
.reg_sel_hl (reg_sel_hl),
|
||||
.reg_sel_de2 (reg_sel_de2),
|
||||
.reg_sel_hl2 (reg_sel_hl2),
|
||||
.reg_sel_af (reg_sel_af),
|
||||
.reg_sel_af2 (reg_sel_af2),
|
||||
.reg_sel_wz (reg_sel_wz),
|
||||
.reg_sel_pc (reg_sel_pc),
|
||||
.reg_sel_ir (reg_sel_ir),
|
||||
.reg_sel_sp (reg_sel_sp),
|
||||
.reg_sel_gp_hi (reg_sel_gp_hi),
|
||||
.reg_sel_gp_lo (reg_sel_gp_lo),
|
||||
.reg_sel_sys_lo (reg_sel_sys_lo),
|
||||
.reg_sel_sys_hi (reg_sel_sys_hi),
|
||||
.reg_gp_we (reg_gp_we),
|
||||
.reg_sys_we_lo (reg_sys_we_lo),
|
||||
.reg_sys_we_hi (reg_sys_we_hi),
|
||||
.reg_sw_4d_lo (reg_sw_4d_lo),
|
||||
.reg_sw_4d_hi (reg_sw_4d_hi)
|
||||
);
|
||||
|
||||
address_latch address_latch_(
|
||||
.ctl_inc_cy (ctl_inc_cy),
|
||||
.ctl_inc_dec (ctl_inc_dec),
|
||||
.ctl_al_we (ctl_al_we),
|
||||
.ctl_inc_limit6 (ctl_inc_limit6),
|
||||
.ctl_bus_inc_oe (ctl_bus_inc_oe),
|
||||
.clk (clk),
|
||||
.ctl_apin_mux (ctl_apin_mux),
|
||||
.ctl_apin_mux2 (ctl_apin_mux2),
|
||||
.clrpc (clrpc),
|
||||
.nreset (nreset),
|
||||
.address_is_1 (address_is_1),
|
||||
.abus ({db_hi_as[7:0], db_lo_as[7:0]}),
|
||||
.address (address)
|
||||
);
|
||||
|
||||
bus_control bus_control_(
|
||||
.ctl_bus_ff_oe (ctl_bus_ff_oe),
|
||||
.ctl_bus_zero_oe (ctl_bus_zero_oe),
|
||||
.db (db0[7:0])
|
||||
);
|
||||
|
||||
bus_switch bus_switch_(
|
||||
.ctl_sw_1u (ctl_sw_1u),
|
||||
.ctl_sw_1d (ctl_sw_1d),
|
||||
.ctl_sw_2u (ctl_sw_2u),
|
||||
.ctl_sw_2d (ctl_sw_2d),
|
||||
.ctl_sw_mask543_en (ctl_sw_mask543_en),
|
||||
.bus_sw_1u (bus_sw_1u),
|
||||
.bus_sw_1d (bus_sw_1d),
|
||||
.bus_sw_2u (bus_sw_2u),
|
||||
.bus_sw_2d (bus_sw_2d),
|
||||
.bus_sw_mask543_en (bus_sw_mask543_en)
|
||||
);
|
||||
@@ -0,0 +1,76 @@
|
||||
These files are part of the Fuse emulator Z80 test vectors:
|
||||
http://fuse-emulator.sourceforge.net/
|
||||
|
||||
File formats
|
||||
============
|
||||
|
||||
tests.in
|
||||
--------
|
||||
|
||||
Each test has the format:
|
||||
|
||||
<arbitrary test description>
|
||||
AF BC DE HL AF' BC' DE' HL' IX IY SP PC
|
||||
I R IFF1 IFF2 IM <halted> <tstates>
|
||||
|
||||
<halted> specifies whether the Z80 is halted.
|
||||
<tstates> specifies the number of tstates to run the test for, in
|
||||
decimal; the number actually executed may be higher, as the final
|
||||
instruction is allowed to complete.
|
||||
|
||||
Then followed by lines specifying the initial memory setup. Each has
|
||||
the format:
|
||||
|
||||
<start address> <byte1> <byte2> ... -1
|
||||
|
||||
eg
|
||||
|
||||
1234 56 78 9a -1
|
||||
|
||||
says to put 0x56 at 0x1234, 0x78 at 0x1235 and 0x9a at 0x1236.
|
||||
|
||||
Finally, -1 to end the test. Blank lines may follow before the next test.
|
||||
|
||||
tests.expected
|
||||
--------------
|
||||
|
||||
Each test output starts with the test description, followed by a list
|
||||
of 'events': each has the format
|
||||
|
||||
<time> <type> <address> <data>
|
||||
|
||||
<time> is simply the time at which the event occurs.
|
||||
<type> is one of MR (memory read), MW (memory write), MC (memory
|
||||
contend), PR (port read), PW (port write) or PC (port contend).
|
||||
<address> is the address (or IO port) affected.
|
||||
<data> is the byte written or read. Missing for contentions.
|
||||
|
||||
After that, lines specifying AF, BC etc as for .in files. <tstates>
|
||||
now specifies the final time.
|
||||
|
||||
After that, lines specifying which bits of memory have changed since
|
||||
the initial setup. Same format as for .in files.
|
||||
|
||||
Why some specific tests are here
|
||||
================================
|
||||
|
||||
37_{1,2,3}: check the behaviour of SCF with respect to bits 3 and 5
|
||||
(bug fixed on 20040225).
|
||||
|
||||
cb{4,5,6,7}{7,f}_1: designed to check that bits 3 and 5 are copied to
|
||||
F only for BIT 3,<arg> and BIT 5,<arg> respectively
|
||||
(bug fixed on 20040225).
|
||||
|
||||
However, later research has revealed the bits 3
|
||||
and 5 are copied on all BIT instructions, so these
|
||||
tests are now essentially redundant.
|
||||
|
||||
d{3,b}_{1,2,3}: check for correct port contention on IO in the four
|
||||
relevant states (port high byte in 0x40 to 0x7f or not,
|
||||
port low bit set or reset).
|
||||
|
||||
dd00.in, ddfd00.in: test timings of "extended NOP" opcodes DD 00 and
|
||||
DD FD 00; the extra 00 at the end is to check the
|
||||
next opcode executes at the right time (bug fixed
|
||||
on 20060722).
|
||||
|
||||
@@ -0,0 +1,263 @@
|
||||
00 NOP
|
||||
0 MC 0000
|
||||
4 MR 0000 00
|
||||
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001
|
||||
00 01 0 0 0 0 4
|
||||
|
||||
ed67 RRD
|
||||
0 MC 0000
|
||||
4 MR 0000 ed
|
||||
4 MC 0001
|
||||
8 MR 0001 67
|
||||
8 MC b9de
|
||||
11 MR b9de 93
|
||||
11 MC b9de
|
||||
12 MC b9de
|
||||
13 MC b9de
|
||||
14 MC b9de
|
||||
15 MC b9de
|
||||
18 MW b9de 69
|
||||
3324 b16a a4db b9de 0000 0000 0000 0000 0000 0000 0000 0002
|
||||
00 02 0 0 0 0 18
|
||||
b9de 69 -1
|
||||
|
||||
ed6f RLD
|
||||
0 MC 0000
|
||||
4 MR 0000 ed
|
||||
4 MC 0001
|
||||
8 MR 0001 6f
|
||||
8 MC 403c
|
||||
11 MR 403c c4
|
||||
11 MC 403c
|
||||
12 MC 403c
|
||||
13 MC 403c
|
||||
14 MC 403c
|
||||
15 MC 403c
|
||||
18 MW 403c 45
|
||||
6c2d 7a7a ecf0 403c 0000 0000 0000 0000 0000 0000 0000 0002
|
||||
00 02 0 0 0 0 18
|
||||
403c 45 -1
|
||||
|
||||
81 ADD A,C
|
||||
0 MC 0000
|
||||
4 MR 0000 81
|
||||
3031 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001
|
||||
00 01 0 0 0 0 4
|
||||
|
||||
cb41 BIT 0,C
|
||||
0 MC 0000
|
||||
4 MR 0000 cb
|
||||
4 MC 0001
|
||||
8 MR 0001 41
|
||||
9e10 1b43 954e 7be9 0000 0000 0000 0000 0000 0000 0000 0002
|
||||
00 02 0 0 0 0 8
|
||||
|
||||
cb93 RES 2,E
|
||||
0 MC 0000
|
||||
4 MR 0000 cb
|
||||
4 MC 0001
|
||||
8 MR 0001 93
|
||||
c200 4e05 b3f8 2234 0000 0000 0000 0000 0000 0000 0000 0002
|
||||
00 02 0 0 0 0 8
|
||||
|
||||
cbe5 SET 4,L
|
||||
0 MC 0000
|
||||
4 MR 0000 cb
|
||||
4 MC 0001
|
||||
8 MR 0001 e5
|
||||
ca00 df0d d588 b49f 0000 0000 0000 0000 0000 0000 0000 0002
|
||||
00 02 0 0 0 0 8
|
||||
|
||||
8c ADC A,H
|
||||
0 MC 0000
|
||||
4 MR 0000 8c
|
||||
d191 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001
|
||||
00 01 0 0 0 0 4
|
||||
|
||||
92 SUB D
|
||||
0 MC 0000
|
||||
4 MR 0000 92
|
||||
d582 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001
|
||||
00 01 0 0 0 0 4
|
||||
|
||||
9d SBC A,L
|
||||
0 MC 0000
|
||||
4 MR 0000 9d
|
||||
4f1a 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001
|
||||
00 01 0 0 0 0 4
|
||||
|
||||
a3 AND E
|
||||
0 MC 0000
|
||||
4 MR 0000 a3
|
||||
0514 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001
|
||||
00 01 0 0 0 0 4
|
||||
|
||||
ae XOR (HL)
|
||||
0 MC 0000
|
||||
4 MR 0000 ae
|
||||
4 MC dca6
|
||||
7 MR dca6 49
|
||||
bca8 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001
|
||||
00 01 0 0 0 0 7
|
||||
|
||||
b4 OR H
|
||||
0 MC 0000
|
||||
4 MR 0000 b4
|
||||
fda8 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001
|
||||
00 01 0 0 0 0 4
|
||||
|
||||
bf CP A
|
||||
0 MC 0000
|
||||
4 MR 0000 bf
|
||||
f562 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001
|
||||
00 01 0 0 0 0 4
|
||||
|
||||
43 LD B,E
|
||||
0 MC 0000
|
||||
4 MR 0000 43
|
||||
0200 d898 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001
|
||||
00 01 0 0 0 0 4
|
||||
|
||||
6e LD L,(HL)
|
||||
0 MC 0000
|
||||
4 MR 0000 6e
|
||||
4 MC a169
|
||||
7 MR a169 50
|
||||
0200 cf98 90d8 a150 0000 0000 0000 0000 0000 0000 0000 0001
|
||||
00 01 0 0 0 0 7
|
||||
|
||||
e3 EX (SP),HL
|
||||
0 MC 0000
|
||||
4 MR 0000 e3
|
||||
4 MC 0373
|
||||
7 MR 0373 8e
|
||||
7 MC 0374
|
||||
10 MR 0374 e1
|
||||
10 MC 0374
|
||||
11 MC 0374
|
||||
14 MW 0374 4d
|
||||
14 MC 0373
|
||||
17 MW 0373 22
|
||||
17 MC 0373
|
||||
18 MC 0373
|
||||
0000 0000 0000 e18e 0000 0000 0000 0000 0000 0000 0373 0001
|
||||
00 01 0 0 0 0 19
|
||||
0373 22 4d -1
|
||||
|
||||
03 INC BC
|
||||
0 MC 0000
|
||||
4 MR 0000 03
|
||||
4 MC 0001
|
||||
5 MC 0001
|
||||
0000 789b 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001
|
||||
00 01 0 0 0 0 6
|
||||
|
||||
3b DEC SP
|
||||
0 MC 0000
|
||||
4 MR 0000 3b
|
||||
4 MC 0001
|
||||
5 MC 0001
|
||||
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 9d35 0001
|
||||
00 01 0 0 0 0 6
|
||||
|
||||
07 RLCA
|
||||
0 MC 0000
|
||||
4 MR 0000 07
|
||||
1101 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001
|
||||
00 01 0 0 0 0 4
|
||||
|
||||
1f RRA
|
||||
0 MC 0000
|
||||
4 MR 0000 1f
|
||||
00c5 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001
|
||||
00 01 0 0 0 0 4
|
||||
|
||||
cb09 RRC C
|
||||
0 MC 0000
|
||||
4 MR 0000 cb
|
||||
4 MC 0001
|
||||
8 MR 0001 09
|
||||
182c 122e dd97 59c6 0000 0000 0000 0000 0000 0000 0000 0002
|
||||
00 02 0 0 0 0 8
|
||||
|
||||
cb11 RL C
|
||||
0 MC 0000
|
||||
4 MR 0000 cb
|
||||
4 MC 0001
|
||||
8 MR 0001 11
|
||||
65ac e2b8 4b8a ed42 0000 0000 0000 0000 0000 0000 0000 0002
|
||||
00 02 0 0 0 0 8
|
||||
|
||||
cb36 SLL (HL)*
|
||||
0 MC 0000
|
||||
4 MR 0000 cb
|
||||
4 MC 0001
|
||||
8 MR 0001 36
|
||||
8 MC 6d38
|
||||
11 MR 6d38 f1
|
||||
11 MC 6d38
|
||||
12 MC 6d38
|
||||
15 MW 6d38 e3
|
||||
8aa1 1185 1dde 6d38 0000 0000 0000 0000 0000 0000 0000 0002
|
||||
00 02 0 0 0 0 15
|
||||
6d38 e3 -1
|
||||
|
||||
cb52 BIT 2,D
|
||||
0 MC 0000
|
||||
4 MR 0000 cb
|
||||
4 MC 0001
|
||||
8 MR 0001 52
|
||||
8b74 ff7a b0ff ac44 0000 0000 0000 0000 0000 0000 0000 0002
|
||||
00 02 0 0 0 0 8
|
||||
|
||||
cb93 RES 2,E
|
||||
0 MC 0000
|
||||
4 MR 0000 cb
|
||||
4 MC 0001
|
||||
8 MR 0001 93
|
||||
c200 4e05 b3f8 2234 0000 0000 0000 0000 0000 0000 0000 0002
|
||||
00 02 0 0 0 0 8
|
||||
|
||||
cbc4 SET 0,H
|
||||
0 MC 0000
|
||||
4 MR 0000 cb
|
||||
4 MC 0001
|
||||
8 MR 0001 c4
|
||||
7e00 545a 6ecf 5976 0000 0000 0000 0000 0000 0000 0000 0002
|
||||
00 02 0 0 0 0 8
|
||||
|
||||
dd75 LD (IX+d),L
|
||||
0 MC 0000
|
||||
4 MR 0000 dd
|
||||
4 MC 0001
|
||||
8 MR 0001 75
|
||||
8 MC 0002
|
||||
11 MR 0002 30
|
||||
11 MC 0002
|
||||
12 MC 0002
|
||||
13 MC 0002
|
||||
14 MC 0002
|
||||
15 MC 0002
|
||||
16 MC ae7c
|
||||
19 MW ae7c 4f
|
||||
5772 e833 b63e 734f 0000 0000 0000 0000 ae4c e8c2 0000 0003
|
||||
00 02 0 0 0 0 19
|
||||
ae7c 4f -1
|
||||
|
||||
dd4e LD C,(IX+d)
|
||||
0 MC 0000
|
||||
4 MR 0000 dd
|
||||
4 MC 0001
|
||||
8 MR 0001 4e
|
||||
8 MC 0002
|
||||
11 MR 0002 2e
|
||||
11 MC 0002
|
||||
12 MC 0002
|
||||
13 MC 0002
|
||||
14 MC 0002
|
||||
15 MC 0002
|
||||
16 MC d979
|
||||
19 MR d979 76
|
||||
7bf7 6676 8d55 def2 0000 0000 0000 0000 d94b 17fb 0000 0003
|
||||
00 02 0 0 0 0 19
|
||||
|
||||
@@ -0,0 +1,197 @@
|
||||
00 NOP
|
||||
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
|
||||
00 00 0 0 0 0 1
|
||||
0000 00 -1
|
||||
-1
|
||||
|
||||
ed67 RRD
|
||||
3624 b16a a4db b9de 0000 0000 0000 0000 0000 0000 0000 0000
|
||||
00 00 0 0 0 0 1
|
||||
0000 ed 67 -1
|
||||
b9de 93 -1
|
||||
-1
|
||||
|
||||
ed6f RLD
|
||||
658b 7a7a ecf0 403c 0000 0000 0000 0000 0000 0000 0000 0000
|
||||
00 00 0 0 0 0 1
|
||||
0000 ed 6f -1
|
||||
403c c4 -1
|
||||
-1
|
||||
|
||||
81 ADD A,C
|
||||
f500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000
|
||||
00 00 0 0 0 0 1
|
||||
0000 81 -1
|
||||
dca6 49 -1
|
||||
-1
|
||||
|
||||
cb41 BIT 0,C
|
||||
9e00 1b43 954e 7be9 0000 0000 0000 0000 0000 0000 0000 0000
|
||||
00 00 0 0 0 0 1
|
||||
0000 cb 41 -1
|
||||
7be9 f7 -1
|
||||
-1
|
||||
|
||||
cb93 RES 2,E
|
||||
c200 4e05 b3f8 2234 0000 0000 0000 0000 0000 0000 0000 0000
|
||||
00 00 0 0 0 0 1
|
||||
0000 cb 93 -1
|
||||
2234 a0 -1
|
||||
-1
|
||||
|
||||
cbe5 SET 4,L
|
||||
ca00 df0d d588 b48f 0000 0000 0000 0000 0000 0000 0000 0000
|
||||
00 00 0 0 0 0 1
|
||||
0000 cb e5 -1
|
||||
b48f cf -1
|
||||
-1
|
||||
|
||||
8c ADC A,H
|
||||
f500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000
|
||||
00 00 0 0 0 0 1
|
||||
0000 8c -1
|
||||
dca6 49 -1
|
||||
-1
|
||||
|
||||
92 SUB D
|
||||
f500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000
|
||||
00 00 0 0 0 0 1
|
||||
0000 92 -1
|
||||
dca6 49 -1
|
||||
-1
|
||||
|
||||
9d SBC A,L
|
||||
f500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000
|
||||
00 00 0 0 0 0 1
|
||||
0000 9d -1
|
||||
dca6 49 -1
|
||||
-1
|
||||
|
||||
a3 AND E
|
||||
f500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000
|
||||
00 00 0 0 0 0 1
|
||||
0000 a3 -1
|
||||
dca6 49 -1
|
||||
-1
|
||||
|
||||
ae XOR (HL)
|
||||
f500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000
|
||||
00 00 0 0 0 0 1
|
||||
0000 ae -1
|
||||
dca6 49 -1
|
||||
-1
|
||||
|
||||
b4 OR H
|
||||
f500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000
|
||||
00 00 0 0 0 0 1
|
||||
0000 b4 -1
|
||||
dca6 49 -1
|
||||
-1
|
||||
|
||||
bf CP A
|
||||
f500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000
|
||||
00 00 0 0 0 0 1
|
||||
0000 bf -1
|
||||
dca6 49 -1
|
||||
-1
|
||||
|
||||
43 LD B,E
|
||||
0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000
|
||||
00 00 0 0 0 0 1
|
||||
0000 43 -1
|
||||
a169 50 -1
|
||||
-1
|
||||
|
||||
6e LD L,(HL)
|
||||
0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000
|
||||
00 00 0 0 0 0 1
|
||||
0000 6e -1
|
||||
a169 50 -1
|
||||
-1
|
||||
|
||||
e3 EX (SP),HL
|
||||
0000 0000 0000 4d22 0000 0000 0000 0000 0000 0000 0373 0000
|
||||
00 00 0 0 0 0 1
|
||||
0000 e3 -1
|
||||
0373 8e e1 -1
|
||||
-1
|
||||
|
||||
03 INC BC
|
||||
0000 789a 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
|
||||
00 00 0 0 0 0 1
|
||||
0000 03 -1
|
||||
-1
|
||||
|
||||
3b DEC SP
|
||||
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 9d36 0000
|
||||
00 00 0 0 0 0 1
|
||||
0000 3b -1
|
||||
-1
|
||||
|
||||
07 RLCA
|
||||
8800 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
|
||||
00 00 0 0 0 0 1
|
||||
0000 07 -1
|
||||
-1
|
||||
|
||||
1f RRA
|
||||
01c4 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
|
||||
00 00 0 0 0 0 1
|
||||
0000 1f -1
|
||||
-1
|
||||
|
||||
cb09 RRC C
|
||||
1800 125c dd97 59c6 0000 0000 0000 0000 0000 0000 0000 0000
|
||||
00 00 0 0 0 0 1
|
||||
0000 cb 09 -1
|
||||
59c6 9e -1
|
||||
-1
|
||||
|
||||
cb11 RL C
|
||||
6500 e25c 4b8a ed42 0000 0000 0000 0000 0000 0000 0000 0000
|
||||
00 00 0 0 0 0 1
|
||||
0000 cb 11 -1
|
||||
ed42 b7 -1
|
||||
-1
|
||||
|
||||
cb36 SLL (HL)*
|
||||
8a00 1185 1dde 6d38 0000 0000 0000 0000 0000 0000 0000 0000
|
||||
00 00 0 0 0 0 1
|
||||
0000 cb 36 -1
|
||||
6d38 f1 -1
|
||||
-1
|
||||
|
||||
cb52 BIT 2,D
|
||||
8b00 ff7a b0ff ac44 0000 0000 0000 0000 0000 0000 0000 0000
|
||||
00 00 0 0 0 0 1
|
||||
0000 cb 52 -1
|
||||
ac44 00 -1
|
||||
-1
|
||||
|
||||
cb93 RES 2,E
|
||||
c200 4e05 b3f8 2234 0000 0000 0000 0000 0000 0000 0000 0000
|
||||
00 00 0 0 0 0 1
|
||||
0000 cb 93 -1
|
||||
2234 a0 -1
|
||||
-1
|
||||
|
||||
cbc4 SET 0,H
|
||||
7e00 545a 6ecf 5876 0000 0000 0000 0000 0000 0000 0000 0000
|
||||
00 00 0 0 0 0 1
|
||||
0000 cb c4 -1
|
||||
5876 9d -1
|
||||
-1
|
||||
|
||||
dd75 LD (IX+d),L
|
||||
5772 e833 b63e 734f 0000 0000 0000 0000 ae4c e8c2 0000 0000
|
||||
00 00 0 0 0 0 1
|
||||
0000 dd 75 30 -1
|
||||
-1
|
||||
|
||||
dd4e LD C,(IX+d)
|
||||
7bf7 6605 8d55 def2 0000 0000 0000 0000 d94b 17fb 0000 0000
|
||||
00 00 0 0 0 0 1
|
||||
0000 dd 4e 2e -1
|
||||
d979 76 -1
|
||||
-1
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,124 @@
|
||||
#!/usr/bin/env python3
|
||||
#
|
||||
# This script reads and parses all top-level modules and generates a core block
|
||||
# file containing instantiation of these modules. This generated file is included
|
||||
# by core.vh
|
||||
#
|
||||
#-------------------------------------------------------------------------------
|
||||
# Copyright (C) 2016 Goran Devic
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify it
|
||||
# under the terms of the GNU General Public License as published by the Free
|
||||
# Software Foundation; either version 2 of the License, or (at your option)
|
||||
# any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
# more details.
|
||||
#-------------------------------------------------------------------------------
|
||||
import os
|
||||
|
||||
# Define a set of module cross-connections. These are the chip's internal buses
|
||||
# which we inject as connections as we generate a list of module instances
|
||||
xconnections = [
|
||||
['interrupts', 'db', 'db0[4:3]'],
|
||||
['ir', 'db', 'db0[7:0]'],
|
||||
['alu_control', 'db', 'db1[7:0]'],
|
||||
['alu_control', 'op543', '{pla[104],pla[103],pla[102]}'],
|
||||
['alu_flags', 'db', 'db1[7:0]'],
|
||||
['alu', 'db', 'db2[7:0]'],
|
||||
['alu', 'bsel', 'db0[5:3]'],
|
||||
['reg_file', 'db_hi_ds', 'db2[7:0]'],
|
||||
['reg_file', 'db_lo_ds', 'db1[7:0]'],
|
||||
['reg_file', 'db_hi_as', 'db_hi_as[7:0]'],
|
||||
['reg_file', 'db_lo_as', 'db_lo_as[7:0]'],
|
||||
['address_latch', 'abus', '{db_hi_as[7:0], db_lo_as[7:0]}'],
|
||||
['bus_control', 'db', 'db0[7:0]']
|
||||
]
|
||||
|
||||
# Define a list of modules that are not used (but listed in 'top-level-files.txt' )
|
||||
skip_modules = ['address_pins', 'data_pins', 'control_pins_n']
|
||||
|
||||
# For error-checking, make sure every xconnection entry has been utilized
|
||||
xcount = len(xconnections)
|
||||
|
||||
def connect(module, wire):
|
||||
global xcount
|
||||
for xconnection in xconnections:
|
||||
m, w, xcon = xconnection
|
||||
if module==m and wire==w:
|
||||
print("Cross-connecting:", module, wire, "->", xcon)
|
||||
xcount -= 1
|
||||
return xcon
|
||||
return wire
|
||||
|
||||
def parse(wires, lines):
|
||||
while(len(lines)>0 and lines[0].startswith(');')==False):
|
||||
line = lines[0].strip()
|
||||
lines.pop(0)
|
||||
if len(line)==0 or line[0]=='(' or line[0]=='/':
|
||||
continue
|
||||
tokens = line.split()
|
||||
if len(tokens)>=3 and tokens[0] in ['input', 'output']:
|
||||
tokens.pop(0)
|
||||
if len(tokens)>=2 and tokens[0] in ['wire', 'reg']:
|
||||
tokens.pop(0)
|
||||
if len(tokens)>=2 and tokens[0].startswith('['):
|
||||
tokens.pop(0)
|
||||
if len(tokens)>=2 and tokens[0]=='`include':
|
||||
include_file = tokens[1].replace('"', '')
|
||||
with open('../control/' + include_file) as f:
|
||||
included_lines = f.read().splitlines()
|
||||
parse(wires, included_lines)
|
||||
continue
|
||||
name = tokens[0]
|
||||
if name.endswith(','):
|
||||
name = name[:-1]
|
||||
wires.append(name)
|
||||
|
||||
with open('../top-level-files.txt') as f:
|
||||
files = f.read().splitlines()
|
||||
|
||||
# Create a file that should be included in the top-level core source
|
||||
with open('coremodules.vh', 'w') as file1:
|
||||
file1.write("// Automatically generated by gencoremodules.py\n")
|
||||
|
||||
# Read and parse each file from the list of input files
|
||||
for infile in files:
|
||||
if not os.path.isfile('../' + infile):
|
||||
continue
|
||||
with open('../' + infile, "r") as f:
|
||||
lines = f.read().splitlines()
|
||||
|
||||
# Find 'module' section; read and generate instantiation statement
|
||||
while(len(lines)>0 and lines[0].startswith('module ')==False):
|
||||
lines.pop(0)
|
||||
if len(lines)==0:
|
||||
continue
|
||||
|
||||
module_name = lines[0].split()[1]
|
||||
lines.pop(0)
|
||||
if module_name.endswith('('):
|
||||
module_name = module_name[:-1]
|
||||
if module_name in skip_modules:
|
||||
continue
|
||||
|
||||
# Read a list of input/output wires, one per line
|
||||
wires = []
|
||||
parse(wires, lines)
|
||||
|
||||
# Print the names of all parsed signals in a module instantiation format
|
||||
with open('coremodules.vh', 'a') as file1:
|
||||
file1.write("\n" + module_name + " " + module_name + "_(\n")
|
||||
while(len(wires)>0):
|
||||
wire = wires.pop(0)
|
||||
terminator = ','
|
||||
if len(wires)==0:
|
||||
terminator = "\n);"
|
||||
file1.write(" ." + wire + " (" + connect(module_name, wire) + ")" + terminator + "\n")
|
||||
|
||||
assert(xcount==0)
|
||||
|
||||
# Touch files that include 'coremodules.vh' to ensure it will recompile correctly
|
||||
os.utime("core.vh", None)
|
||||
@@ -0,0 +1,303 @@
|
||||
#!/usr/bin/env python3
|
||||
#
|
||||
# This script generates a test include file from a set of "Fuse" test vectors.
|
||||
#
|
||||
# Three common testing configurations are:
|
||||
#
|
||||
# 1. You want to test a specific instruction only, say 02 LD (BC),A (see Fuse tests.in)
|
||||
# start_test = "02"
|
||||
# run_tests = 1
|
||||
# regress = 0
|
||||
#
|
||||
# 2. You want to run a smaller subset of 'regression' tests:
|
||||
# start_test = "00"
|
||||
# run_tests = 1
|
||||
# regress = 1
|
||||
#
|
||||
# 3. You want to run a full Fuse test suite (all instructions!):
|
||||
# start_test = "00"
|
||||
# run_tests = -1
|
||||
# regress = 0
|
||||
#
|
||||
# Orthogonal to that, set m1wait to a non-zero value to test nWAIT insertion at
|
||||
# the first M1 cycle of an instruction. Change it to the number of T-clocks to
|
||||
# insert.
|
||||
#
|
||||
#-------------------------------------------------------------------------------
|
||||
# Copyright (C) 2016 Goran Devic
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify it
|
||||
# under the terms of the GNU General Public License as published by the Free
|
||||
# Software Foundation; either version 2 of the License, or (at your option)
|
||||
# any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
# more details.
|
||||
#-------------------------------------------------------------------------------
|
||||
import os
|
||||
|
||||
# Start with this test name (this is a string; see tests files)
|
||||
start_test = "00"
|
||||
|
||||
# Number of tests to run; use -1 to run all tests
|
||||
run_tests = 1
|
||||
|
||||
# Set this to 1 to use regression test instead of selected or full 'tests.*'
|
||||
# Regression test is a shorter set of tests and ignores start_test and run_tests values
|
||||
regress = 1
|
||||
|
||||
# Set this to a number of WAIT cycles to add at M1 clock period or 0 not to test nWAIT
|
||||
m1wait = 0
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# Determine which test files to use
|
||||
tests_in = 'fuse/tests.in'
|
||||
tests_expected = 'fuse/tests.expected'
|
||||
|
||||
# Regression testing executes all regression tests
|
||||
if regress:
|
||||
tests_in = 'fuse/regress.in'
|
||||
tests_expected = 'fuse/regress.expected'
|
||||
start_test = "00"
|
||||
run_tests = -1
|
||||
|
||||
with open(tests_in) as f1:
|
||||
t1 = f1.read().splitlines()
|
||||
# Remove all tests until the one we need to start with. Tests are separated by empty lines.
|
||||
while t1[0].split(" ")[0]!=start_test:
|
||||
while len(t1.pop(0))>0:
|
||||
pass
|
||||
t1 = list(filter(None, t1)) # Filter out empty lines
|
||||
|
||||
with open(tests_expected) as f2:
|
||||
t2 = f2.read().splitlines()
|
||||
while t2[0].split(" ")[0]!=start_test:
|
||||
while len(t2.pop(0))>0:
|
||||
pass
|
||||
|
||||
# Count total clocks required to run all selected tests
|
||||
total_clks = 0
|
||||
|
||||
def RegWrite(reg, hex):
|
||||
global total_clks
|
||||
ftest.write(" // Preset " + reg + "\n")
|
||||
ftest.write(" force dut.reg_file_.b2v_latch_" + reg + "_lo.we=1;\n")
|
||||
ftest.write(" force dut.reg_file_.b2v_latch_" + reg + "_hi.we=1;\n")
|
||||
ftest.write(" force dut.reg_file_.b2v_latch_" + reg + "_lo.db=8'h" + hex[2:] + ";\n")
|
||||
ftest.write(" force dut.reg_file_.b2v_latch_" + reg + "_hi.db=8'h" + hex[0:2] + ";\n")
|
||||
ftest.write("#2 release dut.reg_file_.b2v_latch_" + reg + "_lo.we;\n")
|
||||
ftest.write(" release dut.reg_file_.b2v_latch_" + reg + "_hi.we;\n")
|
||||
ftest.write(" release dut.reg_file_.b2v_latch_" + reg + "_lo.db;\n")
|
||||
ftest.write(" release dut.reg_file_.b2v_latch_" + reg + "_hi.db;\n")
|
||||
total_clks = total_clks + 2
|
||||
|
||||
def RegRead(reg, hex):
|
||||
ftest.write(" if (dut.reg_file_.b2v_latch_" + reg + "_lo.latch!==8'h" + hex[2:] + ") $fdisplay(f,\"* Reg " + reg + " " + reg[1] + "=%h !=" + hex[2:] + "\",dut.reg_file_.b2v_latch_" + reg + "_lo.latch);\n")
|
||||
ftest.write(" if (dut.reg_file_.b2v_latch_" + reg + "_hi.latch!==8'h" + hex[0:2] + ") $fdisplay(f,\"* Reg " + reg + " " + reg[0] + "=%h !=" + hex[0:2] + "\",dut.reg_file_.b2v_latch_" + reg + "_hi.latch);\n")
|
||||
|
||||
#---------------------------- START -----------------------------------
|
||||
# Create a file that should be included in the test_fuse source
|
||||
ftest = open('test_fuse.vh', 'w')
|
||||
ftest.write("// Automatically generated by genfuse.py\n\n")
|
||||
|
||||
# Initial pre-test state is reset and control signals asserted
|
||||
ftest.write("force dut.resets_.clrpc=0;\n")
|
||||
ftest.write("force dut.reg_file_.reg_gp_we=0;\n")
|
||||
ftest.write("force dut.reg_control_.ctl_reg_sys_we=0;\n")
|
||||
ftest.write("force dut.z80_top_ifc_n.fpga_reset=1;\n")
|
||||
ftest.write("#2 // Start test loop\n\n")
|
||||
total_clks = total_clks + 2
|
||||
|
||||
# Read each test from the testdat.in file
|
||||
while True:
|
||||
if len(t1)==0 or run_tests==0:
|
||||
break
|
||||
run_tests = run_tests-1
|
||||
|
||||
# Clear opcode register before starting a new instruction
|
||||
ftest.write(" force dut.ir_.ctl_ir_we=1;\n")
|
||||
ftest.write(" force dut.ir_.db=0;\n")
|
||||
ftest.write("#2 release dut.ir_.ctl_ir_we;\n")
|
||||
ftest.write(" release dut.ir_.db;\n")
|
||||
total_clks = total_clks + 2
|
||||
|
||||
# Format of the test.in file:
|
||||
# <arbitrary test description>
|
||||
# AF BC DE HL AF' BC' DE' HL' IX IY SP PC
|
||||
# I R IFF1 IFF2 IM <halted> <tstates>
|
||||
name = t1.pop(0)
|
||||
ftest.write(" $fdisplay(f,\"Testing opcode " + name + "\");\n")
|
||||
name = name.split(" ")[0]
|
||||
r = t1.pop(0).split(' ')
|
||||
r = list(filter(None, r))
|
||||
# 0 1 2 3 4 5 6 7 8 9 10 11 (index)
|
||||
# AF BC DE HL AF' BC' DE' HL' IX IY SP PC
|
||||
RegWrite("af", r[0])
|
||||
RegWrite("bc", r[1])
|
||||
RegWrite("de", r[2])
|
||||
RegWrite("hl", r[3])
|
||||
RegWrite("af2", r[4])
|
||||
RegWrite("bc2", r[5])
|
||||
RegWrite("de2", r[6])
|
||||
RegWrite("hl2", r[7])
|
||||
RegWrite("ix", r[8])
|
||||
RegWrite("iy", r[9])
|
||||
RegWrite("sp", r[10])
|
||||
RegWrite("wz", "0000") # Initialize WZ with 0
|
||||
RegWrite("pc", r[11])
|
||||
|
||||
s = t1.pop(0).split(' ')
|
||||
s = list(filter(None, s))
|
||||
# 0 1 2 3 4 5 6 (index)
|
||||
# I R IFF1 IFF2 IM <halted> <tstates?>
|
||||
RegWrite("ir", s[0]+s[1])
|
||||
# TODO: Store IFF1/IFF2, IM, in_halt
|
||||
|
||||
# Read memory configuration from the test.in until the line contains only -1
|
||||
while True:
|
||||
m = t1.pop(0).split(' ')
|
||||
if m[0]=="-1":
|
||||
break
|
||||
address = int(m.pop(0),16)
|
||||
ftest.write(" // Preset memory\n")
|
||||
while True:
|
||||
d = m.pop(0)
|
||||
if d=="-1":
|
||||
break
|
||||
ftest.write(" ram.Mem[" + str(address) + "] = 8'h" + d + ";\n")
|
||||
address = address+1
|
||||
|
||||
# We need to prepare the IO map to be able to handle IN/OUT instructions.
|
||||
# Copy tests.out (so we don't modify it just yet), parse all PR and PW (port read, write)
|
||||
# statements and then fill in our IO map (for IO reads) or stack the check statements to be
|
||||
# used below after the opcode has executed (for IO writes)
|
||||
check_io = [] # List of check statements (for OUT instructions)
|
||||
t2b = list(t2)
|
||||
while True:
|
||||
m = t2b.pop(0).split(' ')
|
||||
m = list(filter(None, m))
|
||||
if len(m)==0 or m[0]=="-1":
|
||||
break
|
||||
if len(m)==4 and m[1]=="PR":
|
||||
address = int(m[2],16)
|
||||
ftest.write(" io.IO[" + str(address) + "] = 8'h" + m[3] + ";\n")
|
||||
if len(m)==4 and m[1]=="PW":
|
||||
address = int(m[2],16)
|
||||
check_io.append(" if (io.IO[" + str(address) + "]!==8'h" + m[3] + ") $fdisplay(f,\"* IO[" + hex(address)[2:] + "]=%h !=" + m[3] + "\",io.IO[" + str(address) + "]);\n")
|
||||
|
||||
# Prepare instruction to be run. By releasing the fpga_reset, internal CPU reset will be active for 1T.
|
||||
# Due to the instruction execution overlap, first 2T of an instruction may be writing
|
||||
# value back to a general purpose register (like AF) and we need to prevent that.
|
||||
# Similarly, we let the execution continues 2T into the next instruction but we prevent
|
||||
# it from writing to system registers so it cannot update PC and IR.
|
||||
ftest.write(" force dut.z80_top_ifc_n.fpga_reset=0;\n")
|
||||
ftest.write(" force dut.address_latch_.Q=16'h" + r[11] +";\n") # Force PC into the address latch
|
||||
ftest.write(" release dut.reg_control_.ctl_reg_sys_we;\n")
|
||||
ftest.write(" release dut.reg_file_.reg_gp_we;\n")
|
||||
ftest.write("#2 // Execute: M1/T1 start\n") # 1T (#2) overlaps the reset cycle
|
||||
ftest.write("#1 release dut.address_latch_.Q;\n")
|
||||
total_clks = total_clks + 3 # We borrow 1T (#2) to to force the PC to be what our test wants...
|
||||
ftest.write("#1\n")
|
||||
total_clks = total_clks + 1
|
||||
|
||||
# Read and parse the tests expected list which contains the expected results of our run,
|
||||
# including the number of clocks for a particular instruction
|
||||
xname = t2.pop(0).split()[0]
|
||||
if name!=xname:
|
||||
print("Test " + name + " does not correspond to test.expected " + xname)
|
||||
break
|
||||
# Skip the memory access logs; read to the expected register content list
|
||||
while True:
|
||||
l = t2.pop(0)
|
||||
if l[0]!=' ':
|
||||
break
|
||||
r = l.split(' ')
|
||||
r = list(filter(None, r))
|
||||
|
||||
s = t2.pop(0).split(' ')
|
||||
s = list(filter(None, s))
|
||||
|
||||
ticks = int(s[6]) * 2 - 2 # We return 1T (#2) that we borrowed to set PC
|
||||
total_clks = total_clks + ticks
|
||||
|
||||
# Test WAIT state insertion at the M1 clock cycle
|
||||
if m1wait:
|
||||
ftest.write(" z.nWAIT <= 0;\n")
|
||||
ftest.write("#" + str(m1wait * 2) + " z.nWAIT <= 1; // nWAIT during M1\n")
|
||||
total_clks = total_clks + m1wait * 2
|
||||
|
||||
ftest.write("#" + str(ticks) + " // Wait for opcode end\n")
|
||||
|
||||
ftest.write(" force dut.reg_control_.ctl_reg_sys_we=0;\n")
|
||||
ftest.write("#2 pc=z.A;\n") # Extra 2T for the next instruction overlap & read PC on the ABus
|
||||
ftest.write("#2\n") # Complete this instruction
|
||||
ftest.write("#1 force dut.reg_file_.reg_gp_we=0;\n") # Add 1/2 clock for any pending flops to latch (mainly the F register)
|
||||
ftest.write(" force dut.z80_top_ifc_n.fpga_reset=1;\n")
|
||||
total_clks = total_clks + 5
|
||||
|
||||
# Now we can issue register reading commands
|
||||
# We are guided on what to read and check by the content of "test.expected" file
|
||||
|
||||
# Special case are the register exchange instructions and there are 3 of them.
|
||||
# The exchange operations are not tested directly; instead, the latches that control register bank access are
|
||||
if xname=="08": # EX AF,AF1
|
||||
r[0],r[4] = r[4],r[0]
|
||||
ftest.write(" if (dut.reg_control_.bank_af!==1) $fdisplay(f,\"* Bank AF!=1\");\n")
|
||||
if xname=="eb": # EX DE,HL
|
||||
r[2],r[3] = r[3],r[2]
|
||||
ftest.write(" if (dut.reg_control_.bank_hl_de1!==1) $fdisplay(f,\"* Bank HL/DE!=1\");\n")
|
||||
if xname=="d9": # EXX
|
||||
r[1],r[5] = r[5],r[1]
|
||||
r[2],r[6] = r[6],r[2]
|
||||
r[3],r[7] = r[7],r[3]
|
||||
ftest.write(" if (dut.reg_control_.bank_exx!==1) $fdisplay(f,\"* Bank EXX!=1\");\n")
|
||||
|
||||
# Read the result: registers and memory
|
||||
# 0 1 2 3 4 5 6 7 8 9 10 11 (index)
|
||||
# AF BC DE HL AF' BC' DE' HL' IX IY SP PC
|
||||
RegRead("af", r[0])
|
||||
RegRead("bc", r[1])
|
||||
RegRead("de", r[2])
|
||||
RegRead("hl", r[3])
|
||||
RegRead("af2", r[4])
|
||||
RegRead("bc2", r[5])
|
||||
RegRead("de2", r[6])
|
||||
RegRead("hl2", r[7])
|
||||
RegRead("ix", r[8])
|
||||
RegRead("iy", r[9])
|
||||
RegRead("sp", r[10])
|
||||
#RegRead("pc", r[11]) Instead of PC, we read the address bus of the next instruction
|
||||
ftest.write(" if (pc!==16'h" + r[11] + ") $fdisplay(f,\"* PC=%h !=" + r[11] + "\",pc);\n")
|
||||
|
||||
# 0 1 2 3 4 5 6 (index)
|
||||
# I R IFF1 IFF2 IM <halted> <tstates?>
|
||||
RegRead("ir", s[0]+s[1])
|
||||
|
||||
# Read memory configuration until an empty line or -1 at the end
|
||||
while True:
|
||||
m = t2.pop(0).split(' ')
|
||||
m = list(filter(None, m))
|
||||
if len(m)==0 or m[0]=="-1":
|
||||
break
|
||||
address = int(m.pop(0),16)
|
||||
while True:
|
||||
d = m.pop(0)
|
||||
if d=="-1":
|
||||
break
|
||||
ftest.write(" if (ram.Mem[" + str(address) + "]!==8'h" + d + ") $fdisplay(f,\"* Mem[" + hex(address)[2:] + "]=%h !=" + d + "\",ram.Mem[" + str(address) + "]);\n")
|
||||
address = address+1
|
||||
# Read a list of IO checks that was compiled while parsing the initial condition
|
||||
while len(check_io)>0:
|
||||
ftest.write(check_io.pop(0))
|
||||
ftest.write("#1 // End opcode\n\n")
|
||||
total_clks = total_clks + 1
|
||||
|
||||
# Write out the total number of clocks that this set of tests takes to execute
|
||||
ftest.write("`define TOTAL_CLKS " + str(total_clks) + "\n")
|
||||
ftest.write("$fdisplay(f,\"=== Tests completed ===\");\n")
|
||||
ftest.close()
|
||||
|
||||
# Touch a file that includes 'test_fuse.vh' to ensure it will recompile correctly
|
||||
os.utime("test_fuse.sv", None)
|
||||
@@ -0,0 +1,63 @@
|
||||
#!/usr/bin/env python3
|
||||
#
|
||||
# This script reads and parses selected Verilog and SystemVerilog modules
|
||||
# and generates a set of Verilog include files for the Z80 top-level block.
|
||||
#
|
||||
#-------------------------------------------------------------------------------
|
||||
# Copyright (C) 2014 Goran Devic
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify it
|
||||
# under the terms of the GNU General Public License as published by the Free
|
||||
# Software Foundation; either version 2 of the License, or (at your option)
|
||||
# any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
# more details.
|
||||
#-------------------------------------------------------------------------------
|
||||
import os
|
||||
|
||||
with open('../top-level-files.txt') as f:
|
||||
files = f.read().splitlines()
|
||||
|
||||
# Create a file that should be included in the top-level source
|
||||
with open('globals.vh', 'w') as file1:
|
||||
file1.write("// Automatically generated by genglobals.py\n")
|
||||
|
||||
# Keep track of duplicated symbols across all files
|
||||
globals = []
|
||||
|
||||
# Read and parse each file from the list of input files
|
||||
for infile in files:
|
||||
wires = []
|
||||
if not os.path.isfile('../' + infile):
|
||||
continue
|
||||
with open('../' + infile, "r") as f:
|
||||
for line in f:
|
||||
info = line.split()
|
||||
if len(info)>2:
|
||||
# There can be only one driver for each signal so we read only the outputs
|
||||
if info[0]=="output" and (info[1]=="wire" or info[1]=="reg" or info[1]=="logic"):
|
||||
# There are 2 cases: wires and buses
|
||||
if info[2].startswith('['):
|
||||
wires.append(info[2] + ' ' + info[3].strip(';,'))
|
||||
else:
|
||||
wires.append(info[2].strip(';,'))
|
||||
|
||||
if len(wires)>0:
|
||||
with open('globals.vh', 'a') as file1:
|
||||
file1.write("\n// Module: " + infile + "\n")
|
||||
for wire in wires:
|
||||
# Everything in globals is a wire
|
||||
# (Can't use 'logic' since some buses are bidirectional)
|
||||
if wire in globals:
|
||||
file1.write("// wire " + wire + "; (previously defined)\n")
|
||||
else:
|
||||
file1.write("wire " + wire + ";\n")
|
||||
globals.append(wire)
|
||||
|
||||
# Touch files that include 'globals.vh' to ensure it will recompile correctly
|
||||
os.utime("core.vh", None)
|
||||
os.utime("z80_top_direct_n.v", None)
|
||||
os.utime("z80_top_ifc_n.sv", None)
|
||||
@@ -0,0 +1,290 @@
|
||||
// Automatically generated by genglobals.py
|
||||
|
||||
// Module: control/clk_delay.v
|
||||
wire hold_clk_iorq;
|
||||
wire hold_clk_wait;
|
||||
wire iorq_Tw;
|
||||
wire busack;
|
||||
wire pin_control_oe;
|
||||
wire hold_clk_busrq;
|
||||
wire nhold_clk_wait;
|
||||
|
||||
// Module: control/decode_state.v
|
||||
wire in_halt;
|
||||
wire table_cb;
|
||||
wire table_ed;
|
||||
wire table_xx;
|
||||
wire use_ix;
|
||||
wire use_ixiy;
|
||||
wire in_alu;
|
||||
wire repeat_en;
|
||||
|
||||
// Module: control/exec_module.vh
|
||||
wire ctl_state_iy_set;
|
||||
wire ctl_state_ixiy_clr;
|
||||
wire ctl_state_ixiy_we;
|
||||
wire ctl_state_halt_set;
|
||||
wire ctl_state_tbl_ed_set;
|
||||
wire ctl_state_tbl_cb_set;
|
||||
wire ctl_state_alu;
|
||||
wire ctl_repeat_we;
|
||||
wire ctl_state_tbl_we;
|
||||
wire ctl_iff1_iff2;
|
||||
wire ctl_iffx_we;
|
||||
wire ctl_iffx_bit;
|
||||
wire ctl_im_we;
|
||||
wire ctl_no_ints;
|
||||
wire ctl_ir_we;
|
||||
wire ctl_mRead;
|
||||
wire ctl_mWrite;
|
||||
wire ctl_iorw;
|
||||
wire ctl_shift_en;
|
||||
wire ctl_daa_oe;
|
||||
wire ctl_alu_op_low;
|
||||
wire ctl_cond_short;
|
||||
wire ctl_alu_core_hf;
|
||||
wire ctl_eval_cond;
|
||||
wire ctl_66_oe;
|
||||
wire [1:0] ctl_pf_sel;
|
||||
wire ctl_alu_oe;
|
||||
wire ctl_alu_shift_oe;
|
||||
wire ctl_alu_op2_oe;
|
||||
wire ctl_alu_res_oe;
|
||||
wire ctl_alu_op1_oe;
|
||||
wire ctl_alu_bs_oe;
|
||||
wire ctl_alu_op1_sel_bus;
|
||||
wire ctl_alu_op1_sel_low;
|
||||
wire ctl_alu_op1_sel_zero;
|
||||
wire ctl_alu_op2_sel_zero;
|
||||
wire ctl_alu_op2_sel_bus;
|
||||
wire ctl_alu_op2_sel_lq;
|
||||
wire ctl_alu_sel_op2_neg;
|
||||
wire ctl_alu_sel_op2_high;
|
||||
wire ctl_alu_core_R;
|
||||
wire ctl_alu_core_V;
|
||||
wire ctl_alu_core_S;
|
||||
wire ctl_flags_oe;
|
||||
wire ctl_flags_bus;
|
||||
wire ctl_flags_alu;
|
||||
wire ctl_flags_nf_set;
|
||||
wire ctl_flags_cf_set;
|
||||
wire ctl_flags_cf_cpl;
|
||||
wire ctl_flags_cf_we;
|
||||
wire ctl_flags_sz_we;
|
||||
wire ctl_flags_xy_we;
|
||||
wire ctl_flags_hf_we;
|
||||
wire ctl_flags_pf_we;
|
||||
wire ctl_flags_nf_we;
|
||||
wire ctl_flags_cf2_we;
|
||||
wire ctl_flags_hf_cpl;
|
||||
wire ctl_flags_use_cf2;
|
||||
wire ctl_flags_hf2_we;
|
||||
wire ctl_flags_nf_clr;
|
||||
wire ctl_alu_zero_16bit;
|
||||
wire ctl_flags_cf2_sel_shift;
|
||||
wire ctl_flags_cf2_sel_daa;
|
||||
wire ctl_sw_4u;
|
||||
wire ctl_reg_in_hi;
|
||||
wire ctl_reg_in_lo;
|
||||
wire ctl_reg_out_lo;
|
||||
wire ctl_reg_out_hi;
|
||||
wire ctl_reg_exx;
|
||||
wire ctl_reg_ex_af;
|
||||
wire ctl_reg_ex_de_hl;
|
||||
wire ctl_reg_use_sp;
|
||||
wire ctl_reg_sel_pc;
|
||||
wire ctl_reg_sel_ir;
|
||||
wire ctl_reg_sel_wz;
|
||||
wire ctl_reg_gp_we;
|
||||
wire ctl_reg_not_pc;
|
||||
wire ctl_reg_sys_we_lo;
|
||||
wire ctl_reg_sys_we_hi;
|
||||
wire ctl_reg_sys_we;
|
||||
wire ctl_sw_4d;
|
||||
wire [1:0] ctl_reg_gp_hilo;
|
||||
wire [1:0] ctl_reg_gp_sel;
|
||||
wire [1:0] ctl_reg_sys_hilo;
|
||||
wire ctl_inc_cy;
|
||||
wire ctl_inc_dec;
|
||||
wire ctl_al_we;
|
||||
wire ctl_inc_limit6;
|
||||
wire ctl_bus_inc_oe;
|
||||
wire ctl_apin_mux;
|
||||
wire ctl_apin_mux2;
|
||||
wire ctl_bus_ff_oe;
|
||||
wire ctl_bus_zero_oe;
|
||||
wire ctl_sw_1u;
|
||||
wire ctl_sw_1d;
|
||||
wire ctl_sw_2u;
|
||||
wire ctl_sw_2d;
|
||||
wire ctl_sw_mask543_en;
|
||||
wire ctl_bus_db_we;
|
||||
wire ctl_bus_db_oe;
|
||||
|
||||
// Module: control/execute.v
|
||||
wire nextM;
|
||||
wire setM1;
|
||||
wire fFetch;
|
||||
wire fMRead;
|
||||
wire fMWrite;
|
||||
wire fIORead;
|
||||
wire fIOWrite;
|
||||
|
||||
// Module: control/interrupts.v
|
||||
wire iff2;
|
||||
wire im1;
|
||||
wire im2;
|
||||
wire in_nmi;
|
||||
wire in_intr;
|
||||
|
||||
// Module: control/ir.v
|
||||
wire [7:0] opcode;
|
||||
|
||||
// Module: control/pin_control.v
|
||||
wire bus_ab_pin_we;
|
||||
wire bus_db_pin_oe;
|
||||
wire bus_db_pin_re;
|
||||
|
||||
// Module: control/pla_decode.v
|
||||
wire [104:0] pla;
|
||||
|
||||
// Module: control/resets.v
|
||||
wire clrpc;
|
||||
wire nreset;
|
||||
|
||||
// Module: control/memory_ifc.v
|
||||
wire nM1_out;
|
||||
wire nRFSH_out;
|
||||
wire nMREQ_out;
|
||||
wire nRD_out;
|
||||
wire nWR_out;
|
||||
wire nIORQ_out;
|
||||
wire latch_wait;
|
||||
wire wait_m1;
|
||||
|
||||
// Module: control/sequencer.v
|
||||
wire M1;
|
||||
wire M2;
|
||||
wire M3;
|
||||
wire M4;
|
||||
wire M5;
|
||||
wire T1;
|
||||
wire T2;
|
||||
wire T3;
|
||||
wire T4;
|
||||
wire T5;
|
||||
wire T6;
|
||||
wire timings_en;
|
||||
|
||||
// Module: alu/alu_control.v
|
||||
wire alu_shift_in;
|
||||
wire alu_shift_right;
|
||||
wire alu_shift_left;
|
||||
wire shift_cf_out;
|
||||
wire alu_parity_in;
|
||||
wire flags_cond_true;
|
||||
wire daa_cf_out;
|
||||
wire pf_sel;
|
||||
wire alu_op_low;
|
||||
wire alu_core_cf_in;
|
||||
wire [7:0] db;
|
||||
|
||||
// Module: alu/alu_select.v
|
||||
wire alu_oe;
|
||||
wire alu_shift_oe;
|
||||
wire alu_op2_oe;
|
||||
wire alu_res_oe;
|
||||
wire alu_op1_oe;
|
||||
wire alu_bs_oe;
|
||||
wire alu_op1_sel_bus;
|
||||
wire alu_op1_sel_low;
|
||||
wire alu_op1_sel_zero;
|
||||
wire alu_op2_sel_zero;
|
||||
wire alu_op2_sel_bus;
|
||||
wire alu_op2_sel_lq;
|
||||
wire alu_sel_op2_neg;
|
||||
wire alu_sel_op2_high;
|
||||
wire alu_core_R;
|
||||
wire alu_core_V;
|
||||
wire alu_core_S;
|
||||
|
||||
// Module: alu/alu_flags.v
|
||||
wire flags_sf;
|
||||
wire flags_zf;
|
||||
wire flags_hf;
|
||||
wire flags_pf;
|
||||
wire flags_cf;
|
||||
wire flags_nf;
|
||||
wire flags_cf_latch;
|
||||
wire flags_hf2;
|
||||
|
||||
// Module: alu/alu.v
|
||||
wire alu_zero;
|
||||
wire alu_parity_out;
|
||||
wire alu_high_eq_9;
|
||||
wire alu_high_gt_9;
|
||||
wire alu_low_gt_9;
|
||||
wire alu_shift_db0;
|
||||
wire alu_shift_db7;
|
||||
wire alu_core_cf_out;
|
||||
wire alu_sf_out;
|
||||
wire alu_yf_out;
|
||||
wire alu_xf_out;
|
||||
wire alu_vf_out;
|
||||
wire [3:0] test_db_high;
|
||||
wire [3:0] test_db_low;
|
||||
|
||||
// Module: registers/reg_control.v
|
||||
wire reg_sel_bc;
|
||||
wire reg_sel_bc2;
|
||||
wire reg_sel_ix;
|
||||
wire reg_sel_iy;
|
||||
wire reg_sel_de;
|
||||
wire reg_sel_hl;
|
||||
wire reg_sel_de2;
|
||||
wire reg_sel_hl2;
|
||||
wire reg_sel_af;
|
||||
wire reg_sel_af2;
|
||||
wire reg_sel_wz;
|
||||
wire reg_sel_pc;
|
||||
wire reg_sel_ir;
|
||||
wire reg_sel_sp;
|
||||
wire reg_sel_gp_hi;
|
||||
wire reg_sel_gp_lo;
|
||||
wire reg_sel_sys_lo;
|
||||
wire reg_sel_sys_hi;
|
||||
wire reg_gp_we;
|
||||
wire reg_sys_we_lo;
|
||||
wire reg_sys_we_hi;
|
||||
wire reg_sw_4d_lo;
|
||||
wire reg_sw_4d_hi;
|
||||
|
||||
// Module: bus/address_latch.v
|
||||
wire address_is_1;
|
||||
wire [15:0] address;
|
||||
|
||||
// Module: bus/address_pins.v
|
||||
wire [15:0] abus;
|
||||
|
||||
// Module: bus/bus_switch.v
|
||||
wire bus_sw_1u;
|
||||
wire bus_sw_1d;
|
||||
wire bus_sw_2u;
|
||||
wire bus_sw_2d;
|
||||
wire bus_sw_mask543_en;
|
||||
|
||||
// Module: bus/control_pins_n.v
|
||||
wire nmi;
|
||||
wire busrq;
|
||||
wire clk;
|
||||
wire intr;
|
||||
wire mwait;
|
||||
wire reset_in;
|
||||
wire pin_nM1;
|
||||
wire pin_nMREQ;
|
||||
wire pin_nIORQ;
|
||||
wire pin_nRD;
|
||||
wire pin_nWR;
|
||||
wire pin_nRFSH;
|
||||
wire pin_nHALT;
|
||||
wire pin_nBUSACK;
|
||||
@@ -0,0 +1 @@
|
||||
00
|
||||
@@ -0,0 +1 @@
|
||||
restart -f ; run -all
|
||||
@@ -0,0 +1,24 @@
|
||||
C3 8F 00 00 00 79 FE 02 CA 11 00 FE 09 CA 21 00
|
||||
C9 01 00 0A ED 78 CB 47 C2 11 00 01 00 08 ED 59
|
||||
C9 D5 E1 5E 7B FE 24 C8 CD 11 00 23 C3 23 00 00
|
||||
00 00 00 00 00 00 00 00 D5 11 4B 00 F5 C5 E5 0E
|
||||
09 CD 05 00 E1 C1 F1 D1 FB ED 4D 5F 49 4E 54 5F
|
||||
24 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 F5 C5 D5 E5 11 78 00 0E 09 CD
|
||||
05 00 E1 D1 C1 F1 ED 45 5F 4E 4D 49 5F 24 00 00
|
||||
82 00 D5 11 89 00 C3 3C 00 5F 49 4D 32 5F 24 31
|
||||
00 40 ED 5E 3E 00 ED 47 FB C3 00 01 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
21 00 00 22 60 01 11 64 01 0E 09 CD 05 00 2A 60
|
||||
01 23 22 60 01 21 66 01 3A 61 01 CD 3F 01 21 68
|
||||
01 3A 60 01 CD 3F 01 ED 73 62 01 21 6B 01 3A 63
|
||||
01 CD 3F 01 21 6D 01 3A 62 01 CD 3F 01 18 C7 F5
|
||||
E6 0F FE 0A DA 49 01 C6 07 C6 30 23 77 2B F1 1F
|
||||
1F 1F 1F E6 0F FE 0A DA 5C 01 C6 07 C6 30 77 C9
|
||||
00 00 00 00 0D 0A 30 30 30 30 20 30 30 30 30 20
|
||||
48 65 6C 6C 6F 2C 20 57 6F 72 6C 64 21 0D 0A 24
|
||||
@@ -0,0 +1,594 @@
|
||||
; Copyright 1991-2009 Mentor Graphics Corporation
|
||||
;
|
||||
; All Rights Reserved.
|
||||
;
|
||||
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
|
||||
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
;
|
||||
|
||||
[Library]
|
||||
std = $MODEL_TECH/../std
|
||||
ieee = $MODEL_TECH/../ieee
|
||||
verilog = $MODEL_TECH/../verilog
|
||||
vital2000 = $MODEL_TECH/../vital2000
|
||||
std_developerskit = $MODEL_TECH/../std_developerskit
|
||||
synopsys = $MODEL_TECH/../synopsys
|
||||
modelsim_lib = $MODEL_TECH/../modelsim_lib
|
||||
sv_std = $MODEL_TECH/../sv_std
|
||||
|
||||
; Altera Primitive libraries
|
||||
;
|
||||
; VHDL Section
|
||||
;
|
||||
altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
|
||||
altera = $MODEL_TECH/../altera/vhdl/altera
|
||||
altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim
|
||||
lpm = $MODEL_TECH/../altera/vhdl/220model
|
||||
220model = $MODEL_TECH/../altera/vhdl/220model
|
||||
max = $MODEL_TECH/../altera/vhdl/max
|
||||
maxii = $MODEL_TECH/../altera/vhdl/maxii
|
||||
maxv = $MODEL_TECH/../altera/vhdl/maxv
|
||||
stratix = $MODEL_TECH/../altera/vhdl/stratix
|
||||
stratixii = $MODEL_TECH/../altera/vhdl/stratixii
|
||||
stratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx
|
||||
hardcopyii = $MODEL_TECH/../altera/vhdl/hardcopyii
|
||||
hardcopyiii = $MODEL_TECH/../altera/vhdl/hardcopyiii
|
||||
hardcopyiv = $MODEL_TECH/../altera/vhdl/hardcopyiv
|
||||
cyclone = $MODEL_TECH/../altera/vhdl/cyclone
|
||||
cycloneii = $MODEL_TECH/../altera/vhdl/cycloneii
|
||||
cycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii
|
||||
cycloneiiils = $MODEL_TECH/../altera/vhdl/cycloneiiils
|
||||
sgate = $MODEL_TECH/../altera/vhdl/sgate
|
||||
stratixgx = $MODEL_TECH/../altera/vhdl/stratixgx
|
||||
altgxb = $MODEL_TECH/../altera/vhdl/altgxb
|
||||
stratixgx_gxb = $MODEL_TECH/../altera/vhdl/stratixgx_gxb
|
||||
stratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi
|
||||
arriagx_hssi = $MODEL_TECH/../altera/vhdl/arriagx_hssi
|
||||
arriaii = $MODEL_TECH/../altera/vhdl/arriaii
|
||||
arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
|
||||
arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
|
||||
arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz
|
||||
arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi
|
||||
arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip
|
||||
arriagx = $MODEL_TECH/../altera/vhdl/arriagx
|
||||
altgxb_lib = $MODEL_TECH/../altera/vhdl/altgxb
|
||||
stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
|
||||
stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
|
||||
stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
|
||||
cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
|
||||
cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
|
||||
cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
|
||||
cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive
|
||||
hardcopyiv_hssi = $MODEL_TECH/../altera/vhdl/hardcopyiv_hssi
|
||||
hardcopyiv_pcie_hip = $MODEL_TECH/../altera/vhdl/hardcopyiv_pcie_hip
|
||||
stratixv = $MODEL_TECH/../altera/vhdl/stratixv
|
||||
stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi
|
||||
stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip
|
||||
arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz
|
||||
arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi
|
||||
arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip
|
||||
arriav = $MODEL_TECH/../altera/vhdl/arriav
|
||||
cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev
|
||||
;
|
||||
; Verilog Section
|
||||
;
|
||||
altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
|
||||
altera_ver = $MODEL_TECH/../altera/verilog/altera
|
||||
altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim
|
||||
lpm_ver = $MODEL_TECH/../altera/verilog/220model
|
||||
220model_ver = $MODEL_TECH/../altera/verilog/220model
|
||||
max_ver = $MODEL_TECH/../altera/verilog/max
|
||||
maxii_ver = $MODEL_TECH/../altera/verilog/maxii
|
||||
maxv_ver = $MODEL_TECH/../altera/verilog/maxv
|
||||
stratix_ver = $MODEL_TECH/../altera/verilog/stratix
|
||||
stratixii_ver = $MODEL_TECH/../altera/verilog/stratixii
|
||||
stratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx
|
||||
arriagx_ver = $MODEL_TECH/../altera/verilog/arriagx
|
||||
hardcopyii_ver = $MODEL_TECH/../altera/verilog/hardcopyii
|
||||
hardcopyiii_ver = $MODEL_TECH/../altera/verilog/hardcopyiii
|
||||
hardcopyiv_ver = $MODEL_TECH/../altera/verilog/hardcopyiv
|
||||
cyclone_ver = $MODEL_TECH/../altera/verilog/cyclone
|
||||
cycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii
|
||||
cycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii
|
||||
cycloneiiils_ver = $MODEL_TECH/../altera/verilog/cycloneiiils
|
||||
sgate_ver = $MODEL_TECH/../altera/verilog/sgate
|
||||
stratixgx_ver = $MODEL_TECH/../altera/verilog/stratixgx
|
||||
altgxb_ver = $MODEL_TECH/../altera/verilog/altgxb
|
||||
stratixgx_gxb_ver = $MODEL_TECH/../altera/verilog/stratixgx_gxb
|
||||
stratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi
|
||||
arriagx_hssi_ver = $MODEL_TECH/../altera/verilog/arriagx_hssi
|
||||
arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
|
||||
arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
|
||||
arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
|
||||
arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz
|
||||
arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi
|
||||
arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip
|
||||
stratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii
|
||||
stratixiii = $MODEL_TECH/../altera/vhdl/stratixiii
|
||||
stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
|
||||
stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
|
||||
stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
|
||||
stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv
|
||||
stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi
|
||||
stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip
|
||||
arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz
|
||||
arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi
|
||||
arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip
|
||||
arriav_ver = $MODEL_TECH/../altera/verilog/arriav
|
||||
arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi
|
||||
arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip
|
||||
cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev
|
||||
cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi
|
||||
cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip
|
||||
cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
|
||||
cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
|
||||
cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
|
||||
cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
|
||||
hardcopyiv_hssi_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_hssi
|
||||
hardcopyiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_pcie_hip
|
||||
|
||||
[vcom]
|
||||
; VHDL93 variable selects language version as the default.
|
||||
; Default is VHDL-2002.
|
||||
; Value of 0 or 1987 for VHDL-1987.
|
||||
; Value of 1 or 1993 for VHDL-1993.
|
||||
; Default or value of 2 or 2002 for VHDL-2002.
|
||||
; Default or value of 3 or 2008 for VHDL-2008.
|
||||
VHDL93 = 2002
|
||||
|
||||
; Show source line containing error. Default is off.
|
||||
; Show_source = 1
|
||||
|
||||
; Turn off unbound-component warnings. Default is on.
|
||||
; Show_Warning1 = 0
|
||||
|
||||
; Turn off process-without-a-wait-statement warnings. Default is on.
|
||||
; Show_Warning2 = 0
|
||||
|
||||
; Turn off null-range warnings. Default is on.
|
||||
; Show_Warning3 = 0
|
||||
|
||||
; Turn off no-space-in-time-literal warnings. Default is on.
|
||||
; Show_Warning4 = 0
|
||||
|
||||
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
|
||||
; Show_Warning5 = 0
|
||||
|
||||
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
|
||||
; Optimize_1164 = 0
|
||||
|
||||
; Turn on resolving of ambiguous function overloading in favor of the
|
||||
; "explicit" function declaration (not the one automatically created by
|
||||
; the compiler for each type declaration). Default is off.
|
||||
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
|
||||
; will match the behavior of synthesis tools.
|
||||
Explicit = 1
|
||||
|
||||
; Turn off acceleration of the VITAL packages. Default is to accelerate.
|
||||
; NoVital = 1
|
||||
|
||||
; Turn off VITAL compliance checking. Default is checking on.
|
||||
; NoVitalCheck = 1
|
||||
|
||||
; Ignore VITAL compliance checking errors. Default is to not ignore.
|
||||
; IgnoreVitalErrors = 1
|
||||
|
||||
; Turn off VITAL compliance checking warnings. Default is to show warnings.
|
||||
; Show_VitalChecksWarnings = 0
|
||||
|
||||
; Keep silent about case statement static warnings.
|
||||
; Default is to give a warning.
|
||||
; NoCaseStaticError = 1
|
||||
|
||||
; Keep silent about warnings caused by aggregates that are not locally static.
|
||||
; Default is to give a warning.
|
||||
; NoOthersStaticError = 1
|
||||
|
||||
; Turn off inclusion of debugging info within design units.
|
||||
; Default is to include debugging info.
|
||||
; NoDebug = 1
|
||||
|
||||
; Turn off "Loading..." messages. Default is messages on.
|
||||
; Quiet = 1
|
||||
|
||||
; Turn on some limited synthesis rule compliance checking. Checks only:
|
||||
; -- signals used (read) by a process must be in the sensitivity list
|
||||
; CheckSynthesis = 1
|
||||
|
||||
; Activate optimizations on expressions that do not involve signals,
|
||||
; waits, or function/procedure/task invocations. Default is off.
|
||||
; ScalarOpts = 1
|
||||
|
||||
; Require the user to specify a configuration for all bindings,
|
||||
; and do not generate a compile time default binding for the
|
||||
; component. This will result in an elaboration error of
|
||||
; 'component not bound' if the user fails to do so. Avoids the rare
|
||||
; issue of a false dependency upon the unused default binding.
|
||||
; RequireConfigForAllDefaultBinding = 1
|
||||
|
||||
; Inhibit range checking on subscripts of arrays. Range checking on
|
||||
; scalars defined with subtypes is inhibited by default.
|
||||
; NoIndexCheck = 1
|
||||
|
||||
; Inhibit range checks on all (implicit and explicit) assignments to
|
||||
; scalar objects defined with subtypes.
|
||||
; NoRangeCheck = 1
|
||||
|
||||
[vlog]
|
||||
|
||||
; Turn off inclusion of debugging info within design units.
|
||||
; Default is to include debugging info.
|
||||
; NoDebug = 1
|
||||
|
||||
; Turn off "loading..." messages. Default is messages on.
|
||||
; Quiet = 1
|
||||
|
||||
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
|
||||
; Default is off.
|
||||
; Hazard = 1
|
||||
|
||||
; Turn on converting regular Verilog identifiers to uppercase. Allows case
|
||||
; insensitivity for module names. Default is no conversion.
|
||||
; UpCase = 1
|
||||
|
||||
; Turn on incremental compilation of modules. Default is off.
|
||||
; Incremental = 1
|
||||
|
||||
; Turns on lint-style checking.
|
||||
; Show_Lint = 1
|
||||
|
||||
[vsim]
|
||||
; Simulator resolution
|
||||
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
|
||||
Resolution = ps
|
||||
|
||||
; User time unit for run commands
|
||||
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
|
||||
; unit specified for Resolution. For example, if Resolution is 100ps,
|
||||
; then UserTimeUnit defaults to ps.
|
||||
; Should generally be set to default.
|
||||
UserTimeUnit = default
|
||||
|
||||
; Default run length
|
||||
RunLength = 1 us
|
||||
|
||||
; Maximum iterations that can be run without advancing simulation time
|
||||
IterationLimit = 5000
|
||||
|
||||
; Directive to license manager:
|
||||
; vhdl Immediately reserve a VHDL license
|
||||
; vlog Immediately reserve a Verilog license
|
||||
; plus Immediately reserve a VHDL and Verilog license
|
||||
; nomgc Do not look for Mentor Graphics Licenses
|
||||
; nomti Do not look for Model Technology Licenses
|
||||
; noqueue Do not wait in the license queue when a license isn't available
|
||||
; viewsim Try for viewer license but accept simulator license(s) instead
|
||||
; of queuing for viewer license
|
||||
; License = plus
|
||||
|
||||
; Stop the simulator after a VHDL/Verilog assertion message
|
||||
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
|
||||
BreakOnAssertion = 3
|
||||
|
||||
; Assertion Message Format
|
||||
; %S - Severity Level
|
||||
; %R - Report Message
|
||||
; %T - Time of assertion
|
||||
; %D - Delta
|
||||
; %I - Instance or Region pathname (if available)
|
||||
; %% - print '%' character
|
||||
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
|
||||
|
||||
; Assertion File - alternate file for storing VHDL/Verilog assertion messages
|
||||
; AssertFile = assert.log
|
||||
|
||||
; Default radix for all windows and commands...
|
||||
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
|
||||
DefaultRadix = hexadecimal
|
||||
|
||||
; VSIM Startup command
|
||||
; Startup = do startup.do
|
||||
|
||||
; File for saving command transcript
|
||||
TranscriptFile = transcript
|
||||
|
||||
; File for saving command history
|
||||
; CommandHistory = cmdhist.log
|
||||
|
||||
; Specify whether paths in simulator commands should be described
|
||||
; in VHDL or Verilog format.
|
||||
; For VHDL, PathSeparator = /
|
||||
; For Verilog, PathSeparator = .
|
||||
; Must not be the same character as DatasetSeparator.
|
||||
PathSeparator = /
|
||||
|
||||
; Specify the dataset separator for fully rooted contexts.
|
||||
; The default is ':'. For example, sim:/top
|
||||
; Must not be the same character as PathSeparator.
|
||||
DatasetSeparator = :
|
||||
|
||||
; Disable VHDL assertion messages
|
||||
; IgnoreNote = 1
|
||||
; IgnoreWarning = 1
|
||||
; IgnoreError = 1
|
||||
; IgnoreFailure = 1
|
||||
|
||||
; Default force kind. May be freeze, drive, deposit, or default
|
||||
; or in other terms, fixed, wired, or charged.
|
||||
; A value of "default" will use the signal kind to determine the
|
||||
; force kind, drive for resolved signals, freeze for unresolved signals
|
||||
; DefaultForceKind = freeze
|
||||
|
||||
; If zero, open files when elaborated; otherwise, open files on
|
||||
; first read or write. Default is 0.
|
||||
; DelayFileOpen = 1
|
||||
|
||||
; Control VHDL files opened for write.
|
||||
; 0 = Buffered, 1 = Unbuffered
|
||||
UnbufferedOutput = 0
|
||||
|
||||
; Control the number of VHDL files open concurrently.
|
||||
; This number should always be less than the current ulimit
|
||||
; setting for max file descriptors.
|
||||
; 0 = unlimited
|
||||
ConcurrentFileLimit = 40
|
||||
|
||||
; Control the number of hierarchical regions displayed as
|
||||
; part of a signal name shown in the Wave window.
|
||||
; A value of zero tells VSIM to display the full name.
|
||||
; The default is 0.
|
||||
; WaveSignalNameWidth = 0
|
||||
|
||||
; Turn off warnings from the std_logic_arith, std_logic_unsigned
|
||||
; and std_logic_signed packages.
|
||||
; StdArithNoWarnings = 1
|
||||
|
||||
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
|
||||
; NumericStdNoWarnings = 1
|
||||
|
||||
; Control the format of the (VHDL) FOR generate statement label
|
||||
; for each iteration. Do not quote it.
|
||||
; The format string here must contain the conversion codes %s and %d,
|
||||
; in that order, and no other conversion codes. The %s represents
|
||||
; the generate_label; the %d represents the generate parameter value
|
||||
; at a particular generate iteration (this is the position number if
|
||||
; the generate parameter is of an enumeration type). Embedded whitespace
|
||||
; is allowed (but discouraged); leading and trailing whitespace is ignored.
|
||||
; Application of the format must result in a unique scope name over all
|
||||
; such names in the design so that name lookup can function properly.
|
||||
; GenerateFormat = %s__%d
|
||||
|
||||
; Specify whether checkpoint files should be compressed.
|
||||
; The default is 1 (compressed).
|
||||
; CheckpointCompressMode = 0
|
||||
|
||||
; List of dynamically loaded objects for Verilog PLI applications
|
||||
; Veriuser = veriuser.sl
|
||||
|
||||
; Specify default options for the restart command. Options can be one
|
||||
; or more of: -force -nobreakpoint -nolist -nolog -nowave
|
||||
; DefaultRestartOptions = -force
|
||||
|
||||
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
|
||||
; (> 500 megabyte memory footprint). Default is disabled.
|
||||
; Specify number of megabytes to lock.
|
||||
; LockedMemory = 1000
|
||||
|
||||
; Turn on (1) or off (0) WLF file compression.
|
||||
; The default is 1 (compress WLF file).
|
||||
; WLFCompress = 0
|
||||
|
||||
; Specify whether to save all design hierarchy (1) in the WLF file
|
||||
; or only regions containing logged signals (0).
|
||||
; The default is 0 (save only regions with logged signals).
|
||||
; WLFSaveAllRegions = 1
|
||||
|
||||
; WLF file time limit. Limit WLF file by time, as closely as possible,
|
||||
; to the specified amount of simulation time. When the limit is exceeded
|
||||
; the earliest times get truncated from the file.
|
||||
; If both time and size limits are specified the most restrictive is used.
|
||||
; UserTimeUnits are used if time units are not specified.
|
||||
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
|
||||
; WLFTimeLimit = 0
|
||||
|
||||
; WLF file size limit. Limit WLF file size, as closely as possible,
|
||||
; to the specified number of megabytes. If both time and size limits
|
||||
; are specified then the most restrictive is used.
|
||||
; The default is 0 (no limit).
|
||||
; WLFSizeLimit = 1000
|
||||
|
||||
; Specify whether or not a WLF file should be deleted when the
|
||||
; simulation ends. A value of 1 will cause the WLF file to be deleted.
|
||||
; The default is 0 (do not delete WLF file when simulation ends).
|
||||
; WLFDeleteOnQuit = 1
|
||||
|
||||
; Automatic SDF compilation
|
||||
; Disables automatic compilation of SDF files in flows that support it.
|
||||
; Default is on, uncomment to turn off.
|
||||
; NoAutoSDFCompile = 1
|
||||
|
||||
[lmc]
|
||||
|
||||
[msg_system]
|
||||
; Change a message severity or suppress a message.
|
||||
; The format is: <msg directive> = <msg number>[,<msg number>...]
|
||||
; Examples:
|
||||
; note = 3009
|
||||
; warning = 3033
|
||||
; error = 3010,3016
|
||||
; fatal = 3016,3033
|
||||
; suppress = 3009,3016,3043
|
||||
; The command verror <msg number> can be used to get the complete
|
||||
; description of a message.
|
||||
|
||||
; Control transcripting of elaboration/runtime messages.
|
||||
; The default is to have messages appear in the transcript and
|
||||
; recorded in the wlf file (messages that are recorded in the
|
||||
; wlf file can be viewed in the MsgViewer). The other settings
|
||||
; are to send messages only to the transcript or only to the
|
||||
; wlf file. The valid values are
|
||||
; both {default}
|
||||
; tran {transcript only}
|
||||
; wlf {wlf file only}
|
||||
; msgmode = both
|
||||
[Project]
|
||||
; Warning -- Do not edit the project properties directly.
|
||||
; Property names are dynamic in nature and property
|
||||
; values have special syntax. Changing property data directly
|
||||
; can result in a corrupt MPF file. All project properties
|
||||
; can be modified through project window dialogs.
|
||||
Project_Version = 6
|
||||
Project_DefaultLib = work
|
||||
Project_SortMethod = unused
|
||||
Project_Files_Count = 45
|
||||
Project_File_0 = $ROOT/cpu/alu/alu.v
|
||||
Project_File_P_0 = compile_order 0 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_1 = $ROOT/cpu/alu/alu_bit_select.v
|
||||
Project_File_P_1 = compile_order 1 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_2 = $ROOT/cpu/alu/alu_control.v
|
||||
Project_File_P_2 = compile_order 2 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_3 = $ROOT/cpu/alu/alu_core.v
|
||||
Project_File_P_3 = compile_order 3 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_4 = $ROOT/cpu/alu/alu_flags.v
|
||||
Project_File_P_4 = compile_order 4 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_5 = $ROOT/cpu/alu/alu_mux_2.v
|
||||
Project_File_P_5 = compile_order 40 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_6 = $ROOT/cpu/alu/alu_mux_2z.v
|
||||
Project_File_P_6 = compile_order 5 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_7 = $ROOT/cpu/alu/alu_mux_3z.v
|
||||
Project_File_P_7 = compile_order 6 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_8 = $ROOT/cpu/alu/alu_mux_4.v
|
||||
Project_File_P_8 = compile_order 7 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_9 = $ROOT/cpu/alu/alu_mux_8.v
|
||||
Project_File_P_9 = compile_order 8 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_10 = $ROOT/cpu/alu/alu_prep_daa.v
|
||||
Project_File_P_10 = compile_order 9 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_11 = $ROOT/cpu/alu/alu_select.v
|
||||
Project_File_P_11 = compile_order 26 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_12 = $ROOT/cpu/alu/alu_shifter_core.v
|
||||
Project_File_P_12 = compile_order 10 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_13 = $ROOT/cpu/alu/alu_slice.v
|
||||
Project_File_P_13 = compile_order 11 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_14 = $ROOT/cpu/bus/address_latch.v
|
||||
Project_File_P_14 = compile_order 12 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_15 = $ROOT/cpu/bus/address_mux.v
|
||||
Project_File_P_15 = compile_order 39 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_16 = $ROOT/cpu/bus/address_pins.v
|
||||
Project_File_P_16 = compile_order 13 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_17 = $ROOT/cpu/bus/bus_control.v
|
||||
Project_File_P_17 = compile_order 32 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_18 = $ROOT/cpu/bus/bus_switch.v
|
||||
Project_File_P_18 = compile_order 30 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_19 = $ROOT/cpu/bus/control_pins_n.v
|
||||
Project_File_P_19 = compile_order 42 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_20 = $ROOT/cpu/bus/data_pins.v
|
||||
Project_File_P_20 = compile_order 14 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_21 = $ROOT/cpu/bus/data_switch.v
|
||||
Project_File_P_21 = compile_order 15 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_22 = $ROOT/cpu/bus/data_switch_mask.v
|
||||
Project_File_P_22 = compile_order 34 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_23 = $ROOT/cpu/bus/inc_dec.v
|
||||
Project_File_P_23 = compile_order 16 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_24 = $ROOT/cpu/bus/inc_dec_2bit.v
|
||||
Project_File_P_24 = compile_order 17 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_25 = $ROOT/cpu/control/clk_delay.v
|
||||
Project_File_P_25 = compile_order 28 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_26 = $ROOT/cpu/control/decode_state.v
|
||||
Project_File_P_26 = compile_order 29 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_27 = $ROOT/cpu/control/execute.v
|
||||
Project_File_P_27 = compile_order 18 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options +incdir+../../../control vlog_protect 0 vlog_showsource 1 vlog_upper 0 voptflow 1
|
||||
Project_File_28 = $ROOT/cpu/control/interrupts.v
|
||||
Project_File_P_28 = compile_order 27 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_29 = $ROOT/cpu/control/ir.v
|
||||
Project_File_P_29 = compile_order 19 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_30 = $ROOT/cpu/control/memory_ifc.v
|
||||
Project_File_P_30 = compile_order 41 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_31 = $ROOT/cpu/control/pin_control.v
|
||||
Project_File_P_31 = compile_order 43 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_32 = $ROOT/cpu/control/pla_decode.v
|
||||
Project_File_P_32 = compile_order 20 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_33 = $ROOT/cpu/control/resets.v
|
||||
Project_File_P_33 = compile_order 37 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_34 = $ROOT/cpu/control/sequencer.v
|
||||
Project_File_P_34 = compile_order 21 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_35 = $ROOT/cpu/registers/reg_control.v
|
||||
Project_File_P_35 = compile_order 22 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder registers group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_36 = $ROOT/cpu/registers/reg_file.v
|
||||
Project_File_P_36 = compile_order 23 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder registers group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_37 = $ROOT/cpu/registers/reg_latch.v
|
||||
Project_File_P_37 = compile_order 24 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder registers group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_38 = $ROOT/cpu/toplevel/tb_io.sv
|
||||
Project_File_P_38 = compile_order 35 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder toplevel group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_39 = $ROOT/cpu/toplevel/tb_iorq.sv
|
||||
Project_File_P_39 = compile_order 36 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder toplevel group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_40 = $ROOT/cpu/toplevel/tb_ram.sv
|
||||
Project_File_P_40 = compile_order 31 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder toplevel group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_41 = $ROOT/cpu/toplevel/test_fuse.sv
|
||||
Project_File_P_41 = compile_order 33 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder toplevel group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options +incdir+../../../toplevel vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_42 = $ROOT/cpu/toplevel/test_top.sv
|
||||
Project_File_P_42 = compile_order 25 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder toplevel group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options +incdir+../../../toplevel vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_43 = $ROOT/cpu/toplevel/z80.svh
|
||||
Project_File_P_43 = compile_order -1 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 1 file_type systemverilog folder toplevel group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_44 = $ROOT/cpu/toplevel/z80_top_ifc_n.sv
|
||||
Project_File_P_44 = compile_order 38 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder toplevel group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options +incdir+../../ vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_Sim_Count = 2
|
||||
Project_Sim_0 = test_top
|
||||
Project_Sim_P_0 = timing default -t default -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {Top Level} +pulse_e {} additional_dus work.test_top -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}
|
||||
Project_Sim_1 = test_fuse
|
||||
Project_Sim_P_1 = timing default -t default -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {Top Level} +pulse_e {} additional_dus work.test_fuse -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}
|
||||
Project_Folder_Count = 5
|
||||
Project_Folder_0 = registers
|
||||
Project_Folder_P_0 = folder {Top Level}
|
||||
Project_Folder_1 = control
|
||||
Project_Folder_P_1 = folder {Top Level}
|
||||
Project_Folder_2 = alu
|
||||
Project_Folder_P_2 = folder {Top Level}
|
||||
Project_Folder_3 = bus
|
||||
Project_Folder_P_3 = folder {Top Level}
|
||||
Project_Folder_4 = toplevel
|
||||
Project_Folder_P_4 = folder {Top Level}
|
||||
Echo_Compile_Output = 0
|
||||
Save_Compile_Report = 1
|
||||
Project_Opt_Count = 0
|
||||
ForceSoftPaths = 1
|
||||
ProjectStatusDelay = 5000
|
||||
VERILOG_DoubleClick = Edit
|
||||
VERILOG_CustomDoubleClick =
|
||||
SYSTEMVERILOG_DoubleClick = Compile
|
||||
SYSTEMVERILOG_CustomDoubleClick =
|
||||
VHDL_DoubleClick = Edit
|
||||
VHDL_CustomDoubleClick =
|
||||
PSL_DoubleClick = Edit
|
||||
PSL_CustomDoubleClick =
|
||||
TEXT_DoubleClick = Edit
|
||||
TEXT_CustomDoubleClick =
|
||||
SYSTEMC_DoubleClick = Edit
|
||||
SYSTEMC_CustomDoubleClick =
|
||||
TCL_DoubleClick = Edit
|
||||
TCL_CustomDoubleClick =
|
||||
MACRO_DoubleClick = Edit
|
||||
MACRO_CustomDoubleClick =
|
||||
VCD_DoubleClick = Edit
|
||||
VCD_CustomDoubleClick =
|
||||
SDF_DoubleClick = Edit
|
||||
SDF_CustomDoubleClick =
|
||||
XML_DoubleClick = Edit
|
||||
XML_CustomDoubleClick =
|
||||
LOGFILE_DoubleClick = Edit
|
||||
LOGFILE_CustomDoubleClick =
|
||||
UCDB_DoubleClick = Edit
|
||||
UCDB_CustomDoubleClick =
|
||||
UPF_DoubleClick = Edit
|
||||
UPF_CustomDoubleClick =
|
||||
PCF_DoubleClick = Edit
|
||||
PCF_CustomDoubleClick =
|
||||
PROJECT_DoubleClick = Edit
|
||||
PROJECT_CustomDoubleClick =
|
||||
VRM_DoubleClick = Edit
|
||||
VRM_CustomDoubleClick =
|
||||
DEBUGDATABASE_DoubleClick = Edit
|
||||
DEBUGDATABASE_CustomDoubleClick =
|
||||
DEBUGARCHIVE_DoubleClick = Edit
|
||||
DEBUGARCHIVE_CustomDoubleClick =
|
||||
Project_Major_Version = 10
|
||||
Project_Minor_Version = 1
|
||||
@@ -0,0 +1,438 @@
|
||||
onerror {resume}
|
||||
quietly virtual function -install /test_fuse/dut/alu_ -env /test_fuse { &{/test_fuse/dut/alu_/op1_high, /test_fuse/dut/alu_/op1_low }} OP1
|
||||
quietly virtual function -install /test_fuse/dut/alu_ -env /test_fuse { &{/test_fuse/dut/alu_/op2_high, /test_fuse/dut/alu_/op2_low }} OP2
|
||||
quietly virtual function -install /test_fuse/dut/alu_ -env /test_fuse { &{/test_fuse/dut/alu_/result_hi, /test_fuse/dut/alu_/result_lo }} RESULT
|
||||
quietly virtual function -install /test_fuse/dut/reg_file_ -env /test_fuse/dut/reg_file_/b2v_latch_af_lo { &{/test_fuse/dut/reg_file_/b2v_latch_af_hi/latch, /test_fuse/dut/reg_file_/b2v_latch_af_lo/latch }} AF
|
||||
quietly virtual function -install /test_fuse/dut/reg_file_ -env /test_fuse/dut/reg_file_/b2v_latch_pc_lo { &{/test_fuse/dut/reg_file_/b2v_latch_pc_hi/latch, /test_fuse/dut/reg_file_/b2v_latch_pc_lo/latch }} PC
|
||||
quietly virtual function -install /test_fuse/dut/reg_file_ -env /test_fuse/dut/reg_file_/b2v_latch_ir_lo { &{/test_fuse/dut/reg_file_/b2v_latch_ir_hi/latch, /test_fuse/dut/reg_file_/b2v_latch_ir_lo/latch }} IR
|
||||
quietly virtual function -install /test_fuse/dut/reg_file_ -env /test_fuse/dut/reg_file_/b2v_latch_bc_lo { &{/test_fuse/dut/reg_file_/b2v_latch_bc_hi/latch, /test_fuse/dut/reg_file_/b2v_latch_bc_lo/latch }} BC
|
||||
quietly virtual function -install /test_fuse/dut/reg_file_ -env /test_fuse/dut/reg_file_/b2v_latch_de_lo { &{/test_fuse/dut/reg_file_/b2v_latch_de_hi/latch, /test_fuse/dut/reg_file_/b2v_latch_de_lo/latch }} DE
|
||||
quietly virtual function -install /test_fuse/dut/reg_file_ -env /test_fuse/dut/reg_file_/b2v_latch_hl_lo { &{/test_fuse/dut/reg_file_/b2v_latch_hl_hi/latch, /test_fuse/dut/reg_file_/b2v_latch_hl_lo/latch }} HL
|
||||
quietly virtual function -install /test_fuse/dut/reg_file_ -env /test_fuse/dut/reg_file_/b2v_latch_sp_lo { &{/test_fuse/dut/reg_file_/b2v_latch_sp_hi/latch, /test_fuse/dut/reg_file_/b2v_latch_sp_lo/latch }} SP
|
||||
quietly virtual function -install /test_fuse/dut/reg_file_ -env /test_fuse/dut/reg_file_/b2v_latch_wz_lo { &{/test_fuse/dut/reg_file_/b2v_latch_wz_hi/latch, /test_fuse/dut/reg_file_/b2v_latch_wz_lo/latch }} WZ
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -expand -group {pads
|
||||
} /test_fuse/z80/CLK
|
||||
add wave -noupdate -expand -group {pads
|
||||
} /test_fuse/z80/nM1
|
||||
add wave -noupdate -expand -group {pads
|
||||
} -color Gray90 /test_fuse/z80/nMREQ
|
||||
add wave -noupdate -expand -group {pads
|
||||
} /test_fuse/z80/nIORQ
|
||||
add wave -noupdate -expand -group {pads
|
||||
} /test_fuse/z80/nRD
|
||||
add wave -noupdate -expand -group {pads
|
||||
} /test_fuse/z80/nWR
|
||||
add wave -noupdate -expand -group {pads
|
||||
} /test_fuse/z80/nRFSH
|
||||
add wave -noupdate -expand -group {pads
|
||||
} /test_fuse/z80/nBUSRQ
|
||||
add wave -noupdate -expand -group {pads
|
||||
} /test_fuse/z80/nBUSACK
|
||||
add wave -noupdate -expand -group {pads
|
||||
} /test_fuse/z80/nHALT
|
||||
add wave -noupdate -expand -group {pads
|
||||
} /test_fuse/z80/nWAIT
|
||||
add wave -noupdate -expand -group {pads
|
||||
} /test_fuse/z80/nINT
|
||||
add wave -noupdate -expand -group {pads
|
||||
} /test_fuse/z80/nNMI
|
||||
add wave -noupdate -expand -group {pads
|
||||
} -radix hexadecimal /test_fuse/z80/A
|
||||
add wave -noupdate -expand -group {pads
|
||||
} -radix hexadecimal -childformat {{{/test_fuse/z80/D[7]} -radix hexadecimal} {{/test_fuse/z80/D[6]} -radix hexadecimal} {{/test_fuse/z80/D[5]} -radix hexadecimal} {{/test_fuse/z80/D[4]} -radix hexadecimal} {{/test_fuse/z80/D[3]} -radix hexadecimal} {{/test_fuse/z80/D[2]} -radix hexadecimal} {{/test_fuse/z80/D[1]} -radix hexadecimal} {{/test_fuse/z80/D[0]} -radix hexadecimal}} -subitemconfig {{/test_fuse/z80/D[7]} {-height 15 -radix hexadecimal} {/test_fuse/z80/D[6]} {-height 15 -radix hexadecimal} {/test_fuse/z80/D[5]} {-height 15 -radix hexadecimal} {/test_fuse/z80/D[4]} {-height 15 -radix hexadecimal} {/test_fuse/z80/D[3]} {-height 15 -radix hexadecimal} {/test_fuse/z80/D[2]} {-height 15 -radix hexadecimal} {/test_fuse/z80/D[1]} {-height 15 -radix hexadecimal} {/test_fuse/z80/D[0]} {-height 15 -radix hexadecimal}} /test_fuse/z80/D
|
||||
add wave -noupdate -group sequencer /test_fuse/dut/sequencer_/nextM
|
||||
add wave -noupdate -group sequencer /test_fuse/dut/sequencer_/setM1
|
||||
add wave -noupdate -group sequencer -group internal /test_fuse/dut/sequencer_/hold_clk_iorq
|
||||
add wave -noupdate -group sequencer -group internal /test_fuse/dut/sequencer_/hold_clk_wait
|
||||
add wave -noupdate -group sequencer -group internal /test_fuse/dut/sequencer_/hold_clk_busrq
|
||||
add wave -noupdate -group sequencer -group internal /test_fuse/dut/sequencer_/ena_M
|
||||
add wave -noupdate -group sequencer -group internal /test_fuse/dut/sequencer_/ena_T
|
||||
add wave -noupdate -group sequencer -expand -group function /test_fuse/dut/pin_control_/fFetch
|
||||
add wave -noupdate -group sequencer -expand -group function /test_fuse/dut/pin_control_/fMRead
|
||||
add wave -noupdate -group sequencer -expand -group function /test_fuse/dut/pin_control_/fMWrite
|
||||
add wave -noupdate -group sequencer -expand -group function /test_fuse/dut/pin_control_/fIORead
|
||||
add wave -noupdate -group sequencer -expand -group function /test_fuse/dut/pin_control_/fIOWrite
|
||||
add wave -noupdate -group sequencer -expand -group M /test_fuse/dut/sequencer_/M1
|
||||
add wave -noupdate -group sequencer -expand -group M /test_fuse/dut/sequencer_/M2
|
||||
add wave -noupdate -group sequencer -expand -group M /test_fuse/dut/sequencer_/M3
|
||||
add wave -noupdate -group sequencer -expand -group M /test_fuse/dut/sequencer_/M4
|
||||
add wave -noupdate -group sequencer -expand -group M /test_fuse/dut/sequencer_/M5
|
||||
add wave -noupdate -group sequencer -expand -group T /test_fuse/dut/sequencer_/T1
|
||||
add wave -noupdate -group sequencer -expand -group T /test_fuse/dut/sequencer_/T2
|
||||
add wave -noupdate -group sequencer -expand -group T /test_fuse/dut/sequencer_/T3
|
||||
add wave -noupdate -group sequencer -expand -group T /test_fuse/dut/sequencer_/T4
|
||||
add wave -noupdate -group sequencer -expand -group T /test_fuse/dut/sequencer_/T5
|
||||
add wave -noupdate -group sequencer -expand -group T /test_fuse/dut/sequencer_/T6
|
||||
add wave -noupdate -group opcode /test_fuse/dut/ir_/ctl_ir_we
|
||||
add wave -noupdate -group opcode /test_fuse/dut/ir_/opcode
|
||||
add wave -noupdate -group db -radix hexadecimal /test_fuse/dut/db0
|
||||
add wave -noupdate -group db -radix hexadecimal /test_fuse/dut/db1
|
||||
add wave -noupdate -group db -radix hexadecimal /test_fuse/dut/db2
|
||||
add wave -noupdate -group {bus control} /test_fuse/dut/bus_control_/ctl_bus_ff_oe
|
||||
add wave -noupdate -group {bus control} /test_fuse/dut/bus_control_/ctl_bus_zero_oe
|
||||
add wave -noupdate -group {bus control} /test_fuse/dut/pin_control_/bus_ab_pin_we
|
||||
add wave -noupdate -group {bus control} /test_fuse/dut/pin_control_/bus_db_pin_oe
|
||||
add wave -noupdate -group {bus control} /test_fuse/dut/pin_control_/bus_db_pin_re
|
||||
add wave -noupdate -group {bus control} /test_fuse/dut/fpga_reset
|
||||
add wave -noupdate -group {bus control} /test_fuse/dut/nreset
|
||||
add wave -noupdate -group {bus control} /test_fuse/dut/control_pins_/in_halt
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/ctl_reg_exx
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/ctl_reg_ex_af
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/ctl_reg_ex_de_hl
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/ctl_reg_use_sp
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/nreset
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/ctl_reg_sel_pc
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/ctl_reg_sel_ir
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/ctl_reg_sel_wz
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/ctl_reg_gp_we
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/ctl_reg_not_pc
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/use_ixiy
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/use_ix
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/ctl_reg_sys_we_lo
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/ctl_reg_sys_we_hi
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/ctl_reg_sys_we
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/clk
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/ctl_reg_gp_hilo
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/ctl_reg_gp_sel
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/ctl_reg_sys_hilo
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_bc
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_bc2
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_ix
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_iy
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_de
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_hl
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_de2
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_hl2
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_af
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_af2
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_wz
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_pc
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_ir
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_sp
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_gp_hi
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_gp_lo
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_sys_lo
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_sys_hi
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_gp_we
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sys_we_lo
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sys_we_hi
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/bank_af
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/bank_exx
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/bank_hl_de1
|
||||
add wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/bank_hl_de2
|
||||
add wave -noupdate -group regfile /test_fuse/dut/reg_file_/AF
|
||||
add wave -noupdate -group regfile /test_fuse/dut/reg_file_/BC
|
||||
add wave -noupdate -group regfile /test_fuse/dut/reg_file_/DE
|
||||
add wave -noupdate -group regfile /test_fuse/dut/reg_file_/HL
|
||||
add wave -noupdate -group regfile /test_fuse/dut/reg_file_/SP
|
||||
add wave -noupdate -group regfile /test_fuse/dut/reg_file_/WZ
|
||||
add wave -noupdate -group regfile /test_fuse/dut/reg_file_/PC
|
||||
add wave -noupdate -group regfile /test_fuse/dut/reg_file_/IR
|
||||
add wave -noupdate -group regfile -radix hexadecimal /test_fuse/dut/reg_file_/db_hi_ds
|
||||
add wave -noupdate -group regfile -radix hexadecimal /test_fuse/dut/reg_file_/db_lo_ds
|
||||
add wave -noupdate -group regfile -group selects -color Thistle /test_fuse/dut/reg_file_/reg_gp_we
|
||||
add wave -noupdate -group regfile -group selects -color Gold /test_fuse/dut/reg_file_/reg_sel_gp_lo
|
||||
add wave -noupdate -group regfile -group selects -color Gold /test_fuse/dut/reg_file_/reg_sel_gp_hi
|
||||
add wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_sp
|
||||
add wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_iy
|
||||
add wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_ix
|
||||
add wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_hl2
|
||||
add wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_hl
|
||||
add wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_de2
|
||||
add wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_de
|
||||
add wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_bc2
|
||||
add wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_bc
|
||||
add wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_af2
|
||||
add wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_af
|
||||
add wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sys_we_lo
|
||||
add wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sys_we_hi
|
||||
add wave -noupdate -group regfile -group selects -color Gold /test_fuse/dut/reg_file_/reg_sel_sys_lo
|
||||
add wave -noupdate -group regfile -group selects -color Gold /test_fuse/dut/reg_file_/reg_sel_sys_hi
|
||||
add wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_wz
|
||||
add wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_ir
|
||||
add wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_pc
|
||||
add wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sw_4d_lo
|
||||
add wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sw_4d_hi
|
||||
add wave -noupdate -group regfile -radix hexadecimal /test_fuse/dut/reg_file_/db_hi_as
|
||||
add wave -noupdate -group regfile -radix hexadecimal -childformat {{{/test_fuse/dut/reg_file_/db_lo_as[7]} -radix hexadecimal} {{/test_fuse/dut/reg_file_/db_lo_as[6]} -radix hexadecimal} {{/test_fuse/dut/reg_file_/db_lo_as[5]} -radix hexadecimal} {{/test_fuse/dut/reg_file_/db_lo_as[4]} -radix hexadecimal} {{/test_fuse/dut/reg_file_/db_lo_as[3]} -radix hexadecimal} {{/test_fuse/dut/reg_file_/db_lo_as[2]} -radix hexadecimal} {{/test_fuse/dut/reg_file_/db_lo_as[1]} -radix hexadecimal} {{/test_fuse/dut/reg_file_/db_lo_as[0]} -radix hexadecimal}} -subitemconfig {{/test_fuse/dut/reg_file_/db_lo_as[7]} {-height 15 -radix hexadecimal} {/test_fuse/dut/reg_file_/db_lo_as[6]} {-height 15 -radix hexadecimal} {/test_fuse/dut/reg_file_/db_lo_as[5]} {-height 15 -radix hexadecimal} {/test_fuse/dut/reg_file_/db_lo_as[4]} {-height 15 -radix hexadecimal} {/test_fuse/dut/reg_file_/db_lo_as[3]} {-height 15 -radix hexadecimal} {/test_fuse/dut/reg_file_/db_lo_as[2]} {-height 15 -radix hexadecimal} {/test_fuse/dut/reg_file_/db_lo_as[1]} {-height 15 -radix hexadecimal} {/test_fuse/dut/reg_file_/db_lo_as[0]} {-height 15 -radix hexadecimal}} /test_fuse/dut/reg_file_/db_lo_as
|
||||
add wave -noupdate -group switch /test_fuse/dut/bus_switch_/ctl_sw_mask543_en
|
||||
add wave -noupdate -group switch /test_fuse/dut/bus_switch_/ctl_sw_1u
|
||||
add wave -noupdate -group switch /test_fuse/dut/bus_switch_/ctl_sw_1d
|
||||
add wave -noupdate -group switch /test_fuse/dut/bus_switch_/ctl_sw_2u
|
||||
add wave -noupdate -group switch /test_fuse/dut/bus_switch_/ctl_sw_2d
|
||||
add wave -noupdate -group switch /test_fuse/dut/reg_control_/ctl_sw_4d
|
||||
add wave -noupdate -group switch -color Aquamarine /test_fuse/dut/reg_file_/ctl_sw_4u
|
||||
add wave -noupdate -group {data pins} /test_fuse/dut/data_pins_/bus_db_pin_oe
|
||||
add wave -noupdate -group {data pins} /test_fuse/dut/data_pins_/bus_db_pin_re
|
||||
add wave -noupdate -group {data pins} /test_fuse/dut/data_pins_/ctl_bus_db_we
|
||||
add wave -noupdate -group {data pins} /test_fuse/dut/data_pins_/ctl_bus_db_oe
|
||||
add wave -noupdate -group {data pins} -radix hexadecimal /test_fuse/dut/data_pins_/D
|
||||
add wave -noupdate -group {data pins} -radix hexadecimal /test_fuse/dut/data_pins_/db
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_fuse/dut/alu_control_/alu_shift_db0
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_fuse/dut/alu_control_/alu_shift_db7
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_fuse/dut/alu_control_/ctl_shift_en
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_fuse/dut/alu_control_/flags_hf
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_fuse/dut/alu_control_/ctl_alu_op_low
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_fuse/dut/alu_control_/alu_parity_out
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_fuse/dut/alu_control_/flags_zf
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_fuse/dut/alu_control_/flags_pf
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_fuse/dut/alu_control_/flags_sf
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_fuse/dut/alu_control_/ctl_cond_short
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_fuse/dut/alu_control_/alu_vf_out
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_fuse/dut/alu_control_/iff2
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_fuse/dut/alu_control_/ctl_pf_sel
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_fuse/dut/alu_control_/op543
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_fuse/dut/alu_control_/alu_shift_in
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_fuse/dut/alu_control_/alu_shift_right
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_fuse/dut/alu_control_/alu_shift_left
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_fuse/dut/alu_control_/shift_cf_out
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_fuse/dut/alu_control_/alu_parity_in
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_fuse/dut/alu_control_/flags_cond_true
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_fuse/dut/alu_control_/pf_sel
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_fuse/dut/alu_control_/alu_op_low
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_fuse/dut/alu_control_/alu_core_cf_in
|
||||
add wave -noupdate -group {alu
|
||||
control} -radix hexadecimal /test_fuse/dut/alu_control_/db
|
||||
add wave -noupdate -group {alu
|
||||
control} -radix hexadecimal /test_fuse/dut/alu_control_/out
|
||||
add wave -noupdate -group {alu
|
||||
control} -radix hexadecimal /test_fuse/dut/alu_control_/sel
|
||||
add wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/ctl_flags_oe
|
||||
add wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/ctl_flags_bus
|
||||
add wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/ctl_flags_alu
|
||||
add wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/alu_sf_out
|
||||
add wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/alu_yf_out
|
||||
add wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/alu_xf_out
|
||||
add wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/ctl_flags_nf_set
|
||||
add wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/alu_zero
|
||||
add wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/shift_cf_out
|
||||
add wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/alu_core_cf_out
|
||||
add wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/daa_cf_out
|
||||
add wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/ctl_flags_cf_set
|
||||
add wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/ctl_flags_cf_cpl
|
||||
add wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/ctl_flags_hf_cpl
|
||||
add wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/pf_sel
|
||||
add wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/ctl_flags_cf_we
|
||||
add wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/ctl_flags_sz_we
|
||||
add wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/ctl_flags_xy_we
|
||||
add wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/ctl_flags_hf_we
|
||||
add wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/ctl_flags_pf_we
|
||||
add wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/ctl_flags_nf_we
|
||||
add wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/flags_sf
|
||||
add wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/flags_zf
|
||||
add wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/flags_pf
|
||||
add wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/flags_cf
|
||||
add wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/flags_nf
|
||||
add wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_oe
|
||||
add wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_shift_oe
|
||||
add wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_op2_oe
|
||||
add wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_res_oe
|
||||
add wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_op1_oe
|
||||
add wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_bs_oe
|
||||
add wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_op1_sel_bus
|
||||
add wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_op1_sel_low
|
||||
add wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_op1_sel_zero
|
||||
add wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_op2_sel_zero
|
||||
add wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_op2_sel_bus
|
||||
add wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_op2_sel_lq
|
||||
add wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_sel_op2_neg
|
||||
add wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_sel_op2_high
|
||||
add wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_core_R
|
||||
add wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_core_V
|
||||
add wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_core_S
|
||||
add wave -noupdate -group {alu
|
||||
} -color Green -radix hexadecimal /test_fuse/dut/alu_/OP1
|
||||
add wave -noupdate -group {alu
|
||||
} -color Green -radix hexadecimal /test_fuse/dut/alu_/OP2
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/RESULT
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/alu_bs_oe
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/alu_parity_in
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/alu_oe
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/alu_shift_oe
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/alu_op2_oe
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/alu_op1_oe
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/alu_res_oe
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/alu_op1_sel_low
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/alu_op1_sel_zero
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/alu_op1_sel_bus
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/alu_op2_sel_zero
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/alu_op2_sel_bus
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/alu_op2_sel_lq
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/alu_op_low
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/alu_shift_in
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/alu_sel_op2_neg
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/alu_sel_op2_high
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/alu_shift_left
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/alu_shift_right
|
||||
add wave -noupdate -group {alu
|
||||
} -radix hexadecimal /test_fuse/dut/alu_/bsel
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/alu_zero
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/alu_parity_out
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/alu_high_eq_9
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/alu_high_gt_9
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/alu_low_gt_9
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/alu_shift_db0
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/alu_shift_db7
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/alu_sf_out
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/alu_yf_out
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/alu_xf_out
|
||||
add wave -noupdate -group {alu
|
||||
} /test_fuse/dut/alu_/alu_vf_out
|
||||
add wave -noupdate -group {alu
|
||||
} -radix hexadecimal /test_fuse/dut/alu_/db
|
||||
add wave -noupdate -group {alu
|
||||
} -radix hexadecimal /test_fuse/dut/alu_/test_db_high
|
||||
add wave -noupdate -group {alu
|
||||
} -radix hexadecimal /test_fuse/dut/alu_/test_db_low
|
||||
add wave -noupdate -group {alu
|
||||
} -color Magenta /test_fuse/dut/alu_/alu_core_R
|
||||
add wave -noupdate -group {alu
|
||||
} -color Magenta /test_fuse/dut/alu_/alu_core_V
|
||||
add wave -noupdate -group {alu
|
||||
} -color Magenta /test_fuse/dut/alu_/alu_core_S
|
||||
add wave -noupdate -group {alu
|
||||
} -color Magenta /test_fuse/dut/alu_/alu_core_cf_in
|
||||
add wave -noupdate -group {alu
|
||||
} -color Magenta -radix hexadecimal /test_fuse/dut/alu_/alu_op1
|
||||
add wave -noupdate -group {alu
|
||||
} -color Magenta -radix hexadecimal /test_fuse/dut/alu_/alu_op2
|
||||
add wave -noupdate -group {alu
|
||||
} -color Red /test_fuse/dut/alu_/alu_core_cf_out
|
||||
add wave -noupdate -group {alu
|
||||
} -radix hexadecimal /test_fuse/dut/alu_/result_hi
|
||||
add wave -noupdate -group {alu
|
||||
} -radix hexadecimal /test_fuse/dut/alu_/result_lo
|
||||
add wave -noupdate -group {alu
|
||||
} -radix hexadecimal /test_fuse/dut/alu_/db_high
|
||||
add wave -noupdate -group {alu
|
||||
} -radix hexadecimal /test_fuse/dut/alu_/db_low
|
||||
add wave -noupdate -group {alu
|
||||
} -radix hexadecimal /test_fuse/dut/alu_/op1_high
|
||||
add wave -noupdate -group {alu
|
||||
} -radix hexadecimal /test_fuse/dut/alu_/op1_low
|
||||
add wave -noupdate -group {alu
|
||||
} -radix hexadecimal /test_fuse/dut/alu_/op2_high
|
||||
add wave -noupdate -group {alu
|
||||
} -radix hexadecimal /test_fuse/dut/alu_/op2_low
|
||||
add wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/ctl_inc_cy
|
||||
add wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/ctl_inc_dec
|
||||
add wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/clrpc
|
||||
add wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/ctl_al_we
|
||||
add wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/ctl_inc_limit6
|
||||
add wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/ctl_bus_inc_oe
|
||||
add wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/address_is_1
|
||||
add wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/ctl_apin_mux
|
||||
add wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/ctl_apin_mux2
|
||||
add wave -noupdate -group {address latch} -radix hexadecimal /test_fuse/dut/address_latch_/abus
|
||||
add wave -noupdate -group {address latch} -radix hexadecimal -childformat {{{/test_fuse/dut/address_latch_/address[15]} -radix hexadecimal} {{/test_fuse/dut/address_latch_/address[14]} -radix hexadecimal} {{/test_fuse/dut/address_latch_/address[13]} -radix hexadecimal} {{/test_fuse/dut/address_latch_/address[12]} -radix hexadecimal} {{/test_fuse/dut/address_latch_/address[11]} -radix hexadecimal} {{/test_fuse/dut/address_latch_/address[10]} -radix hexadecimal} {{/test_fuse/dut/address_latch_/address[9]} -radix hexadecimal} {{/test_fuse/dut/address_latch_/address[8]} -radix hexadecimal} {{/test_fuse/dut/address_latch_/address[7]} -radix hexadecimal} {{/test_fuse/dut/address_latch_/address[6]} -radix hexadecimal} {{/test_fuse/dut/address_latch_/address[5]} -radix hexadecimal} {{/test_fuse/dut/address_latch_/address[4]} -radix hexadecimal} {{/test_fuse/dut/address_latch_/address[3]} -radix hexadecimal} {{/test_fuse/dut/address_latch_/address[2]} -radix hexadecimal} {{/test_fuse/dut/address_latch_/address[1]} -radix hexadecimal} {{/test_fuse/dut/address_latch_/address[0]} -radix hexadecimal}} -subitemconfig {{/test_fuse/dut/address_latch_/address[15]} {-height 15 -radix hexadecimal} {/test_fuse/dut/address_latch_/address[14]} {-height 15 -radix hexadecimal} {/test_fuse/dut/address_latch_/address[13]} {-height 15 -radix hexadecimal} {/test_fuse/dut/address_latch_/address[12]} {-height 15 -radix hexadecimal} {/test_fuse/dut/address_latch_/address[11]} {-height 15 -radix hexadecimal} {/test_fuse/dut/address_latch_/address[10]} {-height 15 -radix hexadecimal} {/test_fuse/dut/address_latch_/address[9]} {-height 15 -radix hexadecimal} {/test_fuse/dut/address_latch_/address[8]} {-height 15 -radix hexadecimal} {/test_fuse/dut/address_latch_/address[7]} {-height 15 -radix hexadecimal} {/test_fuse/dut/address_latch_/address[6]} {-height 15 -radix hexadecimal} {/test_fuse/dut/address_latch_/address[5]} {-height 15 -radix hexadecimal} {/test_fuse/dut/address_latch_/address[4]} {-height 15 -radix hexadecimal} {/test_fuse/dut/address_latch_/address[3]} {-height 15 -radix hexadecimal} {/test_fuse/dut/address_latch_/address[2]} {-height 15 -radix hexadecimal} {/test_fuse/dut/address_latch_/address[1]} {-height 15 -radix hexadecimal} {/test_fuse/dut/address_latch_/address[0]} {-height 15 -radix hexadecimal}} /test_fuse/dut/address_latch_/address
|
||||
add wave -noupdate -group {address pins} /test_fuse/dut/address_pins_/bus_ab_pin_we
|
||||
add wave -noupdate -group {address pins} /test_fuse/dut/address_pins_/pin_control_oe
|
||||
add wave -noupdate -group {address pins} -label apin_latch /test_fuse/dut/address_pins_/DFFE_apin_latch
|
||||
add wave -noupdate -group state /test_fuse/dut/decode_state_/ctl_state_iy_set
|
||||
add wave -noupdate -group state /test_fuse/dut/decode_state_/ctl_state_ixiy_clr
|
||||
add wave -noupdate -group state /test_fuse/dut/decode_state_/ctl_state_ixiy_we
|
||||
add wave -noupdate -group state /test_fuse/dut/decode_state_/ctl_state_halt_set
|
||||
add wave -noupdate -group state /test_fuse/dut/decode_state_/ctl_state_tbl_we
|
||||
add wave -noupdate -group state /test_fuse/dut/decode_state_/ctl_state_tbl_ed_set
|
||||
add wave -noupdate -group state /test_fuse/dut/decode_state_/ctl_state_tbl_cb_set
|
||||
add wave -noupdate -group state /test_fuse/dut/decode_state_/ctl_state_alu
|
||||
add wave -noupdate -group state /test_fuse/dut/decode_state_/address_is_1
|
||||
add wave -noupdate -group state /test_fuse/dut/decode_state_/ctl_repeat_we
|
||||
add wave -noupdate -group state /test_fuse/dut/decode_state_/in_intr
|
||||
add wave -noupdate -group state /test_fuse/dut/decode_state_/in_nmi
|
||||
add wave -noupdate -group state /test_fuse/dut/decode_state_/nreset
|
||||
add wave -noupdate -group state /test_fuse/dut/decode_state_/in_halt
|
||||
add wave -noupdate -group state /test_fuse/dut/decode_state_/table_cb
|
||||
add wave -noupdate -group state /test_fuse/dut/decode_state_/table_ed
|
||||
add wave -noupdate -group state /test_fuse/dut/decode_state_/table_xx
|
||||
add wave -noupdate -group state /test_fuse/dut/decode_state_/use_ix
|
||||
add wave -noupdate -group state /test_fuse/dut/decode_state_/use_ixiy
|
||||
add wave -noupdate -group state /test_fuse/dut/decode_state_/in_alu
|
||||
add wave -noupdate -group state /test_fuse/dut/decode_state_/repeat_en
|
||||
add wave -noupdate -group interrupts /test_fuse/dut/interrupts_/intr
|
||||
add wave -noupdate -group interrupts /test_fuse/dut/interrupts_/iff1
|
||||
add wave -noupdate -group interrupts /test_fuse/dut/interrupts_/iff2
|
||||
add wave -noupdate -group interrupts /test_fuse/dut/interrupts_/im1
|
||||
add wave -noupdate -group interrupts /test_fuse/dut/interrupts_/im2
|
||||
add wave -noupdate -group interrupts /test_fuse/dut/interrupts_/nmi
|
||||
add wave -noupdate -group interrupts /test_fuse/dut/interrupts_/ctl_iff1_iff2
|
||||
add wave -noupdate -group interrupts /test_fuse/dut/interrupts_/ctl_iffx_we
|
||||
add wave -noupdate -group interrupts /test_fuse/dut/interrupts_/ctl_iffx_bit
|
||||
add wave -noupdate -group interrupts /test_fuse/dut/interrupts_/ctl_im_we
|
||||
add wave -noupdate -group interrupts /test_fuse/dut/interrupts_/ctl_no_ints
|
||||
add wave -noupdate -group interrupts /test_fuse/dut/interrupts_/in_nmi
|
||||
add wave -noupdate -group interrupts /test_fuse/dut/interrupts_/in_intr
|
||||
add wave -noupdate -group interrupts /test_fuse/dut/interrupts_/int_armed
|
||||
add wave -noupdate -group interrupts /test_fuse/dut/interrupts_/nmi_armed
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {Cursor {3900 ns} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 163
|
||||
configure wave -valuecolwidth 53
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
configure wave -timelineunits us
|
||||
update
|
||||
WaveRestoreZoom {0 ns} {7800 ns}
|
||||
@@ -0,0 +1,438 @@
|
||||
onerror {resume}
|
||||
quietly virtual function -install /test_top/dut/alu_ -env /test_top { &{/test_top/dut/alu_/op1_high, /test_top/dut/alu_/op1_low }} OP1
|
||||
quietly virtual function -install /test_top/dut/alu_ -env /test_top { &{/test_top/dut/alu_/op2_high, /test_top/dut/alu_/op2_low }} OP2
|
||||
quietly virtual function -install /test_top/dut/alu_ -env /test_top { &{/test_top/dut/alu_/result_hi, /test_top/dut/alu_/result_lo }} RESULT
|
||||
quietly virtual function -install /test_top/dut/reg_file_ -env /test_top/dut/reg_file_/b2v_latch_af_lo { &{/test_top/dut/reg_file_/b2v_latch_af_hi/latch, /test_top/dut/reg_file_/b2v_latch_af_lo/latch }} AF
|
||||
quietly virtual function -install /test_top/dut/reg_file_ -env /test_top/dut/reg_file_/b2v_latch_pc_lo { &{/test_top/dut/reg_file_/b2v_latch_pc_hi/latch, /test_top/dut/reg_file_/b2v_latch_pc_lo/latch }} PC
|
||||
quietly virtual function -install /test_top/dut/reg_file_ -env /test_top/dut/reg_file_/b2v_latch_ir_lo { &{/test_top/dut/reg_file_/b2v_latch_ir_hi/latch, /test_top/dut/reg_file_/b2v_latch_ir_lo/latch }} IR
|
||||
quietly virtual function -install /test_top/dut/reg_file_ -env /test_top/dut/reg_file_/b2v_latch_bc_lo { &{/test_top/dut/reg_file_/b2v_latch_bc_hi/latch, /test_top/dut/reg_file_/b2v_latch_bc_lo/latch }} BC
|
||||
quietly virtual function -install /test_top/dut/reg_file_ -env /test_top/dut/reg_file_/b2v_latch_de_lo { &{/test_top/dut/reg_file_/b2v_latch_de_hi/latch, /test_top/dut/reg_file_/b2v_latch_de_lo/latch }} DE
|
||||
quietly virtual function -install /test_top/dut/reg_file_ -env /test_top/dut/reg_file_/b2v_latch_hl_lo { &{/test_top/dut/reg_file_/b2v_latch_hl_hi/latch, /test_top/dut/reg_file_/b2v_latch_hl_lo/latch }} HL
|
||||
quietly virtual function -install /test_top/dut/reg_file_ -env /test_top/dut/reg_file_/b2v_latch_sp_lo { &{/test_top/dut/reg_file_/b2v_latch_sp_hi/latch, /test_top/dut/reg_file_/b2v_latch_sp_lo/latch }} SP
|
||||
quietly virtual function -install /test_top/dut/reg_file_ -env /test_top/dut/reg_file_/b2v_latch_wz_lo { &{/test_top/dut/reg_file_/b2v_latch_wz_hi/latch, /test_top/dut/reg_file_/b2v_latch_wz_lo/latch }} WZ
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -expand -group {pads
|
||||
} /test_top/z80/CLK
|
||||
add wave -noupdate -expand -group {pads
|
||||
} /test_top/z80/nM1
|
||||
add wave -noupdate -expand -group {pads
|
||||
} -color Gray90 /test_top/z80/nMREQ
|
||||
add wave -noupdate -expand -group {pads
|
||||
} /test_top/z80/nIORQ
|
||||
add wave -noupdate -expand -group {pads
|
||||
} /test_top/z80/nRD
|
||||
add wave -noupdate -expand -group {pads
|
||||
} /test_top/z80/nWR
|
||||
add wave -noupdate -expand -group {pads
|
||||
} /test_top/z80/nRFSH
|
||||
add wave -noupdate -expand -group {pads
|
||||
} /test_top/z80/nBUSRQ
|
||||
add wave -noupdate -expand -group {pads
|
||||
} /test_top/z80/nBUSACK
|
||||
add wave -noupdate -expand -group {pads
|
||||
} /test_top/z80/nHALT
|
||||
add wave -noupdate -expand -group {pads
|
||||
} /test_top/z80/nWAIT
|
||||
add wave -noupdate -expand -group {pads
|
||||
} /test_top/z80/nINT
|
||||
add wave -noupdate -expand -group {pads
|
||||
} /test_top/z80/nNMI
|
||||
add wave -noupdate -expand -group {pads
|
||||
} -radix hexadecimal /test_top/z80/A
|
||||
add wave -noupdate -expand -group {pads
|
||||
} -radix hexadecimal -childformat {{{/test_top/z80/D[7]} -radix hexadecimal} {{/test_top/z80/D[6]} -radix hexadecimal} {{/test_top/z80/D[5]} -radix hexadecimal} {{/test_top/z80/D[4]} -radix hexadecimal} {{/test_top/z80/D[3]} -radix hexadecimal} {{/test_top/z80/D[2]} -radix hexadecimal} {{/test_top/z80/D[1]} -radix hexadecimal} {{/test_top/z80/D[0]} -radix hexadecimal}} -subitemconfig {{/test_top/z80/D[7]} {-height 15 -radix hexadecimal} {/test_top/z80/D[6]} {-height 15 -radix hexadecimal} {/test_top/z80/D[5]} {-height 15 -radix hexadecimal} {/test_top/z80/D[4]} {-height 15 -radix hexadecimal} {/test_top/z80/D[3]} {-height 15 -radix hexadecimal} {/test_top/z80/D[2]} {-height 15 -radix hexadecimal} {/test_top/z80/D[1]} {-height 15 -radix hexadecimal} {/test_top/z80/D[0]} {-height 15 -radix hexadecimal}} /test_top/z80/D
|
||||
add wave -noupdate -group sequencer /test_top/dut/sequencer_/nextM
|
||||
add wave -noupdate -group sequencer /test_top/dut/sequencer_/setM1
|
||||
add wave -noupdate -group sequencer -group internal /test_top/dut/sequencer_/hold_clk_iorq
|
||||
add wave -noupdate -group sequencer -group internal /test_top/dut/sequencer_/hold_clk_wait
|
||||
add wave -noupdate -group sequencer -group internal /test_top/dut/sequencer_/hold_clk_busrq
|
||||
add wave -noupdate -group sequencer -group internal /test_top/dut/sequencer_/ena_M
|
||||
add wave -noupdate -group sequencer -group internal /test_top/dut/sequencer_/ena_T
|
||||
add wave -noupdate -group sequencer -expand -group function /test_top/dut/pin_control_/fFetch
|
||||
add wave -noupdate -group sequencer -expand -group function /test_top/dut/pin_control_/fMRead
|
||||
add wave -noupdate -group sequencer -expand -group function /test_top/dut/pin_control_/fMWrite
|
||||
add wave -noupdate -group sequencer -expand -group function /test_top/dut/pin_control_/fIORead
|
||||
add wave -noupdate -group sequencer -expand -group function /test_top/dut/pin_control_/fIOWrite
|
||||
add wave -noupdate -group sequencer -expand -group M /test_top/dut/sequencer_/M1
|
||||
add wave -noupdate -group sequencer -expand -group M /test_top/dut/sequencer_/M2
|
||||
add wave -noupdate -group sequencer -expand -group M /test_top/dut/sequencer_/M3
|
||||
add wave -noupdate -group sequencer -expand -group M /test_top/dut/sequencer_/M4
|
||||
add wave -noupdate -group sequencer -expand -group M /test_top/dut/sequencer_/M5
|
||||
add wave -noupdate -group sequencer -expand -group T /test_top/dut/sequencer_/T1
|
||||
add wave -noupdate -group sequencer -expand -group T /test_top/dut/sequencer_/T2
|
||||
add wave -noupdate -group sequencer -expand -group T /test_top/dut/sequencer_/T3
|
||||
add wave -noupdate -group sequencer -expand -group T /test_top/dut/sequencer_/T4
|
||||
add wave -noupdate -group sequencer -expand -group T /test_top/dut/sequencer_/T5
|
||||
add wave -noupdate -group sequencer -expand -group T /test_top/dut/sequencer_/T6
|
||||
add wave -noupdate -group opcode /test_top/dut/ir_/ctl_ir_we
|
||||
add wave -noupdate -group opcode /test_top/dut/ir_/opcode
|
||||
add wave -noupdate -group db -radix hexadecimal /test_top/dut/db0
|
||||
add wave -noupdate -group db -radix hexadecimal /test_top/dut/db1
|
||||
add wave -noupdate -group db -radix hexadecimal /test_top/dut/db2
|
||||
add wave -noupdate -group {bus control} /test_top/dut/bus_control_/ctl_bus_ff_oe
|
||||
add wave -noupdate -group {bus control} /test_top/dut/bus_control_/ctl_bus_zero_oe
|
||||
add wave -noupdate -group {bus control} /test_top/dut/pin_control_/bus_ab_pin_we
|
||||
add wave -noupdate -group {bus control} /test_top/dut/pin_control_/bus_db_pin_oe
|
||||
add wave -noupdate -group {bus control} /test_top/dut/pin_control_/bus_db_pin_re
|
||||
add wave -noupdate -group {bus control} /test_top/dut/fpga_reset
|
||||
add wave -noupdate -group {bus control} /test_top/dut/nreset
|
||||
add wave -noupdate -group {bus control} /test_top/dut/control_pins_/in_halt
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/ctl_reg_exx
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/ctl_reg_ex_af
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/ctl_reg_ex_de_hl
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/ctl_reg_use_sp
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/nreset
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/ctl_reg_sel_pc
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/ctl_reg_sel_ir
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/ctl_reg_sel_wz
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/ctl_reg_gp_we
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/ctl_reg_not_pc
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/use_ixiy
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/use_ix
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/ctl_reg_sys_we_lo
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/ctl_reg_sys_we_hi
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/ctl_reg_sys_we
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/clk
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/ctl_reg_gp_hilo
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/ctl_reg_gp_sel
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/ctl_reg_sys_hilo
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_bc
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_bc2
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_ix
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_iy
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_de
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_hl
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_de2
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_hl2
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_af
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_af2
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_wz
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_pc
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_ir
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_sp
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_gp_hi
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_gp_lo
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_sys_lo
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_sys_hi
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_gp_we
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sys_we_lo
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sys_we_hi
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/bank_af
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/bank_exx
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/bank_hl_de1
|
||||
add wave -noupdate -group {reg control} /test_top/dut/reg_control_/bank_hl_de2
|
||||
add wave -noupdate -group regfile /test_top/dut/reg_file_/AF
|
||||
add wave -noupdate -group regfile /test_top/dut/reg_file_/BC
|
||||
add wave -noupdate -group regfile /test_top/dut/reg_file_/DE
|
||||
add wave -noupdate -group regfile /test_top/dut/reg_file_/HL
|
||||
add wave -noupdate -group regfile /test_top/dut/reg_file_/SP
|
||||
add wave -noupdate -group regfile /test_top/dut/reg_file_/WZ
|
||||
add wave -noupdate -group regfile /test_top/dut/reg_file_/PC
|
||||
add wave -noupdate -group regfile /test_top/dut/reg_file_/IR
|
||||
add wave -noupdate -group regfile -radix hexadecimal /test_top/dut/reg_file_/db_hi_ds
|
||||
add wave -noupdate -group regfile -radix hexadecimal /test_top/dut/reg_file_/db_lo_ds
|
||||
add wave -noupdate -group regfile -group selects -color Thistle /test_top/dut/reg_file_/reg_gp_we
|
||||
add wave -noupdate -group regfile -group selects -color Gold /test_top/dut/reg_file_/reg_sel_gp_lo
|
||||
add wave -noupdate -group regfile -group selects -color Gold /test_top/dut/reg_file_/reg_sel_gp_hi
|
||||
add wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_sp
|
||||
add wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_iy
|
||||
add wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_ix
|
||||
add wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_hl2
|
||||
add wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_hl
|
||||
add wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_de2
|
||||
add wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_de
|
||||
add wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_bc2
|
||||
add wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_bc
|
||||
add wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_af2
|
||||
add wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_af
|
||||
add wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sys_we_lo
|
||||
add wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sys_we_hi
|
||||
add wave -noupdate -group regfile -group selects -color Gold /test_top/dut/reg_file_/reg_sel_sys_lo
|
||||
add wave -noupdate -group regfile -group selects -color Gold /test_top/dut/reg_file_/reg_sel_sys_hi
|
||||
add wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_wz
|
||||
add wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_ir
|
||||
add wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_pc
|
||||
add wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sw_4d_lo
|
||||
add wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sw_4d_hi
|
||||
add wave -noupdate -group regfile -radix hexadecimal /test_top/dut/reg_file_/db_hi_as
|
||||
add wave -noupdate -group regfile -radix hexadecimal -childformat {{{/test_top/dut/reg_file_/db_lo_as[7]} -radix hexadecimal} {{/test_top/dut/reg_file_/db_lo_as[6]} -radix hexadecimal} {{/test_top/dut/reg_file_/db_lo_as[5]} -radix hexadecimal} {{/test_top/dut/reg_file_/db_lo_as[4]} -radix hexadecimal} {{/test_top/dut/reg_file_/db_lo_as[3]} -radix hexadecimal} {{/test_top/dut/reg_file_/db_lo_as[2]} -radix hexadecimal} {{/test_top/dut/reg_file_/db_lo_as[1]} -radix hexadecimal} {{/test_top/dut/reg_file_/db_lo_as[0]} -radix hexadecimal}} -subitemconfig {{/test_top/dut/reg_file_/db_lo_as[7]} {-height 15 -radix hexadecimal} {/test_top/dut/reg_file_/db_lo_as[6]} {-height 15 -radix hexadecimal} {/test_top/dut/reg_file_/db_lo_as[5]} {-height 15 -radix hexadecimal} {/test_top/dut/reg_file_/db_lo_as[4]} {-height 15 -radix hexadecimal} {/test_top/dut/reg_file_/db_lo_as[3]} {-height 15 -radix hexadecimal} {/test_top/dut/reg_file_/db_lo_as[2]} {-height 15 -radix hexadecimal} {/test_top/dut/reg_file_/db_lo_as[1]} {-height 15 -radix hexadecimal} {/test_top/dut/reg_file_/db_lo_as[0]} {-height 15 -radix hexadecimal}} /test_top/dut/reg_file_/db_lo_as
|
||||
add wave -noupdate -group switch /test_top/dut/bus_switch_/ctl_sw_mask543_en
|
||||
add wave -noupdate -group switch /test_top/dut/bus_switch_/ctl_sw_1u
|
||||
add wave -noupdate -group switch /test_top/dut/bus_switch_/ctl_sw_1d
|
||||
add wave -noupdate -group switch /test_top/dut/bus_switch_/ctl_sw_2u
|
||||
add wave -noupdate -group switch /test_top/dut/bus_switch_/ctl_sw_2d
|
||||
add wave -noupdate -group switch /test_top/dut/reg_control_/ctl_sw_4d
|
||||
add wave -noupdate -group switch -color Aquamarine /test_top/dut/reg_file_/ctl_sw_4u
|
||||
add wave -noupdate -group {data pins} /test_top/dut/data_pins_/bus_db_pin_oe
|
||||
add wave -noupdate -group {data pins} /test_top/dut/data_pins_/bus_db_pin_re
|
||||
add wave -noupdate -group {data pins} /test_top/dut/data_pins_/ctl_bus_db_we
|
||||
add wave -noupdate -group {data pins} /test_top/dut/data_pins_/ctl_bus_db_oe
|
||||
add wave -noupdate -group {data pins} -radix hexadecimal /test_top/dut/data_pins_/D
|
||||
add wave -noupdate -group {data pins} -radix hexadecimal /test_top/dut/data_pins_/db
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_top/dut/alu_control_/alu_shift_db0
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_top/dut/alu_control_/alu_shift_db7
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_top/dut/alu_control_/ctl_shift_en
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_top/dut/alu_control_/flags_hf
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_top/dut/alu_control_/ctl_alu_op_low
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_top/dut/alu_control_/alu_parity_out
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_top/dut/alu_control_/flags_zf
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_top/dut/alu_control_/flags_pf
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_top/dut/alu_control_/flags_sf
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_top/dut/alu_control_/ctl_cond_short
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_top/dut/alu_control_/alu_vf_out
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_top/dut/alu_control_/iff2
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_top/dut/alu_control_/ctl_pf_sel
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_top/dut/alu_control_/op543
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_top/dut/alu_control_/alu_shift_in
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_top/dut/alu_control_/alu_shift_right
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_top/dut/alu_control_/alu_shift_left
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_top/dut/alu_control_/shift_cf_out
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_top/dut/alu_control_/alu_parity_in
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_top/dut/alu_control_/flags_cond_true
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_top/dut/alu_control_/pf_sel
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_top/dut/alu_control_/alu_op_low
|
||||
add wave -noupdate -group {alu
|
||||
control} /test_top/dut/alu_control_/alu_core_cf_in
|
||||
add wave -noupdate -group {alu
|
||||
control} -radix hexadecimal /test_top/dut/alu_control_/db
|
||||
add wave -noupdate -group {alu
|
||||
control} -radix hexadecimal /test_top/dut/alu_control_/out
|
||||
add wave -noupdate -group {alu
|
||||
control} -radix hexadecimal /test_top/dut/alu_control_/sel
|
||||
add wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/ctl_flags_oe
|
||||
add wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/ctl_flags_bus
|
||||
add wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/ctl_flags_alu
|
||||
add wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/alu_sf_out
|
||||
add wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/alu_yf_out
|
||||
add wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/alu_xf_out
|
||||
add wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/ctl_flags_nf_set
|
||||
add wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/alu_zero
|
||||
add wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/shift_cf_out
|
||||
add wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/alu_core_cf_out
|
||||
add wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/daa_cf_out
|
||||
add wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/ctl_flags_cf_set
|
||||
add wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/ctl_flags_cf_cpl
|
||||
add wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/ctl_flags_hf_cpl
|
||||
add wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/pf_sel
|
||||
add wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/ctl_flags_cf_we
|
||||
add wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/ctl_flags_sz_we
|
||||
add wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/ctl_flags_xy_we
|
||||
add wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/ctl_flags_hf_we
|
||||
add wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/ctl_flags_pf_we
|
||||
add wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/ctl_flags_nf_we
|
||||
add wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/flags_sf
|
||||
add wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/flags_zf
|
||||
add wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/flags_pf
|
||||
add wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/flags_cf
|
||||
add wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/flags_nf
|
||||
add wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_oe
|
||||
add wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_shift_oe
|
||||
add wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_op2_oe
|
||||
add wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_res_oe
|
||||
add wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_op1_oe
|
||||
add wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_bs_oe
|
||||
add wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_op1_sel_bus
|
||||
add wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_op1_sel_low
|
||||
add wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_op1_sel_zero
|
||||
add wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_op2_sel_zero
|
||||
add wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_op2_sel_bus
|
||||
add wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_op2_sel_lq
|
||||
add wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_sel_op2_neg
|
||||
add wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_sel_op2_high
|
||||
add wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_core_R
|
||||
add wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_core_V
|
||||
add wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_core_S
|
||||
add wave -noupdate -group {alu
|
||||
} -color Green -radix hexadecimal /test_top/dut/alu_/OP1
|
||||
add wave -noupdate -group {alu
|
||||
} -color Green -radix hexadecimal /test_top/dut/alu_/OP2
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/RESULT
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/alu_bs_oe
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/alu_parity_in
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/alu_oe
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/alu_shift_oe
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/alu_op2_oe
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/alu_op1_oe
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/alu_res_oe
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/alu_op1_sel_low
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/alu_op1_sel_zero
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/alu_op1_sel_bus
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/alu_op2_sel_zero
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/alu_op2_sel_bus
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/alu_op2_sel_lq
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/alu_op_low
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/alu_shift_in
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/alu_sel_op2_neg
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/alu_sel_op2_high
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/alu_shift_left
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/alu_shift_right
|
||||
add wave -noupdate -group {alu
|
||||
} -radix hexadecimal /test_top/dut/alu_/bsel
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/alu_zero
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/alu_parity_out
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/alu_high_eq_9
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/alu_high_gt_9
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/alu_low_gt_9
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/alu_shift_db0
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/alu_shift_db7
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/alu_sf_out
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/alu_yf_out
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/alu_xf_out
|
||||
add wave -noupdate -group {alu
|
||||
} /test_top/dut/alu_/alu_vf_out
|
||||
add wave -noupdate -group {alu
|
||||
} -radix hexadecimal /test_top/dut/alu_/db
|
||||
add wave -noupdate -group {alu
|
||||
} -radix hexadecimal /test_top/dut/alu_/test_db_high
|
||||
add wave -noupdate -group {alu
|
||||
} -radix hexadecimal /test_top/dut/alu_/test_db_low
|
||||
add wave -noupdate -group {alu
|
||||
} -color Magenta /test_top/dut/alu_/alu_core_R
|
||||
add wave -noupdate -group {alu
|
||||
} -color Magenta /test_top/dut/alu_/alu_core_V
|
||||
add wave -noupdate -group {alu
|
||||
} -color Magenta /test_top/dut/alu_/alu_core_S
|
||||
add wave -noupdate -group {alu
|
||||
} -color Magenta /test_top/dut/alu_/alu_core_cf_in
|
||||
add wave -noupdate -group {alu
|
||||
} -color Magenta -radix hexadecimal /test_top/dut/alu_/alu_op1
|
||||
add wave -noupdate -group {alu
|
||||
} -color Magenta -radix hexadecimal /test_top/dut/alu_/alu_op2
|
||||
add wave -noupdate -group {alu
|
||||
} -color Red /test_top/dut/alu_/alu_core_cf_out
|
||||
add wave -noupdate -group {alu
|
||||
} -radix hexadecimal /test_top/dut/alu_/result_hi
|
||||
add wave -noupdate -group {alu
|
||||
} -radix hexadecimal /test_top/dut/alu_/result_lo
|
||||
add wave -noupdate -group {alu
|
||||
} -radix hexadecimal /test_top/dut/alu_/db_high
|
||||
add wave -noupdate -group {alu
|
||||
} -radix hexadecimal /test_top/dut/alu_/db_low
|
||||
add wave -noupdate -group {alu
|
||||
} -radix hexadecimal /test_top/dut/alu_/op1_high
|
||||
add wave -noupdate -group {alu
|
||||
} -radix hexadecimal /test_top/dut/alu_/op1_low
|
||||
add wave -noupdate -group {alu
|
||||
} -radix hexadecimal /test_top/dut/alu_/op2_high
|
||||
add wave -noupdate -group {alu
|
||||
} -radix hexadecimal /test_top/dut/alu_/op2_low
|
||||
add wave -noupdate -group {address latch} /test_top/dut/address_latch_/ctl_inc_cy
|
||||
add wave -noupdate -group {address latch} /test_top/dut/address_latch_/ctl_inc_dec
|
||||
add wave -noupdate -group {address latch} /test_top/dut/address_latch_/clrpc
|
||||
add wave -noupdate -group {address latch} /test_top/dut/address_latch_/ctl_al_we
|
||||
add wave -noupdate -group {address latch} /test_top/dut/address_latch_/ctl_inc_limit6
|
||||
add wave -noupdate -group {address latch} /test_top/dut/address_latch_/ctl_bus_inc_oe
|
||||
add wave -noupdate -group {address latch} /test_top/dut/address_latch_/address_is_1
|
||||
add wave -noupdate -group {address latch} /test_top/dut/address_latch_/ctl_apin_mux
|
||||
add wave -noupdate -group {address latch} /test_top/dut/address_latch_/ctl_apin_mux2
|
||||
add wave -noupdate -group {address latch} -radix hexadecimal /test_top/dut/address_latch_/abus
|
||||
add wave -noupdate -group {address latch} -radix hexadecimal -childformat {{{/test_top/dut/address_latch_/address[15]} -radix hexadecimal} {{/test_top/dut/address_latch_/address[14]} -radix hexadecimal} {{/test_top/dut/address_latch_/address[13]} -radix hexadecimal} {{/test_top/dut/address_latch_/address[12]} -radix hexadecimal} {{/test_top/dut/address_latch_/address[11]} -radix hexadecimal} {{/test_top/dut/address_latch_/address[10]} -radix hexadecimal} {{/test_top/dut/address_latch_/address[9]} -radix hexadecimal} {{/test_top/dut/address_latch_/address[8]} -radix hexadecimal} {{/test_top/dut/address_latch_/address[7]} -radix hexadecimal} {{/test_top/dut/address_latch_/address[6]} -radix hexadecimal} {{/test_top/dut/address_latch_/address[5]} -radix hexadecimal} {{/test_top/dut/address_latch_/address[4]} -radix hexadecimal} {{/test_top/dut/address_latch_/address[3]} -radix hexadecimal} {{/test_top/dut/address_latch_/address[2]} -radix hexadecimal} {{/test_top/dut/address_latch_/address[1]} -radix hexadecimal} {{/test_top/dut/address_latch_/address[0]} -radix hexadecimal}} -subitemconfig {{/test_top/dut/address_latch_/address[15]} {-height 15 -radix hexadecimal} {/test_top/dut/address_latch_/address[14]} {-height 15 -radix hexadecimal} {/test_top/dut/address_latch_/address[13]} {-height 15 -radix hexadecimal} {/test_top/dut/address_latch_/address[12]} {-height 15 -radix hexadecimal} {/test_top/dut/address_latch_/address[11]} {-height 15 -radix hexadecimal} {/test_top/dut/address_latch_/address[10]} {-height 15 -radix hexadecimal} {/test_top/dut/address_latch_/address[9]} {-height 15 -radix hexadecimal} {/test_top/dut/address_latch_/address[8]} {-height 15 -radix hexadecimal} {/test_top/dut/address_latch_/address[7]} {-height 15 -radix hexadecimal} {/test_top/dut/address_latch_/address[6]} {-height 15 -radix hexadecimal} {/test_top/dut/address_latch_/address[5]} {-height 15 -radix hexadecimal} {/test_top/dut/address_latch_/address[4]} {-height 15 -radix hexadecimal} {/test_top/dut/address_latch_/address[3]} {-height 15 -radix hexadecimal} {/test_top/dut/address_latch_/address[2]} {-height 15 -radix hexadecimal} {/test_top/dut/address_latch_/address[1]} {-height 15 -radix hexadecimal} {/test_top/dut/address_latch_/address[0]} {-height 15 -radix hexadecimal}} /test_top/dut/address_latch_/address
|
||||
add wave -noupdate -group {address pins} /test_top/dut/address_pins_/bus_ab_pin_we
|
||||
add wave -noupdate -group {address pins} /test_top/dut/address_pins_/pin_control_oe
|
||||
add wave -noupdate -group {address pins} -label apin_latch /test_top/dut/address_pins_/DFFE_apin_latch
|
||||
add wave -noupdate -group state /test_top/dut/decode_state_/ctl_state_iy_set
|
||||
add wave -noupdate -group state /test_top/dut/decode_state_/ctl_state_ixiy_clr
|
||||
add wave -noupdate -group state /test_top/dut/decode_state_/ctl_state_ixiy_we
|
||||
add wave -noupdate -group state /test_top/dut/decode_state_/ctl_state_halt_set
|
||||
add wave -noupdate -group state /test_top/dut/decode_state_/ctl_state_tbl_we
|
||||
add wave -noupdate -group state /test_top/dut/decode_state_/ctl_state_tbl_ed_set
|
||||
add wave -noupdate -group state /test_top/dut/decode_state_/ctl_state_tbl_cb_set
|
||||
add wave -noupdate -group state /test_top/dut/decode_state_/ctl_state_alu
|
||||
add wave -noupdate -group state /test_top/dut/decode_state_/address_is_1
|
||||
add wave -noupdate -group state /test_top/dut/decode_state_/ctl_repeat_we
|
||||
add wave -noupdate -group state /test_top/dut/decode_state_/in_intr
|
||||
add wave -noupdate -group state /test_top/dut/decode_state_/in_nmi
|
||||
add wave -noupdate -group state /test_top/dut/decode_state_/nreset
|
||||
add wave -noupdate -group state /test_top/dut/decode_state_/in_halt
|
||||
add wave -noupdate -group state /test_top/dut/decode_state_/table_cb
|
||||
add wave -noupdate -group state /test_top/dut/decode_state_/table_ed
|
||||
add wave -noupdate -group state /test_top/dut/decode_state_/table_xx
|
||||
add wave -noupdate -group state /test_top/dut/decode_state_/use_ix
|
||||
add wave -noupdate -group state /test_top/dut/decode_state_/use_ixiy
|
||||
add wave -noupdate -group state /test_top/dut/decode_state_/in_alu
|
||||
add wave -noupdate -group state /test_top/dut/decode_state_/repeat_en
|
||||
add wave -noupdate -group interrupts /test_top/dut/interrupts_/intr
|
||||
add wave -noupdate -group interrupts /test_top/dut/interrupts_/iff1
|
||||
add wave -noupdate -group interrupts /test_top/dut/interrupts_/iff2
|
||||
add wave -noupdate -group interrupts /test_top/dut/interrupts_/im1
|
||||
add wave -noupdate -group interrupts /test_top/dut/interrupts_/im2
|
||||
add wave -noupdate -group interrupts /test_top/dut/interrupts_/nmi
|
||||
add wave -noupdate -group interrupts /test_top/dut/interrupts_/ctl_iff1_iff2
|
||||
add wave -noupdate -group interrupts /test_top/dut/interrupts_/ctl_iffx_we
|
||||
add wave -noupdate -group interrupts /test_top/dut/interrupts_/ctl_iffx_bit
|
||||
add wave -noupdate -group interrupts /test_top/dut/interrupts_/ctl_im_we
|
||||
add wave -noupdate -group interrupts /test_top/dut/interrupts_/ctl_no_ints
|
||||
add wave -noupdate -group interrupts /test_top/dut/interrupts_/in_nmi
|
||||
add wave -noupdate -group interrupts /test_top/dut/interrupts_/in_intr
|
||||
add wave -noupdate -group interrupts /test_top/dut/interrupts_/int_armed
|
||||
add wave -noupdate -group interrupts /test_top/dut/interrupts_/nmi_armed
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {Cursor {3900 ns} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 163
|
||||
configure wave -valuecolwidth 53
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
configure wave -timelineunits us
|
||||
update
|
||||
WaveRestoreZoom {0 ns} {7800 ns}
|
||||
@@ -0,0 +1,61 @@
|
||||
//--------------------------------------------------------------
|
||||
// Implements I/O Model for simulation
|
||||
//--------------------------------------------------------------
|
||||
module io (Address, Data, CS, WE, OE);
|
||||
|
||||
// Set to 1 to have text output to the file "iolog.txt"
|
||||
int iolog = 1;
|
||||
|
||||
// Set to 1 if you want debug printout on each IO access
|
||||
int debug = 0;
|
||||
|
||||
int fd;
|
||||
input [15:0] Address;
|
||||
inout [7:0] Data;
|
||||
input CS, WE, OE;
|
||||
|
||||
reg [7:0] IO [0:1<<16];
|
||||
|
||||
// Return data for the specified IO address:
|
||||
// 1. If the current address is 0A00, that's the UART busy bit (which is never busy for ModelSim), so return 00
|
||||
// 2. If the IO map is not defined for the current address, return FF
|
||||
// 3. If the IO map is defined, return the value from it
|
||||
// 4. Lastly, if !CS and !OE (not selecting the IO), tri-state the data bus
|
||||
assign Data = (!CS && !OE) ? (Address==16'h0A00)? 8'h00 : (IO[Address]===8'hxx) ? 8'hFF : IO[Address] : {8{1'bz}};
|
||||
|
||||
// Read the initial content of the IO map from file
|
||||
initial begin : init
|
||||
$readmemh("io.hex", IO);
|
||||
// If logging to a file was enabled, clear the file so we can append
|
||||
if (iolog) begin
|
||||
fd = $fopen("iolog.txt", "wb");
|
||||
$fclose(fd);
|
||||
end
|
||||
end : init
|
||||
|
||||
always @(!CS && !OE) begin
|
||||
if (debug)
|
||||
$strobe("[IO] IN A=%H, D=%H", Address, Data);
|
||||
end
|
||||
|
||||
always @(CS or WE)
|
||||
if (!CS && !WE) begin
|
||||
if (debug)
|
||||
$strobe("[IO] OUT A=%H, D=%H", Address, Data);
|
||||
if (Address==8*256) begin
|
||||
$write("%c", Data);
|
||||
// If logging to a file was enabled, append a character
|
||||
if (iolog) begin
|
||||
fd = $fopen("iolog.txt", "ab");
|
||||
$fwrite(fd, "%c", Data);
|
||||
$fclose(fd);
|
||||
end
|
||||
end
|
||||
IO[Address] = Data;
|
||||
end
|
||||
|
||||
always @(WE or OE)
|
||||
if (!WE && !OE)
|
||||
$display("[IO] error: OE and WE both active!");
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,32 @@
|
||||
//--------------------------------------------------------------
|
||||
// Interrupt test for simulation
|
||||
// This model injects an interrupt opcode on the bus
|
||||
//--------------------------------------------------------------
|
||||
module iorq (Data, M1, IORQ);
|
||||
|
||||
// Set to 1 if you want debug printout on each IO access
|
||||
int debug = 0;
|
||||
|
||||
inout [7:0] Data;
|
||||
input M1, IORQ;
|
||||
|
||||
// Define the opcode to be sent through IORQ (FF=RST38, C7=RST0,...)
|
||||
|
||||
// To test interrupts in mode 0, uncommend one of these lines (pushed opcode):
|
||||
//`define OPCODE 8'hFF
|
||||
//`define OPCODE 8'hC7
|
||||
|
||||
// To test interrupts in mode 2, uncommend this line (this is a vector):
|
||||
`define OPCODE 8'h80
|
||||
|
||||
// Return data on an IORQ condition
|
||||
assign Data = (!M1 && !IORQ) ? `OPCODE : {8{1'bz}};
|
||||
|
||||
int fd;
|
||||
|
||||
always @(!M1 && !IORQ) begin
|
||||
if (debug)
|
||||
$strobe("[IORQ] DB=%H", `OPCODE);
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,41 @@
|
||||
//--------------------------------------------------------------
|
||||
// Implements RAM Model for simulation
|
||||
// Loads in a file "ram.hexdump" before execution.
|
||||
//--------------------------------------------------------------
|
||||
module ram (Address, Data, CS, WE, OE);
|
||||
|
||||
// Set this to 1 if you want debug printout on each RAM access
|
||||
int debug = 0;
|
||||
|
||||
input [15:0] Address;
|
||||
inout [7:0] Data;
|
||||
input CS, WE, OE;
|
||||
|
||||
reg [7:0] Mem [0:1<<16];
|
||||
|
||||
// Return data at the specified memory address; return 0x76 for non-initialized memory
|
||||
assign Data = (!CS && !OE) ? (Mem[Address]===8'hxx) ? 8'h76 : Mem[Address] : {8{1'bz}};
|
||||
|
||||
// Read the initial content of the RAM memory from a file
|
||||
initial begin : init
|
||||
// Read the CPU code (address 0) to simulate
|
||||
$readmemh("ram.hexdump", Mem, 0);
|
||||
end : init
|
||||
|
||||
always @(!CS && !OE) begin
|
||||
if (debug)
|
||||
$strobe("[ram] RD A=%H, D=%H", Address, Data);
|
||||
end
|
||||
|
||||
always @(CS or WE)
|
||||
if (!CS && !WE) begin
|
||||
if (debug)
|
||||
$strobe("[ram] WR A=%H, D=%H", Address, Data);
|
||||
Mem[Address] = Data;
|
||||
end
|
||||
|
||||
always @(WE or OE)
|
||||
if (!WE && !OE)
|
||||
$display("[ram] error: OE and WE both active!");
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,42 @@
|
||||
//--------------------------------------------------------------
|
||||
// Testbench using Fuse Z80 emulator test vectors
|
||||
//--------------------------------------------------------------
|
||||
`include "z80.svh"
|
||||
|
||||
module test_bench_fuse(z80_if.tb z);
|
||||
|
||||
assign clk = z.CLK;
|
||||
|
||||
integer f;
|
||||
// Instead of the PC register, we read the address of the next instruction
|
||||
logic [15:0] pc;
|
||||
|
||||
initial begin : init
|
||||
z.nWAIT <= `CLR;
|
||||
z.nINT <= `CLR;
|
||||
z.nNMI <= `CLR;
|
||||
z.nBUSRQ <= `CLR;
|
||||
z.nRESET <= `CLR;
|
||||
|
||||
// Run all the tests and write the result to a file
|
||||
f = $fopen("fuse.result.txt");
|
||||
`include "test_fuse.vh"
|
||||
$fclose(f);
|
||||
|
||||
end : init
|
||||
|
||||
endmodule
|
||||
|
||||
module test_fuse();
|
||||
|
||||
bit clk = 1;
|
||||
initial repeat (`TOTAL_CLKS) #1 clk = ~clk;
|
||||
|
||||
z80_if z80(clk); // Instantiate the Z80 bus interface
|
||||
z80_top_ifc_n dut(z80); // Create an instance of our Z80 design
|
||||
test_bench_fuse tb(z80); // Create an instance of the test bench
|
||||
|
||||
ram ram( .Address(z80.A), .Data(z80.D), .CS(z80.nMREQ), .WE(z80.nWR), .OE(z80.nRD) );
|
||||
io io( .Address(z80.A), .Data(z80.D), .CS(z80.nIORQ), .WE(z80.nWR), .OE(z80.nRD) );
|
||||
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,104 @@
|
||||
//--------------------------------------------------------------
|
||||
// Testbench for the top level design
|
||||
//--------------------------------------------------------------
|
||||
`include "z80.svh"
|
||||
|
||||
module test_bench_top(z80_if.tb z);
|
||||
|
||||
assign clk = z.CLK;
|
||||
|
||||
initial begin : init
|
||||
$display("Test: Start of test at %d", $time);
|
||||
z.nWAIT <= `CLR;
|
||||
z.nINT <= `CLR;
|
||||
z.nNMI <= `CLR;
|
||||
z.nBUSRQ <= `CLR;
|
||||
z.nRESET <= `SET;
|
||||
#2 repeat (3) @(posedge clk);
|
||||
z.nRESET <= `CLR;
|
||||
end : init
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// Testbench for interrupt testing
|
||||
// Enable one or more interrupt generators and run them with the
|
||||
// 'hello world' code
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
// Infuse a NMI at a certain clock
|
||||
initial begin : nmi_once
|
||||
repeat (500) @(posedge clk);
|
||||
// z.nNMI <= `SET;
|
||||
repeat (1) @(posedge clk);
|
||||
z.nNMI <= `CLR;
|
||||
end : nmi_once
|
||||
|
||||
// Test sending a *periodic* NMI
|
||||
always begin : nmi_rep
|
||||
repeat (3000) @(posedge clk);
|
||||
// z.nNMI <= `SET;
|
||||
repeat (1) @(posedge clk);
|
||||
z.nNMI <= `CLR;
|
||||
end : nmi_rep
|
||||
|
||||
// Infuse an INT at a certain clock
|
||||
initial begin : int_once
|
||||
repeat (1000) @(posedge clk);
|
||||
// z.nINT <= `SET;
|
||||
repeat (300) @(posedge clk);
|
||||
z.nINT <= `CLR;
|
||||
end : int_once
|
||||
|
||||
// Test sending a *periodic* INT
|
||||
always begin : int_rep
|
||||
repeat (5000) @(posedge clk);
|
||||
// z.nINT <= `SET;
|
||||
repeat (300) @(posedge clk);
|
||||
z.nINT <= `CLR;
|
||||
end : int_rep
|
||||
|
||||
// Test WAIT.. inject at will
|
||||
initial begin : wait_once
|
||||
repeat (1008) @(posedge clk);
|
||||
// z.nWAIT <= `SET;
|
||||
repeat (2) @(posedge clk);
|
||||
z.nWAIT <= `CLR;
|
||||
end : wait_once
|
||||
|
||||
// Test BUSRQ / BUSACK
|
||||
initial begin : busrq_once
|
||||
repeat (10) @(posedge clk);
|
||||
// z.nBUSRQ <= `SET;
|
||||
repeat (10) @(posedge clk);
|
||||
z.nBUSRQ <= `CLR;
|
||||
end : busrq_once
|
||||
|
||||
// Test special RESET
|
||||
initial begin : spc_reset
|
||||
repeat (40) @(posedge clk);
|
||||
// z.nRESET <= `SET;
|
||||
repeat (1) @(posedge clk);
|
||||
z.nRESET <= `CLR;
|
||||
end : spc_reset
|
||||
|
||||
endmodule
|
||||
|
||||
module test_top();
|
||||
|
||||
// Although the clock is going forever, we will stop simulation at some point
|
||||
bit clk = 1;
|
||||
initial forever #1 clk = ~clk;
|
||||
|
||||
// Stop after printing "Hello, World!"
|
||||
initial begin : stopme
|
||||
#70000 $stop();
|
||||
end : stopme
|
||||
|
||||
z80_if z80(clk); // Instantiate the Z80 bus interface
|
||||
z80_top_ifc_n dut(z80); // Create an instance of our Z80 design
|
||||
test_bench_top tb(z80); // Create an instance of the test bench
|
||||
|
||||
ram ram( .Address(z80.A), .Data(z80.D), .CS(z80.nMREQ), .WE(z80.nWR), .OE(z80.nRD) );
|
||||
io io( .Address(z80.A), .Data(z80.D), .CS(z80.nIORQ), .WE(z80.nWR), .OE(z80.nRD) );
|
||||
iorq iorq( .Data(z80.D), .M1(z80.nM1), .IORQ(z80.nIORQ) );
|
||||
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,30 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
# Date created = 09:31:29 October 13, 2014
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "13.0"
|
||||
DATE = "09:31:29 October 13, 2014"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "toplevel"
|
||||
@@ -0,0 +1,603 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
# Date created = 09:31:29 October 13, 2014
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# toplevel_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
###########################################################################
|
||||
# System Clocks
|
||||
###########################################################################
|
||||
set_location_assignment PIN_D12 -to CLOCK_27
|
||||
set_location_assignment PIN_E12 -to CLOCK_27_1
|
||||
set_location_assignment PIN_B12 -to CLOCK_24
|
||||
set_location_assignment PIN_A12 -to CLOCK_24_1
|
||||
set_location_assignment PIN_L1 -to CLOCK_50
|
||||
set_location_assignment PIN_M21 -to EXT_CLOCK
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_27
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_27_1
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24_1
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_50
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to EXT_CLOCK
|
||||
|
||||
###########################################################################
|
||||
# Pushbuttons
|
||||
###########################################################################
|
||||
set_location_assignment PIN_R22 -to KEY0
|
||||
set_location_assignment PIN_R21 -to KEY1
|
||||
set_location_assignment PIN_T22 -to KEY2
|
||||
set_location_assignment PIN_T21 -to KEY3
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to KEY0
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to KEY1
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to KEY2
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to KEY3
|
||||
|
||||
###########################################################################
|
||||
# Toggle switches
|
||||
###########################################################################
|
||||
set_location_assignment PIN_L22 -to SW0
|
||||
set_location_assignment PIN_L21 -to SW1
|
||||
set_location_assignment PIN_M22 -to SW2
|
||||
set_location_assignment PIN_V12 -to SW3
|
||||
set_location_assignment PIN_W12 -to SW4
|
||||
set_location_assignment PIN_U12 -to SW5
|
||||
set_location_assignment PIN_U11 -to SW6
|
||||
set_location_assignment PIN_M2 -to SW7
|
||||
set_location_assignment PIN_M1 -to SW8
|
||||
set_location_assignment PIN_L2 -to SW9
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to SW0
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to SW1
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to SW2
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to SW3
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to SW4
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to SW5
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to SW6
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to SW7
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to SW8
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to SW9
|
||||
|
||||
###########################################################################
|
||||
# LEDs
|
||||
###########################################################################
|
||||
set_location_assignment PIN_R20 -to LEDR[0]
|
||||
set_location_assignment PIN_R19 -to LEDR[1]
|
||||
set_location_assignment PIN_U19 -to LEDR[2]
|
||||
set_location_assignment PIN_Y19 -to LEDR[3]
|
||||
set_location_assignment PIN_T18 -to LEDR[4]
|
||||
set_location_assignment PIN_V19 -to LEDR[5]
|
||||
set_location_assignment PIN_Y18 -to LEDR[6]
|
||||
set_location_assignment PIN_U18 -to LEDR[7]
|
||||
set_location_assignment PIN_R18 -to LEDR[8]
|
||||
set_location_assignment PIN_R17 -to LEDR[9]
|
||||
set_location_assignment PIN_U22 -to LEDG[0]
|
||||
set_location_assignment PIN_U21 -to LEDG[1]
|
||||
set_location_assignment PIN_V22 -to LEDG[2]
|
||||
set_location_assignment PIN_V21 -to LEDG[3]
|
||||
set_location_assignment PIN_W22 -to LEDG[4]
|
||||
set_location_assignment PIN_W21 -to LEDG[5]
|
||||
set_location_assignment PIN_Y22 -to LEDG[6]
|
||||
set_location_assignment PIN_Y21 -to LEDG[7]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[0]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[1]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[2]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[3]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[4]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[5]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[6]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[7]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[8]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[9]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[0]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[1]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[2]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[3]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[4]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[5]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[6]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[7]
|
||||
|
||||
###########################################################################
|
||||
# 7-Segment displays
|
||||
###########################################################################
|
||||
set_location_assignment PIN_J2 -to HEX0[0]
|
||||
set_location_assignment PIN_J1 -to HEX0[1]
|
||||
set_location_assignment PIN_H2 -to HEX0[2]
|
||||
set_location_assignment PIN_H1 -to HEX0[3]
|
||||
set_location_assignment PIN_F2 -to HEX0[4]
|
||||
set_location_assignment PIN_F1 -to HEX0[5]
|
||||
set_location_assignment PIN_E2 -to HEX0[6]
|
||||
set_location_assignment PIN_E1 -to HEX1[0]
|
||||
set_location_assignment PIN_H6 -to HEX1[1]
|
||||
set_location_assignment PIN_H5 -to HEX1[2]
|
||||
set_location_assignment PIN_H4 -to HEX1[3]
|
||||
set_location_assignment PIN_G3 -to HEX1[4]
|
||||
set_location_assignment PIN_D2 -to HEX1[5]
|
||||
set_location_assignment PIN_D1 -to HEX1[6]
|
||||
set_location_assignment PIN_G5 -to HEX2[0]
|
||||
set_location_assignment PIN_G6 -to HEX2[1]
|
||||
set_location_assignment PIN_C2 -to HEX2[2]
|
||||
set_location_assignment PIN_C1 -to HEX2[3]
|
||||
set_location_assignment PIN_E3 -to HEX2[4]
|
||||
set_location_assignment PIN_E4 -to HEX2[5]
|
||||
set_location_assignment PIN_D3 -to HEX2[6]
|
||||
set_location_assignment PIN_F4 -to HEX3[0]
|
||||
set_location_assignment PIN_D5 -to HEX3[1]
|
||||
set_location_assignment PIN_D6 -to HEX3[2]
|
||||
set_location_assignment PIN_J4 -to HEX3[3]
|
||||
set_location_assignment PIN_L8 -to HEX3[4]
|
||||
set_location_assignment PIN_F3 -to HEX3[5]
|
||||
set_location_assignment PIN_D4 -to HEX3[6]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]
|
||||
|
||||
###########################################################################
|
||||
# VGA
|
||||
###########################################################################
|
||||
set_location_assignment PIN_D9 -to VGA_R[0]
|
||||
set_location_assignment PIN_C9 -to VGA_R[1]
|
||||
set_location_assignment PIN_A7 -to VGA_R[2]
|
||||
set_location_assignment PIN_B7 -to VGA_R[3]
|
||||
set_location_assignment PIN_B8 -to VGA_G[0]
|
||||
set_location_assignment PIN_C10 -to VGA_G[1]
|
||||
set_location_assignment PIN_B9 -to VGA_G[2]
|
||||
set_location_assignment PIN_A8 -to VGA_G[3]
|
||||
set_location_assignment PIN_A9 -to VGA_B[0]
|
||||
set_location_assignment PIN_D11 -to VGA_B[1]
|
||||
set_location_assignment PIN_A10 -to VGA_B[2]
|
||||
set_location_assignment PIN_B10 -to VGA_B[3]
|
||||
set_location_assignment PIN_A11 -to VGA_HS
|
||||
set_location_assignment PIN_B11 -to VGA_VS
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[0]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[1]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[2]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[3]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[0]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[1]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[2]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[3]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[0]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[1]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[2]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[3]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_HS
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to VGA_VS
|
||||
|
||||
###########################################################################
|
||||
# Audio Codec
|
||||
###########################################################################
|
||||
set_location_assignment PIN_A3 -to I2C_SCLK
|
||||
set_location_assignment PIN_B3 -to I2C_SDAT
|
||||
set_location_assignment PIN_A6 -to AUD_ADCLRCK
|
||||
set_location_assignment PIN_B6 -to AUD_ADCDAT
|
||||
set_location_assignment PIN_A5 -to AUD_DACLRCK
|
||||
set_location_assignment PIN_B5 -to AUD_DACDAT
|
||||
set_location_assignment PIN_B4 -to AUD_XCK
|
||||
set_location_assignment PIN_A4 -to AUD_BCLK
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK
|
||||
|
||||
###########################################################################
|
||||
# Serial (UART)
|
||||
###########################################################################
|
||||
set_location_assignment PIN_F14 -to UART_RXD
|
||||
set_location_assignment PIN_G12 -to UART_TXD
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to UART_RXD
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to UART_TXD
|
||||
|
||||
###########################################################################
|
||||
# PS/2
|
||||
###########################################################################
|
||||
set_location_assignment PIN_H15 -to PS2_CLK
|
||||
set_location_assignment PIN_J14 -to PS2_DAT
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to PS2_CLK
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to PS2_DAT
|
||||
|
||||
###########################################################################
|
||||
# SD Card
|
||||
###########################################################################
|
||||
set_location_assignment PIN_E8 -to TDI
|
||||
set_location_assignment PIN_D8 -to TCS
|
||||
set_location_assignment PIN_C7 -to TCK
|
||||
set_location_assignment PIN_D7 -to TDO
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to TDI
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to TCS
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to TCK
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to TDO
|
||||
|
||||
###########################################################################
|
||||
# SDRAM
|
||||
###########################################################################
|
||||
set_location_assignment PIN_W4 -to DRAM_ADDR[0]
|
||||
set_location_assignment PIN_W5 -to DRAM_ADDR[1]
|
||||
set_location_assignment PIN_Y3 -to DRAM_ADDR[2]
|
||||
set_location_assignment PIN_Y4 -to DRAM_ADDR[3]
|
||||
set_location_assignment PIN_R6 -to DRAM_ADDR[4]
|
||||
set_location_assignment PIN_R5 -to DRAM_ADDR[5]
|
||||
set_location_assignment PIN_P6 -to DRAM_ADDR[6]
|
||||
set_location_assignment PIN_P5 -to DRAM_ADDR[7]
|
||||
set_location_assignment PIN_P3 -to DRAM_ADDR[8]
|
||||
set_location_assignment PIN_N4 -to DRAM_ADDR[9]
|
||||
set_location_assignment PIN_W3 -to DRAM_ADDR[10]
|
||||
set_location_assignment PIN_N6 -to DRAM_ADDR[11]
|
||||
set_location_assignment PIN_U1 -to DRAM_DQ[0]
|
||||
set_location_assignment PIN_U2 -to DRAM_DQ[1]
|
||||
set_location_assignment PIN_V1 -to DRAM_DQ[2]
|
||||
set_location_assignment PIN_V2 -to DRAM_DQ[3]
|
||||
set_location_assignment PIN_W1 -to DRAM_DQ[4]
|
||||
set_location_assignment PIN_W2 -to DRAM_DQ[5]
|
||||
set_location_assignment PIN_Y1 -to DRAM_DQ[6]
|
||||
set_location_assignment PIN_Y2 -to DRAM_DQ[7]
|
||||
set_location_assignment PIN_N1 -to DRAM_DQ[8]
|
||||
set_location_assignment PIN_N2 -to DRAM_DQ[9]
|
||||
set_location_assignment PIN_P1 -to DRAM_DQ[10]
|
||||
set_location_assignment PIN_P2 -to DRAM_DQ[11]
|
||||
set_location_assignment PIN_R1 -to DRAM_DQ[12]
|
||||
set_location_assignment PIN_R2 -to DRAM_DQ[13]
|
||||
set_location_assignment PIN_T1 -to DRAM_DQ[14]
|
||||
set_location_assignment PIN_T2 -to DRAM_DQ[15]
|
||||
set_location_assignment PIN_U3 -to DRAM_BA_0
|
||||
set_location_assignment PIN_V4 -to DRAM_BA_1
|
||||
set_location_assignment PIN_R7 -to DRAM_LDQM
|
||||
set_location_assignment PIN_M5 -to DRAM_UDQM
|
||||
set_location_assignment PIN_T5 -to DRAM_RAS_N
|
||||
set_location_assignment PIN_T3 -to DRAM_CAS_N
|
||||
set_location_assignment PIN_N3 -to DRAM_CKE
|
||||
set_location_assignment PIN_U4 -to DRAM_CLK
|
||||
set_location_assignment PIN_R8 -to DRAM_WE_N
|
||||
set_location_assignment PIN_T6 -to DRAM_CS_N
|
||||
|
||||
###########################################################################
|
||||
# SRAM
|
||||
###########################################################################
|
||||
set_location_assignment PIN_AA3 -to SRAM_ADDR[0]
|
||||
set_location_assignment PIN_AB3 -to SRAM_ADDR[1]
|
||||
set_location_assignment PIN_AA4 -to SRAM_ADDR[2]
|
||||
set_location_assignment PIN_AB4 -to SRAM_ADDR[3]
|
||||
set_location_assignment PIN_AA5 -to SRAM_ADDR[4]
|
||||
set_location_assignment PIN_AB10 -to SRAM_ADDR[5]
|
||||
set_location_assignment PIN_AA11 -to SRAM_ADDR[6]
|
||||
set_location_assignment PIN_AB11 -to SRAM_ADDR[7]
|
||||
set_location_assignment PIN_V11 -to SRAM_ADDR[8]
|
||||
set_location_assignment PIN_W11 -to SRAM_ADDR[9]
|
||||
set_location_assignment PIN_R11 -to SRAM_ADDR[10]
|
||||
set_location_assignment PIN_T11 -to SRAM_ADDR[11]
|
||||
set_location_assignment PIN_Y10 -to SRAM_ADDR[12]
|
||||
set_location_assignment PIN_U10 -to SRAM_ADDR[13]
|
||||
set_location_assignment PIN_R10 -to SRAM_ADDR[14]
|
||||
set_location_assignment PIN_T7 -to SRAM_ADDR[15]
|
||||
set_location_assignment PIN_Y6 -to SRAM_ADDR[16]
|
||||
set_location_assignment PIN_Y5 -to SRAM_ADDR[17]
|
||||
set_location_assignment PIN_AA6 -to SRAM_DQ[0]
|
||||
set_location_assignment PIN_AB6 -to SRAM_DQ[1]
|
||||
set_location_assignment PIN_AA7 -to SRAM_DQ[2]
|
||||
set_location_assignment PIN_AB7 -to SRAM_DQ[3]
|
||||
set_location_assignment PIN_AA8 -to SRAM_DQ[4]
|
||||
set_location_assignment PIN_AB8 -to SRAM_DQ[5]
|
||||
set_location_assignment PIN_AA9 -to SRAM_DQ[6]
|
||||
set_location_assignment PIN_AB9 -to SRAM_DQ[7]
|
||||
set_location_assignment PIN_Y9 -to SRAM_DQ[8]
|
||||
set_location_assignment PIN_W9 -to SRAM_DQ[9]
|
||||
set_location_assignment PIN_V9 -to SRAM_DQ[10]
|
||||
set_location_assignment PIN_U9 -to SRAM_DQ[11]
|
||||
set_location_assignment PIN_R9 -to SRAM_DQ[12]
|
||||
set_location_assignment PIN_W8 -to SRAM_DQ[13]
|
||||
set_location_assignment PIN_V8 -to SRAM_DQ[14]
|
||||
set_location_assignment PIN_U8 -to SRAM_DQ[15]
|
||||
set_location_assignment PIN_AB5 -to SRAM_CE_N
|
||||
set_location_assignment PIN_T8 -to SRAM_OE_N
|
||||
set_location_assignment PIN_AA10 -to SRAM_WE_N
|
||||
set_location_assignment PIN_W7 -to SRAM_UB_N
|
||||
set_location_assignment PIN_Y7 -to SRAM_LB_N
|
||||
|
||||
###########################################################################
|
||||
# FLASH
|
||||
###########################################################################
|
||||
set_location_assignment PIN_AB20 -to FL_ADDR[0]
|
||||
set_location_assignment PIN_AA14 -to FL_ADDR[1]
|
||||
set_location_assignment PIN_Y16 -to FL_ADDR[2]
|
||||
set_location_assignment PIN_R15 -to FL_ADDR[3]
|
||||
set_location_assignment PIN_T15 -to FL_ADDR[4]
|
||||
set_location_assignment PIN_U15 -to FL_ADDR[5]
|
||||
set_location_assignment PIN_V15 -to FL_ADDR[6]
|
||||
set_location_assignment PIN_W15 -to FL_ADDR[7]
|
||||
set_location_assignment PIN_R14 -to FL_ADDR[8]
|
||||
set_location_assignment PIN_Y13 -to FL_ADDR[9]
|
||||
set_location_assignment PIN_R12 -to FL_ADDR[10]
|
||||
set_location_assignment PIN_T12 -to FL_ADDR[11]
|
||||
set_location_assignment PIN_AB14 -to FL_ADDR[12]
|
||||
set_location_assignment PIN_AA13 -to FL_ADDR[13]
|
||||
set_location_assignment PIN_AB13 -to FL_ADDR[14]
|
||||
set_location_assignment PIN_AA12 -to FL_ADDR[15]
|
||||
set_location_assignment PIN_AB12 -to FL_ADDR[16]
|
||||
set_location_assignment PIN_AA20 -to FL_ADDR[17]
|
||||
set_location_assignment PIN_U14 -to FL_ADDR[18]
|
||||
set_location_assignment PIN_V14 -to FL_ADDR[19]
|
||||
set_location_assignment PIN_U13 -to FL_ADDR[20]
|
||||
set_location_assignment PIN_R13 -to FL_ADDR[21]
|
||||
set_location_assignment PIN_AB16 -to FL_DQ[0]
|
||||
set_location_assignment PIN_AA16 -to FL_DQ[1]
|
||||
set_location_assignment PIN_AB17 -to FL_DQ[2]
|
||||
set_location_assignment PIN_AA17 -to FL_DQ[3]
|
||||
set_location_assignment PIN_AB18 -to FL_DQ[4]
|
||||
set_location_assignment PIN_AA18 -to FL_DQ[5]
|
||||
set_location_assignment PIN_AB19 -to FL_DQ[6]
|
||||
set_location_assignment PIN_AA19 -to FL_DQ[7]
|
||||
set_location_assignment PIN_AB15 -to FL_CE_N
|
||||
set_location_assignment PIN_AA15 -to FL_OE_N
|
||||
set_location_assignment PIN_Y14 -to FL_WE_N
|
||||
set_location_assignment PIN_W14 -to FL_RST_N
|
||||
|
||||
###########################################################################
|
||||
# GPIO-0 Expansion Header 1
|
||||
###########################################################################
|
||||
set_location_assignment PIN_A13 -to D[0]
|
||||
set_location_assignment PIN_B13 -to D[1]
|
||||
set_location_assignment PIN_A14 -to D[2]
|
||||
set_location_assignment PIN_B14 -to D[3]
|
||||
set_location_assignment PIN_A15 -to D[4]
|
||||
set_location_assignment PIN_B15 -to D[5]
|
||||
set_location_assignment PIN_A16 -to D[6]
|
||||
set_location_assignment PIN_B16 -to D[7]
|
||||
set_location_assignment PIN_A17 -to A[0]
|
||||
set_location_assignment PIN_B17 -to A[1]
|
||||
set_location_assignment PIN_A18 -to A[2]
|
||||
set_location_assignment PIN_B18 -to A[3]
|
||||
set_location_assignment PIN_A19 -to A[4]
|
||||
set_location_assignment PIN_B19 -to A[5]
|
||||
set_location_assignment PIN_A20 -to A[6]
|
||||
set_location_assignment PIN_B20 -to A[7]
|
||||
set_location_assignment PIN_C21 -to A[8]
|
||||
set_location_assignment PIN_C22 -to A[9]
|
||||
set_location_assignment PIN_D21 -to A[10]
|
||||
set_location_assignment PIN_D22 -to A[11]
|
||||
set_location_assignment PIN_E21 -to A[12]
|
||||
set_location_assignment PIN_E22 -to A[13]
|
||||
set_location_assignment PIN_F21 -to A[14]
|
||||
set_location_assignment PIN_F22 -to A[15]
|
||||
set_location_assignment PIN_G21 -to GPIO_0[24]
|
||||
set_location_assignment PIN_G22 -to GPIO_0[25]
|
||||
set_location_assignment PIN_J21 -to GPIO_0[26]
|
||||
set_location_assignment PIN_J22 -to GPIO_0[27]
|
||||
set_location_assignment PIN_K21 -to GPIO_0[28]
|
||||
set_location_assignment PIN_K22 -to GPIO_0[29]
|
||||
set_location_assignment PIN_J19 -to GPIO_0[30]
|
||||
set_location_assignment PIN_J20 -to GPIO_0[31]
|
||||
set_location_assignment PIN_J18 -to GPIO_0[32]
|
||||
set_location_assignment PIN_K20 -to GPIO_0[33]
|
||||
set_location_assignment PIN_L19 -to GPIO_0[34]
|
||||
set_location_assignment PIN_L18 -to GPIO_0[35]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[0]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[1]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[2]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[3]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[4]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[5]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[6]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[7]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[8]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[9]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[10]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[11]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[12]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[13]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[14]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[15]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[16]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[17]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[18]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[19]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[20]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[21]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[22]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[23]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[24]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[25]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[26]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[27]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[28]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[29]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[30]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[31]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[32]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[33]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[34]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[35]
|
||||
|
||||
###########################################################################
|
||||
# GPIO-1 Expansion Header 2
|
||||
###########################################################################
|
||||
set_location_assignment PIN_H12 -to GPIO_1[0]
|
||||
set_location_assignment PIN_H13 -to GPIO_1[1]
|
||||
set_location_assignment PIN_H14 -to GPIO_1[2]
|
||||
set_location_assignment PIN_G15 -to GPIO_1[3]
|
||||
set_location_assignment PIN_E14 -to GPIO_1[4]
|
||||
set_location_assignment PIN_E15 -to GPIO_1[5]
|
||||
set_location_assignment PIN_F15 -to GPIO_1[6]
|
||||
set_location_assignment PIN_G16 -to GPIO_1[7]
|
||||
set_location_assignment PIN_F12 -to GPIO_1[8]
|
||||
set_location_assignment PIN_F13 -to GPIO_1[9]
|
||||
set_location_assignment PIN_C14 -to GPIO_1[10]
|
||||
set_location_assignment PIN_D14 -to GPIO_1[11]
|
||||
set_location_assignment PIN_D15 -to GPIO_1[12]
|
||||
set_location_assignment PIN_D16 -to GPIO_1[13]
|
||||
set_location_assignment PIN_C17 -to GPIO_1[14]
|
||||
set_location_assignment PIN_C18 -to GPIO_1[15]
|
||||
set_location_assignment PIN_C19 -to GPIO_1[16]
|
||||
set_location_assignment PIN_C20 -to GPIO_1[17]
|
||||
set_location_assignment PIN_D19 -to GPIO_1[18]
|
||||
set_location_assignment PIN_D20 -to GPIO_1[19]
|
||||
set_location_assignment PIN_E20 -to GPIO_1[20]
|
||||
set_location_assignment PIN_F20 -to GPIO_1[21]
|
||||
set_location_assignment PIN_E19 -to GPIO_1[22]
|
||||
set_location_assignment PIN_E18 -to GPIO_1[23]
|
||||
set_location_assignment PIN_G20 -to GPIO_1[24]
|
||||
set_location_assignment PIN_G18 -to GPIO_1[25]
|
||||
set_location_assignment PIN_G17 -to GPIO_1[26]
|
||||
set_location_assignment PIN_H17 -to GPIO_1[27]
|
||||
set_location_assignment PIN_J15 -to GPIO_1[28]
|
||||
set_location_assignment PIN_H18 -to GPIO_1[29]
|
||||
set_location_assignment PIN_N22 -to GPIO_1[30]
|
||||
set_location_assignment PIN_N21 -to GPIO_1[31]
|
||||
set_location_assignment PIN_P15 -to GPIO_1[32]
|
||||
set_location_assignment PIN_N15 -to GPIO_1[33]
|
||||
set_location_assignment PIN_P17 -to GPIO_1[34]
|
||||
set_location_assignment PIN_P18 -to GPIO_1[35]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[0]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[1]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[2]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[3]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[4]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[5]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[6]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[7]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[8]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[9]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[10]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[11]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[12]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[13]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[14]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[15]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[16]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[17]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[18]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[19]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[20]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[21]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[22]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[23]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[24]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[25]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[26]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[27]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[28]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[29]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[30]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[31]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34]
|
||||
set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35]
|
||||
|
||||
#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
# These are some common settings that all DE1 boards might want to have
|
||||
# without having to be manually set each time
|
||||
#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
|
||||
set_global_assignment -name SMART_RECOMPILE ON
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
|
||||
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
|
||||
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "NORMAL COMPILATION"
|
||||
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "NORMAL COMPILATION"
|
||||
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
|
||||
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
|
||||
#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
# Quartus managed
|
||||
#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
set_global_assignment -name FAMILY "Cyclone II"
|
||||
set_global_assignment -name DEVICE EP2C20F484C7
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY toplevel
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:31:29 OCTOBER 13, 2014"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
|
||||
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
|
||||
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
||||
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
|
||||
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
|
||||
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
|
||||
|
||||
set_global_assignment -name SEARCH_PATH "../alu"
|
||||
set_global_assignment -name SEARCH_PATH "../bus"
|
||||
set_global_assignment -name SEARCH_PATH "../control"
|
||||
set_global_assignment -name SEARCH_PATH "../registers"
|
||||
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||
set_global_assignment -name BDF_FILE toplevel.bdf
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@@ -0,0 +1,43 @@
|
||||
//============================================================================
|
||||
// Z80 Top level interface
|
||||
//============================================================================
|
||||
`ifndef Z80_IFC
|
||||
`define Z80_IFC
|
||||
|
||||
`timescale 100 ns/ 100 ns
|
||||
|
||||
// Define set and clear for the negative logic pins
|
||||
`define CLR 1
|
||||
`define SET 0
|
||||
|
||||
interface z80_if (input logic CLK);
|
||||
logic nM1, nMREQ, nIORQ, nRD, nWR, nRFSH, nHALT, nBUSACK;
|
||||
logic nWAIT, nINT, nNMI, nRESET, nBUSRQ;
|
||||
logic [15:0] A;
|
||||
wire [7:0] D;
|
||||
|
||||
//=================================================
|
||||
// Modport for the CPU module (internal) interface
|
||||
// Also considered "design under test" port
|
||||
//=================================================
|
||||
modport dut (
|
||||
output nM1, nMREQ, nIORQ, nRD, nWR, nRFSH, nHALT, nBUSACK,
|
||||
input nWAIT, nINT, nNMI, nRESET, nBUSRQ,
|
||||
input CLK,
|
||||
output A,
|
||||
inout D);
|
||||
|
||||
//=================================================
|
||||
// Modport for the user (external) pin interface
|
||||
// Also considered a "test bench" port
|
||||
//=================================================
|
||||
modport tb (
|
||||
input nM1, nMREQ, nIORQ, nRD, nWR, nRFSH, nHALT, nBUSACK,
|
||||
output nWAIT, nINT, nNMI, nRESET, nBUSRQ,
|
||||
input CLK,
|
||||
input A,
|
||||
inout D);
|
||||
|
||||
endinterface : z80_if
|
||||
|
||||
`endif
|
||||
@@ -0,0 +1,85 @@
|
||||
//============================================================================
|
||||
// Z80 Top level using the direct module declaration
|
||||
//============================================================================
|
||||
`timescale 1us/ 100 ns
|
||||
|
||||
module z80_top_direct_n(
|
||||
output wire nM1,
|
||||
output wire nMREQ,
|
||||
output wire nIORQ,
|
||||
output wire nRD,
|
||||
output wire nWR,
|
||||
output wire nRFSH,
|
||||
output wire nHALT,
|
||||
output wire nBUSACK,
|
||||
|
||||
input wire nWAIT,
|
||||
input wire nINT,
|
||||
input wire nNMI,
|
||||
input wire nRESET,
|
||||
input wire nBUSRQ,
|
||||
|
||||
input wire CLK,
|
||||
output wire [15:0] A,
|
||||
inout wire [7:0] D
|
||||
);
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// Include core A-Z80 level connecting all internal modules
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
`include "core.vh"
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// Address, Data and Control bus drivers connecting to external pins
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
address_pins address_pins_(
|
||||
.clk (clk),
|
||||
.bus_ab_pin_we (bus_ab_pin_we),
|
||||
.pin_control_oe (pin_control_oe),
|
||||
.address (address),
|
||||
.abus (A)
|
||||
);
|
||||
|
||||
data_pins data_pins_(
|
||||
.bus_db_pin_oe (bus_db_pin_oe),
|
||||
.bus_db_pin_re (bus_db_pin_re),
|
||||
.ctl_bus_db_we (ctl_bus_db_we),
|
||||
.ctl_bus_db_oe (ctl_bus_db_oe),
|
||||
.clk (clk),
|
||||
.db (db0),
|
||||
.D (D)
|
||||
);
|
||||
|
||||
control_pins_n control_pins_(
|
||||
.busack (busack),
|
||||
.CPUCLK (CLK),
|
||||
.pin_control_oe(pin_control_oe),
|
||||
.in_halt (in_halt),
|
||||
.pin_nWAIT (nWAIT),
|
||||
.pin_nBUSRQ (nBUSRQ),
|
||||
.pin_nINT (nINT),
|
||||
.pin_nNMI (nNMI),
|
||||
.pin_nRESET (nRESET),
|
||||
.nM1_out (nM1_out),
|
||||
.nRFSH_out (nRFSH_out),
|
||||
.nRD_out (nRD_out),
|
||||
.nWR_out (nWR_out),
|
||||
.nIORQ_out (nIORQ_out),
|
||||
.nMREQ_out (nMREQ_out),
|
||||
.nmi (nmi),
|
||||
.busrq (busrq),
|
||||
.clk (clk),
|
||||
.intr (intr),
|
||||
.mwait (mwait),
|
||||
.reset_in (reset_in),
|
||||
.pin_nM1 (nM1),
|
||||
.pin_nMREQ (nMREQ),
|
||||
.pin_nIORQ (nIORQ),
|
||||
.pin_nRD (nRD),
|
||||
.pin_nWR (nWR),
|
||||
.pin_nRFSH (nRFSH),
|
||||
.pin_nHALT (nHALT),
|
||||
.pin_nBUSACK (nBUSACK)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,35 @@
|
||||
//============================================================================
|
||||
// Z80 Top level using the interface declaration
|
||||
//============================================================================
|
||||
`include "z80.svh"
|
||||
|
||||
module z80_top_ifc_n (z80_if.dut z80);
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// Include core A-Z80 level connecting all internal modules
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
`include "core.vh"
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// Address, Data and Control bus drivers connecting to external pins
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
address_pins address_pins_( .*, .abus(z80.A[15:0]) );
|
||||
data_pins data_pins_ ( .*, .db(db0[7:0]), .D(z80.D[7:0]) );
|
||||
control_pins_n control_pins_( .*,
|
||||
.pin_nM1 (z80.nM1),
|
||||
.pin_nMREQ (z80.nMREQ),
|
||||
.pin_nIORQ (z80.nIORQ),
|
||||
.pin_nRD (z80.nRD),
|
||||
.pin_nWR (z80.nWR),
|
||||
.pin_nRFSH (z80.nRFSH),
|
||||
.pin_nHALT (z80.nHALT),
|
||||
.pin_nWAIT (z80.nWAIT),
|
||||
.pin_nBUSACK (z80.nBUSACK),
|
||||
.pin_nINT (z80.nINT),
|
||||
.pin_nNMI (z80.nNMI),
|
||||
.pin_nRESET (z80.nRESET),
|
||||
.pin_nBUSRQ (z80.nBUSRQ),
|
||||
.CPUCLK (z80.CLK)
|
||||
);
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user