Fixed video, kbd and buzzer
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@@ -0,0 +1,120 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
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||||
(symbol
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||||
(rect 16 16 240 240)
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||||
(text "address_latch" (rect 5 0 86 14)(font "Arial" (font_size 8)))
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||||
(text "inst" (rect 8 208 25 220)(font "Arial" ))
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||||
(port
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||||
(pt 0 32)
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||||
(input)
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||||
(text "clrpc" (rect 0 0 28 14)(font "Arial" (font_size 8)))
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||||
(text "clrpc" (rect 21 27 49 41)(font "Arial" (font_size 8)))
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||||
(line (pt 0 32)(pt 16 32))
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||||
)
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||||
(port
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||||
(pt 0 48)
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||||
(input)
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||||
(text "ctl_bus_inc_oe" (rect 0 0 86 14)(font "Arial" (font_size 8)))
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||||
(text "ctl_bus_inc_oe" (rect 21 43 107 57)(font "Arial" (font_size 8)))
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||||
(line (pt 0 48)(pt 16 48))
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||||
)
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||||
(port
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||||
(pt 0 64)
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||||
(input)
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||||
(text "ctl_inc_limit6" (rect 0 0 70 14)(font "Arial" (font_size 8)))
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||||
(text "ctl_inc_limit6" (rect 21 59 91 73)(font "Arial" (font_size 8)))
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||||
(line (pt 0 64)(pt 16 64))
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||||
)
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||||
(port
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||||
(pt 0 80)
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||||
(input)
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||||
(text "ctl_inc_dec" (rect 0 0 64 14)(font "Arial" (font_size 8)))
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||||
(text "ctl_inc_dec" (rect 21 75 85 89)(font "Arial" (font_size 8)))
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||||
(line (pt 0 80)(pt 16 80))
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||||
)
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||||
(port
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||||
(pt 0 96)
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||||
(input)
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||||
(text "ctl_inc_cy" (rect 0 0 57 14)(font "Arial" (font_size 8)))
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||||
(text "ctl_inc_cy" (rect 21 91 78 105)(font "Arial" (font_size 8)))
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||||
(line (pt 0 96)(pt 16 96))
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||||
)
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||||
(port
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||||
(pt 0 112)
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||||
(input)
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||||
(text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8)))
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||||
(text "clk" (rect 21 107 36 121)(font "Arial" (font_size 8)))
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||||
(line (pt 0 112)(pt 16 112))
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||||
)
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||||
(port
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||||
(pt 0 128)
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||||
(input)
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||||
(text "ctl_al_we" (rect 0 0 55 14)(font "Arial" (font_size 8)))
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||||
(text "ctl_al_we" (rect 21 123 76 137)(font "Arial" (font_size 8)))
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||||
(line (pt 0 128)(pt 16 128))
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||||
)
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||||
(port
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||||
(pt 0 144)
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||||
(input)
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||||
(text "nreset" (rect 0 0 36 14)(font "Arial" (font_size 8)))
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||||
(text "nreset" (rect 21 139 57 153)(font "Arial" (font_size 8)))
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||||
(line (pt 0 144)(pt 16 144))
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||||
)
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||||
(port
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||||
(pt 0 160)
|
||||
(input)
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||||
(text "ctl_apin_mux2" (rect 0 0 81 14)(font "Arial" (font_size 8)))
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||||
(text "ctl_apin_mux2" (rect 21 155 102 169)(font "Arial" (font_size 8)))
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||||
(line (pt 0 160)(pt 16 160))
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||||
)
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||||
(port
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||||
(pt 0 176)
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||||
(input)
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||||
(text "ctl_apin_mux" (rect 0 0 74 14)(font "Arial" (font_size 8)))
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||||
(text "ctl_apin_mux" (rect 21 171 95 185)(font "Arial" (font_size 8)))
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||||
(line (pt 0 176)(pt 16 176))
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||||
)
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||||
(port
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||||
(pt 224 48)
|
||||
(output)
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||||
(text "address_is_1" (rect 0 0 77 14)(font "Arial" (font_size 8)))
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||||
(text "address_is_1" (rect 126 43 203 57)(font "Arial" (font_size 8)))
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||||
(line (pt 224 48)(pt 208 48))
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||||
)
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||||
(port
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||||
(pt 224 64)
|
||||
(output)
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||||
(text "address[15..0]" (rect 0 0 82 14)(font "Arial" (font_size 8)))
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||||
(text "address[15..0]" (rect 121 59 203 73)(font "Arial" (font_size 8)))
|
||||
(line (pt 224 64)(pt 208 64)(line_width 3))
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||||
)
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||||
(port
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||||
(pt 224 32)
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||||
(bidir)
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||||
(text "abus[15..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
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||||
(text "abus[15..0]" (rect 140 27 203 41)(font "Arial" (font_size 8)))
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||||
(line (pt 224 32)(pt 208 32)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 208 208))
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||||
)
|
||||
)
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||||
@@ -0,0 +1,128 @@
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||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// CREATED "Sat Feb 27 08:13:14 2016"
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module address_latch(
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ctl_inc_cy,
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ctl_inc_dec,
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ctl_al_we,
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ctl_inc_limit6,
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ctl_bus_inc_oe,
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clk,
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ctl_apin_mux,
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ctl_apin_mux2,
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clrpc,
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nreset,
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address_is_1,
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abus,
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address
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);
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input wire ctl_inc_cy;
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input wire ctl_inc_dec;
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input wire ctl_al_we;
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input wire ctl_inc_limit6;
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input wire ctl_bus_inc_oe;
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input wire clk;
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input wire ctl_apin_mux;
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input wire ctl_apin_mux2;
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input wire clrpc;
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input wire nreset;
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output wire address_is_1;
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inout wire [15:0] abus;
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output wire [15:0] address;
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wire [15:0] abusz;
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reg [15:0] Q;
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wire SYNTHESIZED_WIRE_0;
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wire SYNTHESIZED_WIRE_1;
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wire SYNTHESIZED_WIRE_2;
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wire [15:0] SYNTHESIZED_WIRE_7;
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wire SYNTHESIZED_WIRE_4;
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wire [15:0] SYNTHESIZED_WIRE_5;
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always@(posedge clk or negedge nreset)
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begin
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if (!nreset)
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begin
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Q[15:0] <= 16'b0000000000000000;
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end
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else
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if (ctl_al_we)
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begin
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Q[15:0] <= abusz[15:0];
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end
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end
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assign address_is_1 = ~(SYNTHESIZED_WIRE_0 | SYNTHESIZED_WIRE_1);
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assign abusz = {SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2} & abus;
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assign abus[15] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[15] : 1'bz;
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assign abus[14] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[14] : 1'bz;
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assign abus[13] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[13] : 1'bz;
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assign abus[12] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[12] : 1'bz;
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assign abus[11] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[11] : 1'bz;
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assign abus[10] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[10] : 1'bz;
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assign abus[9] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[9] : 1'bz;
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assign abus[8] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[8] : 1'bz;
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assign abus[7] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[7] : 1'bz;
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assign abus[6] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[6] : 1'bz;
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assign abus[5] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[5] : 1'bz;
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assign abus[4] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[4] : 1'bz;
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assign abus[3] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[3] : 1'bz;
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assign abus[2] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[2] : 1'bz;
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assign abus[1] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[1] : 1'bz;
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assign abus[0] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[0] : 1'bz;
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assign SYNTHESIZED_WIRE_0 = Q[7] | Q[5] | Q[6] | Q[4] | Q[2] | Q[3] | Q[1] | SYNTHESIZED_WIRE_4;
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assign SYNTHESIZED_WIRE_1 = Q[15] | Q[13] | Q[14] | Q[12] | Q[10] | Q[11] | Q[9] | Q[8];
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address_mux b2v_inst7(
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.select(ctl_apin_mux2),
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.in0(SYNTHESIZED_WIRE_5),
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.in1(Q),
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.out(address));
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assign SYNTHESIZED_WIRE_2 = ~clrpc;
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inc_dec b2v_inst_inc_dec(
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.limit6(ctl_inc_limit6),
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.decrement(ctl_inc_dec),
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.carry_in(ctl_inc_cy),
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.d(Q),
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.address(SYNTHESIZED_WIRE_7));
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||||
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||||
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||||
address_mux b2v_mux(
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.select(ctl_apin_mux),
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.in0(abusz),
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.in1(SYNTHESIZED_WIRE_7),
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.out(SYNTHESIZED_WIRE_5));
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assign SYNTHESIZED_WIRE_4 = ~Q[0];
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||||
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||||
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||||
endmodule
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||||
@@ -0,0 +1,292 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "graphic" (version "1.4"))
|
||||
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|
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|
||||
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)
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)
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|
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(bus)
|
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)
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|
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(pt 416 88)
|
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(pt 432 88)
|
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(bus)
|
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)
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(junction (pt 240 176))
|
||||
(title_block
|
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(rect 32 240 289 292)
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(name "title-custom-small")
|
||||
(section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border))
|
||||
(section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "address_mux" (rect 43 2 136 17)(font "Arial" (font_size 9)(bold)))(border))
|
||||
(section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border))
|
||||
(section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "November 8, 2014" (rect 56 3 159 17)(font "Arial" (font_size 8)))(border))
|
||||
(section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.0" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border))
|
||||
(drawing
|
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)
|
||||
)
|
||||
@@ -0,0 +1,62 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
(rect 64 64 152 208)
|
||||
(text "address_mux" (rect 5 0 82 14)(font "Arial" (font_size 8)))
|
||||
(text "inst" (rect 0 128 17 140)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "in1[15..0]" (rect 0 0 51 14)(font "Arial" (font_size 8)))
|
||||
(text "in1[15..0]" (rect 21 27 72 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32)(line_width 3))
|
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)
|
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(port
|
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(pt 0 72)
|
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(input)
|
||||
(text "in0[15..0]" (rect 0 0 51 14)(font "Arial" (font_size 8)))
|
||||
(text "in0[15..0]" (rect 21 67 72 81)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 16 72)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 120)
|
||||
(input)
|
||||
(text "select" (rect 0 0 34 14)(font "Arial" (font_size 8)))
|
||||
(text "select" (rect 5 99 39 113)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 120)(pt 16 120))
|
||||
)
|
||||
(port
|
||||
(pt 88 56)
|
||||
(output)
|
||||
(text "out[15..0]" (rect -72 0 -19 14)(font "Arial" (font_size 8)))
|
||||
(text "out[15..0]" (rect 24 48 77 62)(font "Arial" (font_size 8)))
|
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(line (pt 48 120)(pt 48 80))
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,48 @@
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Sat Nov 08 09:37:58 2014"
|
||||
|
||||
module address_mux(
|
||||
select,
|
||||
in0,
|
||||
in1,
|
||||
out
|
||||
);
|
||||
|
||||
|
||||
input wire select;
|
||||
input wire [15:0] in0;
|
||||
input wire [15:0] in1;
|
||||
output wire [15:0] out;
|
||||
|
||||
wire SYNTHESIZED_WIRE_0;
|
||||
wire [15:0] SYNTHESIZED_WIRE_1;
|
||||
wire [15:0] SYNTHESIZED_WIRE_2;
|
||||
|
||||
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_1 = in0 & {SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0};
|
||||
|
||||
assign SYNTHESIZED_WIRE_2 = in1 & {select,select,select,select,select,select,select,select,select,select,select,select,select,select,select,select};
|
||||
|
||||
assign SYNTHESIZED_WIRE_0 = ~select;
|
||||
|
||||
assign out = SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,261 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "graphic" (version "1.4"))
|
||||
(pin
|
||||
(input)
|
||||
(rect 40 80 216 96)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "address[15..0]" (rect 9 0 79 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
)
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(pt 176 8)
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
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|
||||
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|
||||
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|
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|
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|
||||
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|
||||
(rect 480 72 528 104)
|
||||
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|
||||
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|
||||
(port
|
||||
(pt 0 16)
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(text "OE" (rect 26 0 37 12)(font "Courier New" (bold))(invisible))
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(line (pt 14 25)(pt 14 7))
|
||||
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|
||||
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|
||||
)
|
||||
)
|
||||
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|
||||
(rect 312 64 376 144)
|
||||
(text "DFFE" (rect 1 0 25 10)(font "Arial" (font_size 6)))
|
||||
(text "apin_latch" (rect 3 68 52 80)(font "Arial" ))
|
||||
(port
|
||||
(pt 32 0)
|
||||
(input)
|
||||
(text "PRN" (rect 24 13 41 25)(font "Courier New" (bold)))
|
||||
(text "PRN" (rect 24 11 41 23)(font "Courier New" (bold)))
|
||||
(line (pt 32 4)(pt 32 0))
|
||||
)
|
||||
(port
|
||||
(pt 32 80)
|
||||
(input)
|
||||
(text "CLRN" (rect 21 59 44 71)(font "Courier New" (bold)))
|
||||
(text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold)))
|
||||
(line (pt 32 80)(pt 32 76))
|
||||
)
|
||||
(port
|
||||
(pt 0 24)
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
)
|
||||
(port
|
||||
(pt 0 40)
|
||||
(input)
|
||||
(text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible))
|
||||
(text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 0 40)(pt 12 40))
|
||||
)
|
||||
(port
|
||||
(pt 0 56)
|
||||
(input)
|
||||
(text "ENA" (rect 14 50 31 62)(font "Courier New" (bold)))
|
||||
(text "ENA" (rect 14 50 31 62)(font "Courier New" (bold)))
|
||||
(line (pt 0 56)(pt 12 56))
|
||||
)
|
||||
(port
|
||||
(pt 64 24)
|
||||
(output)
|
||||
(text "Q" (rect 44 20 49 32)(font "Courier New" (bold)))
|
||||
(text "Q" (rect 44 20 48 32)(font "Courier New" (bold)))
|
||||
(line (pt 53 24)(pt 64 24))
|
||||
)
|
||||
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|
||||
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|
||||
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|
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|
||||
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|
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|
||||
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|
||||
(circle (rect 28 4 36 12))
|
||||
(circle (rect 28 68 36 76))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 240 88 288 120)
|
||||
(text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6)))
|
||||
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|
||||
(port
|
||||
(pt 0 16)
|
||||
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|
||||
(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
|
||||
(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 0 16)(pt 13 16))
|
||||
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|
||||
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|
||||
(pt 48 16)
|
||||
(output)
|
||||
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
(circle (rect 31 12 39 20))
|
||||
)
|
||||
)
|
||||
(connector
|
||||
(pt 216 88)
|
||||
(pt 312 88)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 216 120)
|
||||
(pt 312 120)
|
||||
)
|
||||
(connector
|
||||
(pt 504 40)
|
||||
(pt 504 72)
|
||||
)
|
||||
(connector
|
||||
(pt 216 40)
|
||||
(pt 504 40)
|
||||
)
|
||||
(connector
|
||||
(pt 376 88)
|
||||
(pt 480 88)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 528 88)
|
||||
(pt 568 88)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 216 104)
|
||||
(pt 240 104)
|
||||
)
|
||||
(connector
|
||||
(pt 288 104)
|
||||
(pt 312 104)
|
||||
)
|
||||
(text "Repeated 16 times, once for each address pin." (rect 472 144 738 158)(font "Arial" (font_size 8)))
|
||||
(title_block
|
||||
(rect 40 184 297 236)
|
||||
(name "title-custom-small")
|
||||
(section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border))
|
||||
(section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "address_pins" (rect 43 2 135 17)(font "Arial" (font_size 9)(bold)))(border))
|
||||
(section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border))
|
||||
(section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "June 14, 2014" (rect 56 3 136 17)(font "Arial" (font_size 8)))(border))
|
||||
(section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.3" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border))
|
||||
(drawing
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,64 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
(rect 16 16 224 144)
|
||||
(text "address_pins" (rect 5 0 82 14)(font "Arial" (font_size 8)))
|
||||
(text "inst" (rect 8 112 25 124)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "pin_control_oe" (rect 0 0 83 14)(font "Arial" (font_size 8)))
|
||||
(text "pin_control_oe" (rect 21 27 104 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "address[15..0]" (rect 0 0 82 14)(font "Arial" (font_size 8)))
|
||||
(text "address[15..0]" (rect 21 43 103 57)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 48)(pt 16 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8)))
|
||||
(text "clk" (rect 21 59 36 73)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 64)(pt 16 64))
|
||||
)
|
||||
(port
|
||||
(pt 0 80)
|
||||
(input)
|
||||
(text "bus_ab_pin_we" (rect 0 0 92 14)(font "Arial" (font_size 8)))
|
||||
(text "bus_ab_pin_we" (rect 21 75 113 89)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 80)(pt 16 80))
|
||||
)
|
||||
(port
|
||||
(pt 208 32)
|
||||
(output)
|
||||
(text "abus[15..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
|
||||
(text "abus[15..0]" (rect 124 27 187 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 208 32)(pt 192 32)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 192 112))
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,69 @@
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Sun Nov 16 16:56:05 2014"
|
||||
|
||||
module address_pins(
|
||||
clk,
|
||||
bus_ab_pin_we,
|
||||
pin_control_oe,
|
||||
address,
|
||||
abus
|
||||
);
|
||||
|
||||
|
||||
input wire clk;
|
||||
input wire bus_ab_pin_we;
|
||||
input wire pin_control_oe;
|
||||
input wire [15:0] address;
|
||||
output wire [15:0] abus;
|
||||
|
||||
wire SYNTHESIZED_WIRE_0;
|
||||
reg [15:0] DFFE_apin_latch;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_0)
|
||||
begin
|
||||
if (bus_ab_pin_we)
|
||||
begin
|
||||
DFFE_apin_latch[15:0] <= address[15:0];
|
||||
end
|
||||
end
|
||||
|
||||
assign abus[15] = pin_control_oe ? DFFE_apin_latch[15] : 1'bz;
|
||||
assign abus[14] = pin_control_oe ? DFFE_apin_latch[14] : 1'bz;
|
||||
assign abus[13] = pin_control_oe ? DFFE_apin_latch[13] : 1'bz;
|
||||
assign abus[12] = pin_control_oe ? DFFE_apin_latch[12] : 1'bz;
|
||||
assign abus[11] = pin_control_oe ? DFFE_apin_latch[11] : 1'bz;
|
||||
assign abus[10] = pin_control_oe ? DFFE_apin_latch[10] : 1'bz;
|
||||
assign abus[9] = pin_control_oe ? DFFE_apin_latch[9] : 1'bz;
|
||||
assign abus[8] = pin_control_oe ? DFFE_apin_latch[8] : 1'bz;
|
||||
assign abus[7] = pin_control_oe ? DFFE_apin_latch[7] : 1'bz;
|
||||
assign abus[6] = pin_control_oe ? DFFE_apin_latch[6] : 1'bz;
|
||||
assign abus[5] = pin_control_oe ? DFFE_apin_latch[5] : 1'bz;
|
||||
assign abus[4] = pin_control_oe ? DFFE_apin_latch[4] : 1'bz;
|
||||
assign abus[3] = pin_control_oe ? DFFE_apin_latch[3] : 1'bz;
|
||||
assign abus[2] = pin_control_oe ? DFFE_apin_latch[2] : 1'bz;
|
||||
assign abus[1] = pin_control_oe ? DFFE_apin_latch[1] : 1'bz;
|
||||
assign abus[0] = pin_control_oe ? DFFE_apin_latch[0] : 1'bz;
|
||||
|
||||
assign SYNTHESIZED_WIRE_0 = ~clk;
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,243 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "graphic" (version "1.4"))
|
||||
(pin
|
||||
(input)
|
||||
(rect 32 64 208 80)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "ctl_bus_ff_oe" (rect 9 0 77 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
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|
||||
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|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
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|
||||
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|
||||
(rect 32 48 208 64)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
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|
||||
(pt 176 8)
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
)
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
)
|
||||
(symbol
|
||||
(rect 512 128 560 160)
|
||||
(text "TRI" (rect 1 0 16 10)(font "Arial" (font_size 6)))
|
||||
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|
||||
(port
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
)
|
||||
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|
||||
(pt 24 0)
|
||||
(input)
|
||||
(text "OE" (rect 26 0 37 12)(font "Courier New" (bold))(invisible))
|
||||
(text "OE" (rect 26 0 37 12)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 24 12)(pt 24 0))
|
||||
)
|
||||
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|
||||
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|
||||
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|
||||
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
|
||||
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|
||||
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|
||||
)
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
)
|
||||
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|
||||
(rect 304 120 368 168)
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
)
|
||||
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|
||||
(rect 304 40 368 88)
|
||||
(text "OR2" (rect 1 0 19 10)(font "Arial" (font_size 6)))
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36))
|
||||
)
|
||||
)
|
||||
(connector
|
||||
(pt 600 144)
|
||||
(pt 560 144)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 208 56)
|
||||
(pt 304 56)
|
||||
)
|
||||
(connector
|
||||
(pt 304 136)
|
||||
(pt 232 136)
|
||||
)
|
||||
(connector
|
||||
(pt 232 72)
|
||||
(pt 232 136)
|
||||
)
|
||||
(connector
|
||||
(text "bus[7..0]" (rect 387 128 430 140)(font "Arial" ))
|
||||
(pt 368 144)
|
||||
(pt 512 144)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "vcc[7..0]" (rect 190 136 234 148)(font "Arial" ))
|
||||
(pt 304 152)
|
||||
(pt 160 152)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 368 64)
|
||||
(pt 536 64)
|
||||
)
|
||||
(connector
|
||||
(pt 160 136)
|
||||
(pt 160 152)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 208 72)
|
||||
(pt 232 72)
|
||||
)
|
||||
(connector
|
||||
(pt 232 72)
|
||||
(pt 304 72)
|
||||
)
|
||||
(connector
|
||||
(pt 536 64)
|
||||
(pt 536 128)
|
||||
)
|
||||
(junction (pt 232 72))
|
||||
(title_block
|
||||
(rect 32 208 289 260)
|
||||
(name "title-custom-small")
|
||||
(section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "August 17, 2014, 2016" (rect 56 3 185 17)(font "Arial" (font_size 8)))(border))
|
||||
(section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border))
|
||||
(section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "bus_control" (rect 43 2 123 17)(font "Arial" (font_size 9)(bold)))(border))
|
||||
(section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border))
|
||||
(section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.3" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border))
|
||||
(drawing
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,50 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
(rect 16 16 208 112)
|
||||
(text "bus_control" (rect 5 0 72 14)(font "Arial" (font_size 8)))
|
||||
(text "inst" (rect 8 80 25 92)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "ctl_bus_zero_oe" (rect 0 0 95 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_bus_zero_oe" (rect 21 27 116 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "ctl_bus_ff_oe" (rect 0 0 79 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_bus_ff_oe" (rect 21 43 100 57)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 48)(pt 16 48))
|
||||
)
|
||||
(port
|
||||
(pt 192 32)
|
||||
(bidir)
|
||||
(text "db[7..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
|
||||
(text "db[7..0]" (rect 129 27 171 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 192 32)(pt 176 32)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 176 80))
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,53 @@
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Fri Feb 26 22:25:37 2016"
|
||||
|
||||
module bus_control(
|
||||
ctl_bus_ff_oe,
|
||||
ctl_bus_zero_oe,
|
||||
db
|
||||
);
|
||||
|
||||
|
||||
input wire ctl_bus_ff_oe;
|
||||
input wire ctl_bus_zero_oe;
|
||||
inout wire [7:0] db;
|
||||
|
||||
wire [7:0] bus;
|
||||
wire [7:0] vcc;
|
||||
wire SYNTHESIZED_WIRE_0;
|
||||
|
||||
|
||||
|
||||
|
||||
assign db[7] = SYNTHESIZED_WIRE_0 ? bus[7] : 1'bz;
|
||||
assign db[6] = SYNTHESIZED_WIRE_0 ? bus[6] : 1'bz;
|
||||
assign db[5] = SYNTHESIZED_WIRE_0 ? bus[5] : 1'bz;
|
||||
assign db[4] = SYNTHESIZED_WIRE_0 ? bus[4] : 1'bz;
|
||||
assign db[3] = SYNTHESIZED_WIRE_0 ? bus[3] : 1'bz;
|
||||
assign db[2] = SYNTHESIZED_WIRE_0 ? bus[2] : 1'bz;
|
||||
assign db[1] = SYNTHESIZED_WIRE_0 ? bus[1] : 1'bz;
|
||||
assign db[0] = SYNTHESIZED_WIRE_0 ? bus[0] : 1'bz;
|
||||
|
||||
|
||||
assign bus = {ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe} & vcc;
|
||||
|
||||
assign SYNTHESIZED_WIRE_0 = ctl_bus_ff_oe | ctl_bus_zero_oe;
|
||||
|
||||
assign vcc = 8'b11111111;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,99 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 16 16 288 160)
|
||||
(text "bus_switch" (rect 5 0 48 12)(font "Arial" ))
|
||||
(text "inst" (rect 8 128 20 140)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "ctl_sw_1u" (rect 0 0 38 12)(font "Arial" ))
|
||||
(text "ctl_sw_1u" (rect 21 27 59 39)(font "Arial" ))
|
||||
(line (pt 0 32)(pt 16 32)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "ctl_sw_1d" (rect 0 0 38 12)(font "Arial" ))
|
||||
(text "ctl_sw_1d" (rect 21 43 59 55)(font "Arial" ))
|
||||
(line (pt 0 48)(pt 16 48)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "ctl_sw_2u" (rect 0 0 40 12)(font "Arial" ))
|
||||
(text "ctl_sw_2u" (rect 21 59 61 71)(font "Arial" ))
|
||||
(line (pt 0 64)(pt 16 64)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 80)
|
||||
(input)
|
||||
(text "ctl_sw_2d" (rect 0 0 40 12)(font "Arial" ))
|
||||
(text "ctl_sw_2d" (rect 21 75 61 87)(font "Arial" ))
|
||||
(line (pt 0 80)(pt 16 80)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "ctl_sw_mask543_en" (rect 0 0 83 12)(font "Arial" ))
|
||||
(text "ctl_sw_mask543_en" (rect 21 91 104 103)(font "Arial" ))
|
||||
(line (pt 0 96)(pt 16 96)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 272 32)
|
||||
(output)
|
||||
(text "bus_sw_1u" (rect 0 0 44 12)(font "Arial" ))
|
||||
(text "bus_sw_1u" (rect 207 27 251 39)(font "Arial" ))
|
||||
(line (pt 272 32)(pt 256 32)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 272 48)
|
||||
(output)
|
||||
(text "bus_sw_1d" (rect 0 0 44 12)(font "Arial" ))
|
||||
(text "bus_sw_1d" (rect 207 43 251 55)(font "Arial" ))
|
||||
(line (pt 272 48)(pt 256 48)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 272 64)
|
||||
(output)
|
||||
(text "bus_sw_2u" (rect 0 0 46 12)(font "Arial" ))
|
||||
(text "bus_sw_2u" (rect 205 59 251 71)(font "Arial" ))
|
||||
(line (pt 272 64)(pt 256 64)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 272 80)
|
||||
(output)
|
||||
(text "bus_sw_2d" (rect 0 0 46 12)(font "Arial" ))
|
||||
(text "bus_sw_2d" (rect 205 75 251 87)(font "Arial" ))
|
||||
(line (pt 272 80)(pt 256 80)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 272 96)
|
||||
(output)
|
||||
(text "bus_sw_mask543_en" (rect 0 0 89 12)(font "Arial" ))
|
||||
(text "bus_sw_mask543_en" (rect 162 91 251 103)(font "Arial" ))
|
||||
(line (pt 272 96)(pt 256 96)(line_width 1))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 256 128)(line_width 1))
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,41 @@
|
||||
//============================================================================
|
||||
// Bus switch in bus A-Z80 CPU
|
||||
//
|
||||
// Copyright 2014, 2016 Goran Devic
|
||||
//
|
||||
// This module provides control data bus switch signals. The sole purpose of
|
||||
// having these wires defined in this module is to get all control signals
|
||||
// (which are processed by genglobals.py) to appear in the list of global
|
||||
// control signals ("globals.vh") for consistency.
|
||||
//============================================================================
|
||||
|
||||
module bus_switch
|
||||
(
|
||||
input wire ctl_sw_1u, // Control input for the SW1 upstream
|
||||
input wire ctl_sw_1d, // Control input for the SW1 downstream
|
||||
|
||||
input wire ctl_sw_2u, // Control input for the SW2 upstream
|
||||
input wire ctl_sw_2d, // Control input for the SW2 downstream
|
||||
|
||||
input wire ctl_sw_mask543_en, // Enables masking [5:3] on the data bus switch 1
|
||||
|
||||
//--------------------------------------------------------------------
|
||||
|
||||
output wire bus_sw_1u, // SW1 upstream
|
||||
output wire bus_sw_1d, // SW1 downstream
|
||||
|
||||
output wire bus_sw_2u, // SW2 upstream
|
||||
output wire bus_sw_2d, // SW2 downstream
|
||||
|
||||
output wire bus_sw_mask543_en // Affects SW1 downstream
|
||||
);
|
||||
|
||||
assign bus_sw_1u = ctl_sw_1u;
|
||||
assign bus_sw_1d = ctl_sw_1d;
|
||||
|
||||
assign bus_sw_2u = ctl_sw_2u;
|
||||
assign bus_sw_2d = ctl_sw_2d;
|
||||
|
||||
assign bus_sw_mask543_en = ctl_sw_mask543_en;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,963 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "graphic" (version "1.4"))
|
||||
(pin
|
||||
(input)
|
||||
(rect 32 472 208 488)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "busack" (rect 9 0 44 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 456 512 632 528)
|
||||
(text "INPUT" (rect 15 0 43 10)(font "Arial" (font_size 6)))
|
||||
(text "CPUCLK" (rect 123 0 167 12)(font "Arial" ))
|
||||
(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 59 12))
|
||||
(line (pt 84 4)(pt 59 4))
|
||||
(line (pt 55 8)(pt 0 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 59 4)(pt 55 8))
|
||||
(line (pt 59 12)(pt 55 8))
|
||||
)
|
||||
(flipy)
|
||||
(text "VCC" (rect 20 7 40 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 32 80 208 96)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "pin_control_oe" (rect 9 0 79 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 32 344 208 360)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "in_halt" (rect 9 0 40 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 456 392 632 408)
|
||||
(text "INPUT" (rect 15 0 43 10)(font "Arial" (font_size 6)))
|
||||
(text "pin_nWAIT" (rect 114 0 167 12)(font "Arial" ))
|
||||
(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 59 12))
|
||||
(line (pt 84 4)(pt 59 4))
|
||||
(line (pt 55 8)(pt 0 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 59 4)(pt 55 8))
|
||||
(line (pt 59 12)(pt 55 8))
|
||||
)
|
||||
(flipy)
|
||||
(text "VCC" (rect 20 7 40 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 456 432 632 448)
|
||||
(text "INPUT" (rect 15 0 43 10)(font "Arial" (font_size 6)))
|
||||
(text "pin_nBUSRQ" (rect 103 0 167 12)(font "Arial" ))
|
||||
(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 59 12))
|
||||
(line (pt 84 4)(pt 59 4))
|
||||
(line (pt 55 8)(pt 0 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 59 4)(pt 55 8))
|
||||
(line (pt 59 12)(pt 55 8))
|
||||
)
|
||||
(flipy)
|
||||
(text "VCC" (rect 20 7 40 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 456 552 632 568)
|
||||
(text "INPUT" (rect 15 0 43 10)(font "Arial" (font_size 6)))
|
||||
(text "pin_nINT" (rect 124 0 167 12)(font "Arial" ))
|
||||
(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 59 12))
|
||||
(line (pt 84 4)(pt 59 4))
|
||||
(line (pt 55 8)(pt 0 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 59 4)(pt 55 8))
|
||||
(line (pt 59 12)(pt 55 8))
|
||||
)
|
||||
(flipy)
|
||||
(text "VCC" (rect 20 7 40 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 456 584 632 600)
|
||||
(text "INPUT" (rect 15 0 43 10)(font "Arial" (font_size 6)))
|
||||
(text "pin_nNMI" (rect 121 0 167 12)(font "Arial" ))
|
||||
(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 59 12))
|
||||
(line (pt 84 4)(pt 59 4))
|
||||
(line (pt 55 8)(pt 0 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 59 4)(pt 55 8))
|
||||
(line (pt 59 12)(pt 55 8))
|
||||
)
|
||||
(flipy)
|
||||
(text "VCC" (rect 20 7 40 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 456 624 632 640)
|
||||
(text "INPUT" (rect 15 0 43 10)(font "Arial" (font_size 6)))
|
||||
(text "pin_nRESET" (rect 106 0 167 12)(font "Arial" ))
|
||||
(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 59 12))
|
||||
(line (pt 84 4)(pt 59 4))
|
||||
(line (pt 55 8)(pt 0 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 59 4)(pt 55 8))
|
||||
(line (pt 59 12)(pt 55 8))
|
||||
)
|
||||
(flipy)
|
||||
(text "VCC" (rect 20 7 40 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 32 40 208 56)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "nM1_out" (rect 9 0 50 12)(font "Arial" ))
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||||
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@@ -0,0 +1,232 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
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||||
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||||
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|
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|
||||
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|
||||
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||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
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|
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|
||||
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|
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|
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||||
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|
||||
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|
||||
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|
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
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|
||||
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|
||||
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|
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|
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|
||||
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|
||||
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|
||||
(text "pin_nM1" (rect 0 0 47 14)(font "Arial" (font_size 8)))
|
||||
(text "pin_nM1" (rect 148 27 195 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 32)(pt 200 32))
|
||||
)
|
||||
(port
|
||||
(pt 216 48)
|
||||
(output)
|
||||
(text "pin_nMREQ" (rect 0 0 64 14)(font "Arial" (font_size 8)))
|
||||
(text "pin_nMREQ" (rect 131 43 195 57)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 48)(pt 200 48))
|
||||
)
|
||||
(port
|
||||
(pt 216 64)
|
||||
(output)
|
||||
(text "pin_nIORQ" (rect 0 0 60 14)(font "Arial" (font_size 8)))
|
||||
(text "pin_nIORQ" (rect 135 59 195 73)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 64)(pt 200 64))
|
||||
)
|
||||
(port
|
||||
(pt 216 80)
|
||||
(output)
|
||||
(text "pin_nRD" (rect 0 0 47 14)(font "Arial" (font_size 8)))
|
||||
(text "pin_nRD" (rect 148 75 195 89)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 80)(pt 200 80))
|
||||
)
|
||||
(port
|
||||
(pt 216 96)
|
||||
(output)
|
||||
(text "pin_nWR" (rect 0 0 50 14)(font "Arial" (font_size 8)))
|
||||
(text "pin_nWR" (rect 145 91 195 105)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 96)(pt 200 96))
|
||||
)
|
||||
(port
|
||||
(pt 216 112)
|
||||
(output)
|
||||
(text "pin_nRFSH" (rect 0 0 62 14)(font "Arial" (font_size 8)))
|
||||
(text "pin_nRFSH" (rect 133 107 195 121)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 112)(pt 200 112))
|
||||
)
|
||||
(port
|
||||
(pt 216 128)
|
||||
(output)
|
||||
(text "pin_nHALT" (rect 0 0 62 14)(font "Arial" (font_size 8)))
|
||||
(text "pin_nHALT" (rect 133 123 195 137)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 128)(pt 200 128))
|
||||
)
|
||||
(port
|
||||
(pt 216 144)
|
||||
(output)
|
||||
(text "mwait" (rect 0 0 34 14)(font "Arial" (font_size 8)))
|
||||
(text "mwait" (rect 161 139 195 153)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 144)(pt 200 144))
|
||||
)
|
||||
(port
|
||||
(pt 216 160)
|
||||
(output)
|
||||
(text "busrq" (rect 0 0 33 14)(font "Arial" (font_size 8)))
|
||||
(text "busrq" (rect 162 155 195 169)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 160)(pt 200 160))
|
||||
)
|
||||
(port
|
||||
(pt 216 176)
|
||||
(output)
|
||||
(text "pin_nBUSACK" (rect 0 0 81 14)(font "Arial" (font_size 8)))
|
||||
(text "pin_nBUSACK" (rect 114 171 195 185)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 176)(pt 200 176))
|
||||
)
|
||||
(port
|
||||
(pt 216 192)
|
||||
(output)
|
||||
(text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8)))
|
||||
(text "clk" (rect 180 187 195 201)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 192)(pt 200 192))
|
||||
)
|
||||
(port
|
||||
(pt 216 208)
|
||||
(output)
|
||||
(text "intr" (rect 0 0 17 14)(font "Arial" (font_size 8)))
|
||||
(text "intr" (rect 178 203 195 217)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 208)(pt 200 208))
|
||||
)
|
||||
(port
|
||||
(pt 216 224)
|
||||
(output)
|
||||
(text "nmi" (rect 0 0 18 14)(font "Arial" (font_size 8)))
|
||||
(text "nmi" (rect 177 219 195 233)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 224)(pt 200 224))
|
||||
)
|
||||
(port
|
||||
(pt 216 240)
|
||||
(output)
|
||||
(text "reset_in" (rect 0 0 46 14)(font "Arial" (font_size 8)))
|
||||
(text "reset_in" (rect 149 235 195 249)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 240)(pt 200 240))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 200 272))
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,112 @@
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Sun Nov 16 23:06:14 2014"
|
||||
|
||||
module control_pins_n(
|
||||
busack,
|
||||
CPUCLK,
|
||||
pin_control_oe,
|
||||
in_halt,
|
||||
pin_nWAIT,
|
||||
pin_nBUSRQ,
|
||||
pin_nINT,
|
||||
pin_nNMI,
|
||||
pin_nRESET,
|
||||
nM1_out,
|
||||
nRFSH_out,
|
||||
nRD_out,
|
||||
nWR_out,
|
||||
nIORQ_out,
|
||||
nMREQ_out,
|
||||
nmi,
|
||||
busrq,
|
||||
clk,
|
||||
intr,
|
||||
mwait,
|
||||
reset_in,
|
||||
pin_nM1,
|
||||
pin_nMREQ,
|
||||
pin_nIORQ,
|
||||
pin_nRD,
|
||||
pin_nWR,
|
||||
pin_nRFSH,
|
||||
pin_nHALT,
|
||||
pin_nBUSACK
|
||||
);
|
||||
|
||||
|
||||
input wire busack;
|
||||
input wire CPUCLK;
|
||||
input wire pin_control_oe;
|
||||
input wire in_halt;
|
||||
input wire pin_nWAIT;
|
||||
input wire pin_nBUSRQ;
|
||||
input wire pin_nINT;
|
||||
input wire pin_nNMI;
|
||||
input wire pin_nRESET;
|
||||
input wire nM1_out;
|
||||
input wire nRFSH_out;
|
||||
input wire nRD_out;
|
||||
input wire nWR_out;
|
||||
input wire nIORQ_out;
|
||||
input wire nMREQ_out;
|
||||
output wire nmi;
|
||||
output wire busrq;
|
||||
output wire clk;
|
||||
output wire intr;
|
||||
output wire mwait;
|
||||
output wire reset_in;
|
||||
output wire pin_nM1;
|
||||
output wire pin_nMREQ;
|
||||
output wire pin_nIORQ;
|
||||
output wire pin_nRD;
|
||||
output wire pin_nWR;
|
||||
output wire pin_nRFSH;
|
||||
output wire pin_nHALT;
|
||||
output wire pin_nBUSACK;
|
||||
|
||||
|
||||
assign clk = CPUCLK;
|
||||
assign pin_nM1 = nM1_out;
|
||||
assign pin_nRFSH = nRFSH_out;
|
||||
|
||||
|
||||
|
||||
assign pin_nMREQ = pin_control_oe ? nMREQ_out : 1'bz;
|
||||
|
||||
assign pin_nIORQ = pin_control_oe ? nIORQ_out : 1'bz;
|
||||
|
||||
assign pin_nRD = pin_control_oe ? nRD_out : 1'bz;
|
||||
|
||||
assign pin_nWR = pin_control_oe ? nWR_out : 1'bz;
|
||||
|
||||
assign busrq = ~pin_nBUSRQ;
|
||||
|
||||
assign pin_nHALT = ~in_halt;
|
||||
|
||||
assign mwait = ~pin_nWAIT;
|
||||
|
||||
assign pin_nBUSACK = ~busack;
|
||||
|
||||
assign intr = ~pin_nINT;
|
||||
|
||||
assign nmi = ~pin_nNMI;
|
||||
|
||||
assign reset_in = ~pin_nRESET;
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,612 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "graphic" (version "1.4"))
|
||||
(pin
|
||||
(input)
|
||||
(rect 24 32 200 48)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "bus_db_pin_oe" (rect 9 0 82 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 24 200 200 216)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "bus_db_pin_re" (rect 9 0 79 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 24 216 200 232)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "ctl_bus_db_we" (rect 9 0 80 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 24 168 200 184)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "clk" (rect 9 0 23 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 24 256 200 272)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "ctl_bus_db_oe" (rect 9 0 79 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(bidir)
|
||||
(rect 728 176 904 192)
|
||||
(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
|
||||
(text "D[7..0]" (rect 90 0 124 12)(font "Arial" ))
|
||||
(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 56 4)(pt 78 4))
|
||||
(line (pt 0 8)(pt 52 8))
|
||||
(line (pt 56 12)(pt 78 12))
|
||||
(line (pt 78 4)(pt 82 8))
|
||||
(line (pt 78 12)(pt 82 8))
|
||||
(line (pt 56 4)(pt 52 8))
|
||||
(line (pt 52 8)(pt 56 12))
|
||||
)
|
||||
(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(bidir)
|
||||
(rect 24 288 200 304)
|
||||
(text "BIDIR" (rect 151 6 175 16)(font "Arial" (font_size 6)))
|
||||
(text "db[7..0]" (rect 49 4 86 16)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 120 12)(pt 98 12))
|
||||
(line (pt 176 8)(pt 124 8))
|
||||
(line (pt 120 4)(pt 98 4))
|
||||
(line (pt 98 12)(pt 94 8))
|
||||
(line (pt 98 4)(pt 94 8))
|
||||
(line (pt 120 12)(pt 124 8))
|
||||
(line (pt 124 8)(pt 120 4))
|
||||
)
|
||||
(rotate180)
|
||||
(text "VCC" (rect 152 -1 172 9)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(symbol
|
||||
(rect 320 56 384 104)
|
||||
(text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
|
||||
(text "inst0" (rect 3 37 26 49)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 16)
|
||||
(input)
|
||||
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
|
||||
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 0 16)(pt 14 16))
|
||||
)
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
|
||||
(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 0 32)(pt 14 32))
|
||||
)
|
||||
(port
|
||||
(pt 64 24)
|
||||
(output)
|
||||
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
|
||||
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 42 24)(pt 64 24))
|
||||
)
|
||||
(drawing
|
||||
(line (pt 14 12)(pt 30 12))
|
||||
(line (pt 14 37)(pt 31 37))
|
||||
(line (pt 14 12)(pt 14 37))
|
||||
(arc (pt 31 37)(pt 30 12)(rect 18 12 43 37))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 320 104 384 152)
|
||||
(text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
|
||||
(text "inst1" (rect 3 37 26 49)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 16)
|
||||
(input)
|
||||
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
|
||||
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 0 16)(pt 14 16))
|
||||
)
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
|
||||
(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 0 32)(pt 14 32))
|
||||
)
|
||||
(port
|
||||
(pt 64 24)
|
||||
(output)
|
||||
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
|
||||
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 42 24)(pt 64 24))
|
||||
)
|
||||
(drawing
|
||||
(line (pt 14 12)(pt 30 12))
|
||||
(line (pt 14 37)(pt 31 37))
|
||||
(line (pt 14 12)(pt 14 37))
|
||||
(arc (pt 31 37)(pt 30 12)(rect 18 12 43 37))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 416 80 480 128)
|
||||
(text "OR2" (rect 1 0 19 10)(font "Arial" (font_size 6)))
|
||||
(text "inst2" (rect 3 37 26 49)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
|
||||
(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 0 32)(pt 15 32))
|
||||
)
|
||||
(port
|
||||
(pt 0 16)
|
||||
(input)
|
||||
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
|
||||
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 0 16)(pt 15 16))
|
||||
)
|
||||
(port
|
||||
(pt 64 24)
|
||||
(output)
|
||||
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
|
||||
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 48 24)(pt 64 24))
|
||||
)
|
||||
(drawing
|
||||
(line (pt 14 36)(pt 25 36))
|
||||
(line (pt 14 13)(pt 25 13))
|
||||
(arc (pt 7 29)(pt 7 19)(rect -14 8 19 41))
|
||||
(arc (pt 49 24)(pt 25 13)(rect -6 13 57 76))
|
||||
(arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 320 192 384 240)
|
||||
(text "OR2" (rect 1 0 19 10)(font "Arial" (font_size 6)))
|
||||
(text "inst3" (rect 3 37 26 49)(font "Arial" ))
|
||||
(port
|
||||
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|
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|
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|
||||
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|
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|
||||
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|
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|
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|
||||
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|
||||
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|
||||
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|
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|
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|
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|
||||
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
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|
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|
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|
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|
||||
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|
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
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|
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
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|
||||
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|
||||
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|
||||
(port
|
||||
(pt 32 0)
|
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(input)
|
||||
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|
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(text "PRN" (rect 24 11 41 23)(font "Courier New" (bold)))
|
||||
(line (pt 32 4)(pt 32 0))
|
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)
|
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|
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(pt 32 80)
|
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|
||||
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|
||||
(text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold)))
|
||||
(line (pt 32 80)(pt 32 76))
|
||||
)
|
||||
(port
|
||||
(pt 0 24)
|
||||
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|
||||
(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
|
||||
(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
|
||||
(line (pt 0 24)(pt 12 24))
|
||||
)
|
||||
(port
|
||||
(pt 0 40)
|
||||
(input)
|
||||
(text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible))
|
||||
(text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 0 40)(pt 12 40))
|
||||
)
|
||||
(port
|
||||
(pt 0 56)
|
||||
(input)
|
||||
(text "ENA" (rect 14 50 31 62)(font "Courier New" (bold)))
|
||||
(text "ENA" (rect 14 50 31 62)(font "Courier New" (bold)))
|
||||
(line (pt 0 56)(pt 12 56))
|
||||
)
|
||||
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|
||||
(pt 64 24)
|
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|
||||
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|
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(text "Q" (rect 44 20 49 32)(font "Courier New" (bold)))
|
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|
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)
|
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|
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|
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|
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(line (pt 12 34)(pt 19 41))
|
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(line (pt 18 41)(pt 12 47))
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(circle (rect 28 4 36 12))
|
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(circle (rect 28 68 36 76))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 424 160 472 192)
|
||||
(text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6)))
|
||||
(text "nclk" (rect 3 21 23 33)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 16)
|
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|
||||
(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
|
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|
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|
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)
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|
||||
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|
||||
(line (pt 13 25)(pt 31 16))
|
||||
(circle (rect 31 12 39 20))
|
||||
)
|
||||
)
|
||||
(connector
|
||||
(pt 400 96)
|
||||
(pt 416 96)
|
||||
(bus)
|
||||
)
|
||||
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|
||||
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|
||||
(pt 416 112)
|
||||
(bus)
|
||||
)
|
||||
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|
||||
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|
||||
(pt 400 128)
|
||||
(bus)
|
||||
)
|
||||
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|
||||
(pt 288 120)
|
||||
(pt 320 120)
|
||||
)
|
||||
(connector
|
||||
(pt 400 96)
|
||||
(pt 400 80)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 272 72)
|
||||
(pt 320 72)
|
||||
)
|
||||
(connector
|
||||
(pt 384 80)
|
||||
(pt 400 80)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 384 128)
|
||||
(pt 400 128)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 320 136)
|
||||
(pt 304 136)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 320 88)
|
||||
(pt 224 88)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 224 88)
|
||||
(pt 224 296)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 272 264)
|
||||
(pt 200 264)
|
||||
)
|
||||
(connector
|
||||
(pt 200 296)
|
||||
(pt 224 296)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 224 296)
|
||||
(pt 248 296)
|
||||
(bus)
|
||||
)
|
||||
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|
||||
(pt 272 264)
|
||||
(pt 272 280)
|
||||
)
|
||||
(connector
|
||||
(pt 304 136)
|
||||
(pt 304 256)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 272 72)
|
||||
(pt 272 224)
|
||||
)
|
||||
(connector
|
||||
(pt 288 120)
|
||||
(pt 288 208)
|
||||
)
|
||||
(connector
|
||||
(pt 480 104)
|
||||
(pt 504 104)
|
||||
(bus)
|
||||
)
|
||||
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|
||||
(pt 504 104)
|
||||
(pt 504 184)
|
||||
(bus)
|
||||
)
|
||||
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|
||||
(pt 528 184)
|
||||
(pt 504 184)
|
||||
(bus)
|
||||
)
|
||||
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|
||||
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|
||||
(pt 616 296)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 616 184)
|
||||
(pt 616 296)
|
||||
(bus)
|
||||
)
|
||||
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|
||||
(pt 200 40)
|
||||
(pt 664 40)
|
||||
)
|
||||
(connector
|
||||
(pt 664 40)
|
||||
(pt 664 168)
|
||||
)
|
||||
(connector
|
||||
(pt 616 184)
|
||||
(pt 640 184)
|
||||
(bus)
|
||||
)
|
||||
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|
||||
(pt 304 256)
|
||||
(pt 704 256)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 704 184)
|
||||
(pt 704 256)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 688 184)
|
||||
(pt 704 184)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 704 184)
|
||||
(pt 728 184)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "dout[7..0]" (rect 598 168 645 180)(font "Arial" ))
|
||||
(pt 592 184)
|
||||
(pt 616 184)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 200 176)
|
||||
(pt 424 176)
|
||||
)
|
||||
(connector
|
||||
(pt 488 200)
|
||||
(pt 528 200)
|
||||
)
|
||||
(connector
|
||||
(pt 488 200)
|
||||
(pt 488 176)
|
||||
)
|
||||
(connector
|
||||
(pt 488 176)
|
||||
(pt 472 176)
|
||||
)
|
||||
(connector
|
||||
(pt 528 216)
|
||||
(pt 384 216)
|
||||
)
|
||||
(connector
|
||||
(pt 200 208)
|
||||
(pt 288 208)
|
||||
)
|
||||
(connector
|
||||
(pt 200 224)
|
||||
(pt 272 224)
|
||||
)
|
||||
(connector
|
||||
(pt 272 224)
|
||||
(pt 320 224)
|
||||
)
|
||||
(connector
|
||||
(pt 288 208)
|
||||
(pt 320 208)
|
||||
)
|
||||
(junction (pt 224 296))
|
||||
(junction (pt 272 224))
|
||||
(junction (pt 288 208))
|
||||
(junction (pt 616 184))
|
||||
(junction (pt 704 184))
|
||||
(text "Repeated 8 times, once for each data pin." (rect 648 280 885 294)(font "Arial" (font_size 8)))
|
||||
(title_block
|
||||
(rect 24 360 281 412)
|
||||
(name "title-custom-small")
|
||||
(section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "June 14, 2014, 2016" (rect 56 3 171 17)(font "Arial" (font_size 8)))(border))
|
||||
(section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border))
|
||||
(section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "data_pins" (rect 43 2 109 17)(font "Arial" (font_size 9)(bold)))(border))
|
||||
(section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border))
|
||||
(section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.4" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border))
|
||||
(drawing
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,78 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
(rect 16 16 200 144)
|
||||
(text "data_pins" (rect 5 0 60 14)(font "Arial" (font_size 8)))
|
||||
(text "inst" (rect 8 112 25 124)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "bus_db_pin_oe" (rect 0 0 87 14)(font "Arial" (font_size 8)))
|
||||
(text "bus_db_pin_oe" (rect 21 27 108 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8)))
|
||||
(text "clk" (rect 21 43 36 57)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 48)(pt 16 48))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "bus_db_pin_re" (rect 0 0 84 14)(font "Arial" (font_size 8)))
|
||||
(text "bus_db_pin_re" (rect 21 59 105 73)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 64)(pt 16 64))
|
||||
)
|
||||
(port
|
||||
(pt 0 80)
|
||||
(input)
|
||||
(text "ctl_bus_db_we" (rect 0 0 88 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_bus_db_we" (rect 21 75 109 89)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 80)(pt 16 80))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "ctl_bus_db_oe" (rect 0 0 83 14)(font "Arial" (font_size 8)))
|
||||
(text "ctl_bus_db_oe" (rect 21 91 104 105)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 96)(pt 16 96))
|
||||
)
|
||||
(port
|
||||
(pt 184 32)
|
||||
(bidir)
|
||||
(text "D[7..0]" (rect 0 0 36 14)(font "Arial" (font_size 8)))
|
||||
(text "D[7..0]" (rect 127 27 163 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 184 32)(pt 168 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 184 48)
|
||||
(bidir)
|
||||
(text "db[7..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
|
||||
(text "db[7..0]" (rect 121 43 163 57)(font "Arial" (font_size 8)))
|
||||
(line (pt 184 48)(pt 168 48)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 168 112))
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,86 @@
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Thu Nov 06 23:28:26 2014"
|
||||
|
||||
module data_pins(
|
||||
bus_db_pin_oe,
|
||||
bus_db_pin_re,
|
||||
ctl_bus_db_we,
|
||||
clk,
|
||||
ctl_bus_db_oe,
|
||||
D,
|
||||
db
|
||||
);
|
||||
|
||||
|
||||
input wire bus_db_pin_oe;
|
||||
input wire bus_db_pin_re;
|
||||
input wire ctl_bus_db_we;
|
||||
input wire clk;
|
||||
input wire ctl_bus_db_oe;
|
||||
inout wire [7:0] D;
|
||||
inout wire [7:0] db;
|
||||
|
||||
reg [7:0] dout;
|
||||
wire [7:0] SYNTHESIZED_WIRE_0;
|
||||
wire SYNTHESIZED_WIRE_1;
|
||||
wire SYNTHESIZED_WIRE_2;
|
||||
wire [7:0] SYNTHESIZED_WIRE_3;
|
||||
wire [7:0] SYNTHESIZED_WIRE_4;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_1)
|
||||
begin
|
||||
if (SYNTHESIZED_WIRE_2)
|
||||
begin
|
||||
dout[7:0] <= SYNTHESIZED_WIRE_0[7:0];
|
||||
end
|
||||
end
|
||||
|
||||
assign SYNTHESIZED_WIRE_4 = {ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we} & db;
|
||||
|
||||
assign SYNTHESIZED_WIRE_3 = {bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re} & D;
|
||||
|
||||
assign SYNTHESIZED_WIRE_0 = SYNTHESIZED_WIRE_3 | SYNTHESIZED_WIRE_4;
|
||||
|
||||
assign SYNTHESIZED_WIRE_2 = ctl_bus_db_we | bus_db_pin_re;
|
||||
|
||||
assign db[7] = ctl_bus_db_oe ? dout[7] : 1'bz;
|
||||
assign db[6] = ctl_bus_db_oe ? dout[6] : 1'bz;
|
||||
assign db[5] = ctl_bus_db_oe ? dout[5] : 1'bz;
|
||||
assign db[4] = ctl_bus_db_oe ? dout[4] : 1'bz;
|
||||
assign db[3] = ctl_bus_db_oe ? dout[3] : 1'bz;
|
||||
assign db[2] = ctl_bus_db_oe ? dout[2] : 1'bz;
|
||||
assign db[1] = ctl_bus_db_oe ? dout[1] : 1'bz;
|
||||
assign db[0] = ctl_bus_db_oe ? dout[0] : 1'bz;
|
||||
|
||||
assign D[7] = bus_db_pin_oe ? dout[7] : 1'bz;
|
||||
assign D[6] = bus_db_pin_oe ? dout[6] : 1'bz;
|
||||
assign D[5] = bus_db_pin_oe ? dout[5] : 1'bz;
|
||||
assign D[4] = bus_db_pin_oe ? dout[4] : 1'bz;
|
||||
assign D[3] = bus_db_pin_oe ? dout[3] : 1'bz;
|
||||
assign D[2] = bus_db_pin_oe ? dout[2] : 1'bz;
|
||||
assign D[1] = bus_db_pin_oe ? dout[1] : 1'bz;
|
||||
assign D[0] = bus_db_pin_oe ? dout[0] : 1'bz;
|
||||
|
||||
assign SYNTHESIZED_WIRE_1 = ~clk;
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,39 @@
|
||||
// Use this file with Lattice toolset instead of data_pins.v
|
||||
//
|
||||
// This file is provided courtesy by JuanS
|
||||
|
||||
module data_pins(
|
||||
bus_db_pin_oe,
|
||||
bus_db_pin_re,
|
||||
ctl_bus_db_we,
|
||||
clk,
|
||||
ctl_bus_db_oe,
|
||||
D,
|
||||
db
|
||||
);
|
||||
|
||||
input wire bus_db_pin_oe;
|
||||
input wire bus_db_pin_re;
|
||||
input wire ctl_bus_db_we;
|
||||
input wire clk;
|
||||
input wire ctl_bus_db_oe;
|
||||
inout wire [7:0] D;
|
||||
inout wire [7:0] db;
|
||||
|
||||
reg [7:0] dout;
|
||||
|
||||
always@(negedge clk)
|
||||
begin
|
||||
if (ctl_bus_db_we | bus_db_pin_re)
|
||||
begin
|
||||
if (bus_db_pin_re)
|
||||
dout <= D;
|
||||
else if (ctl_bus_db_we)
|
||||
dout <= db;
|
||||
end
|
||||
end
|
||||
|
||||
assign db = ctl_bus_db_oe ? dout : 8'hZ;
|
||||
assign D = bus_db_pin_oe ? dout : 8'hZ;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,230 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "graphic" (version "1.4"))
|
||||
(pin
|
||||
(input)
|
||||
(rect 32 32 208 48)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "sw_up_en" (rect 9 0 57 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 32 128 208 144)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "sw_down_en" (rect 9 0 70 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(bidir)
|
||||
(rect 32 80 208 96)
|
||||
(text "BIDIR" (rect 151 0 175 10)(font "Arial" (font_size 6)))
|
||||
(text "db_down[7..0]" (rect 18 0 86 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 120 4)(pt 98 4))
|
||||
(line (pt 176 8)(pt 124 8))
|
||||
(line (pt 120 12)(pt 98 12))
|
||||
(line (pt 98 4)(pt 94 8))
|
||||
(line (pt 98 12)(pt 94 8))
|
||||
(line (pt 120 4)(pt 124 8))
|
||||
(line (pt 124 8)(pt 120 12))
|
||||
)
|
||||
(flipy)
|
||||
(text "VCC" (rect 152 7 172 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(bidir)
|
||||
(rect 352 80 528 96)
|
||||
(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
|
||||
(text "db_up[7..0]" (rect 90 0 145 12)(font "Arial" ))
|
||||
(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 56 4)(pt 78 4))
|
||||
(line (pt 0 8)(pt 52 8))
|
||||
(line (pt 56 12)(pt 78 12))
|
||||
(line (pt 78 4)(pt 82 8))
|
||||
(line (pt 78 12)(pt 82 8))
|
||||
(line (pt 56 4)(pt 52 8))
|
||||
(line (pt 52 8)(pt 56 12))
|
||||
)
|
||||
(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(symbol
|
||||
(rect 256 56 304 88)
|
||||
(text "TRI" (rect 1 0 16 10)(font "Arial" (font_size 6)))
|
||||
(text "tri1" (rect 3 21 18 33)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 16)
|
||||
(input)
|
||||
(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
|
||||
(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 0 16)(pt 14 16))
|
||||
)
|
||||
(port
|
||||
(pt 24 0)
|
||||
(input)
|
||||
(text "OE" (rect 26 0 37 12)(font "Courier New" (bold))(invisible))
|
||||
(text "OE" (rect 26 0 37 12)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 24 12)(pt 24 0))
|
||||
)
|
||||
(port
|
||||
(pt 48 16)
|
||||
(output)
|
||||
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
|
||||
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 32 16)(pt 48 16))
|
||||
)
|
||||
(drawing
|
||||
(line (pt 14 25)(pt 14 7))
|
||||
(line (pt 14 25)(pt 32 16))
|
||||
(line (pt 14 7)(pt 32 16))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 256 88 304 120)
|
||||
(text "TRI" (rect 32 22 47 32)(font "Arial" (font_size 6)))
|
||||
(text "tri2" (rect 30 -1 45 11)(font "Arial" ))
|
||||
(port
|
||||
(pt 48 16)
|
||||
(input)
|
||||
(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
|
||||
(text "IN" (rect 35 13 46 25)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 48 16)(pt 34 16))
|
||||
)
|
||||
(port
|
||||
(pt 24 32)
|
||||
(input)
|
||||
(text "OE" (rect 26 0 37 12)(font "Courier New" (bold))(invisible))
|
||||
(text "OE" (rect 11 20 22 32)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 24 20)(pt 24 32))
|
||||
)
|
||||
(port
|
||||
(pt 0 16)
|
||||
(output)
|
||||
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
|
||||
(text "OUT" (rect -1 13 16 25)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 16 16)(pt 0 16))
|
||||
)
|
||||
(drawing
|
||||
(line (pt 34 7)(pt 34 25))
|
||||
(line (pt 34 7)(pt 16 16))
|
||||
(line (pt 34 25)(pt 16 16))
|
||||
)
|
||||
(rotate180)
|
||||
)
|
||||
(connector
|
||||
(pt 208 88)
|
||||
(pt 232 88)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 232 72)
|
||||
(pt 256 72)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 232 104)
|
||||
(pt 256 104)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 304 72)
|
||||
(pt 328 72)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 328 104)
|
||||
(pt 304 104)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 328 88)
|
||||
(pt 352 88)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 280 40)
|
||||
(pt 280 56)
|
||||
)
|
||||
(connector
|
||||
(pt 280 136)
|
||||
(pt 280 120)
|
||||
)
|
||||
(connector
|
||||
(pt 232 72)
|
||||
(pt 232 88)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 232 88)
|
||||
(pt 232 104)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 328 72)
|
||||
(pt 328 88)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 328 88)
|
||||
(pt 328 104)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 208 40)
|
||||
(pt 280 40)
|
||||
)
|
||||
(connector
|
||||
(pt 208 136)
|
||||
(pt 280 136)
|
||||
)
|
||||
(junction (pt 232 88))
|
||||
(junction (pt 328 88))
|
||||
(title_block
|
||||
(rect 32 184 289 236)
|
||||
(name "title-custom-small")
|
||||
(section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "June 14, 2014" (rect 56 3 136 17)(font "Arial" (font_size 8)))(border))
|
||||
(section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border))
|
||||
(section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "data_switch" (rect 43 2 125 17)(font "Arial" (font_size 9)(bold)))(border))
|
||||
(section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border))
|
||||
(section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.0" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border))
|
||||
(drawing
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,57 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
(rect 16 16 232 112)
|
||||
(text "data_switch" (rect 5 0 75 14)(font "Arial" (font_size 8)))
|
||||
(text "inst" (rect 8 80 25 92)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "sw_up_en" (rect 0 0 61 14)(font "Arial" (font_size 8)))
|
||||
(text "sw_up_en" (rect 21 27 82 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "sw_down_en" (rect 0 0 80 14)(font "Arial" (font_size 8)))
|
||||
(text "sw_down_en" (rect 21 43 101 57)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 48)(pt 16 48))
|
||||
)
|
||||
(port
|
||||
(pt 216 32)
|
||||
(bidir)
|
||||
(text "db_down[7..0]" (rect 0 0 82 14)(font "Arial" (font_size 8)))
|
||||
(text "db_down[7..0]" (rect 113 27 195 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 32)(pt 200 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 216 48)
|
||||
(bidir)
|
||||
(text "db_up[7..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
|
||||
(text "db_up[7..0]" (rect 132 43 195 57)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 48)(pt 200 48)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 200 80))
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,55 @@
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Mon Oct 13 12:33:19 2014"
|
||||
|
||||
module data_switch(
|
||||
sw_up_en,
|
||||
sw_down_en,
|
||||
db_down,
|
||||
db_up
|
||||
);
|
||||
|
||||
|
||||
input wire sw_up_en;
|
||||
input wire sw_down_en;
|
||||
inout wire [7:0] db_down;
|
||||
inout wire [7:0] db_up;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
assign db_up[7] = sw_up_en ? db_down[7] : 1'bz;
|
||||
assign db_up[6] = sw_up_en ? db_down[6] : 1'bz;
|
||||
assign db_up[5] = sw_up_en ? db_down[5] : 1'bz;
|
||||
assign db_up[4] = sw_up_en ? db_down[4] : 1'bz;
|
||||
assign db_up[3] = sw_up_en ? db_down[3] : 1'bz;
|
||||
assign db_up[2] = sw_up_en ? db_down[2] : 1'bz;
|
||||
assign db_up[1] = sw_up_en ? db_down[1] : 1'bz;
|
||||
assign db_up[0] = sw_up_en ? db_down[0] : 1'bz;
|
||||
|
||||
assign db_down[7] = sw_down_en ? db_up[7] : 1'bz;
|
||||
assign db_down[6] = sw_down_en ? db_up[6] : 1'bz;
|
||||
assign db_down[5] = sw_down_en ? db_up[5] : 1'bz;
|
||||
assign db_down[4] = sw_down_en ? db_up[4] : 1'bz;
|
||||
assign db_down[3] = sw_down_en ? db_up[3] : 1'bz;
|
||||
assign db_down[2] = sw_down_en ? db_up[2] : 1'bz;
|
||||
assign db_down[1] = sw_down_en ? db_up[1] : 1'bz;
|
||||
assign db_down[0] = sw_down_en ? db_up[0] : 1'bz;
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,518 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
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|
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|
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|
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|
||||
(text "db_up[5..3]" (rect 531 184 586 196)(font "Arial" ))
|
||||
(pt 368 200)
|
||||
(pt 600 200)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "db_down[7..0]" (rect 250 56 318 68)(font "Arial" ))
|
||||
(pt 232 72)
|
||||
(pt 392 72)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "db_up[7..0]" (rect 529 56 584 68)(font "Arial" ))
|
||||
(pt 440 72)
|
||||
(pt 600 72)
|
||||
(bus)
|
||||
)
|
||||
(junction (pt 232 88))
|
||||
(junction (pt 344 312))
|
||||
(junction (pt 232 136))
|
||||
(junction (pt 384 232))
|
||||
(junction (pt 232 200))
|
||||
(junction (pt 600 200))
|
||||
(junction (pt 600 128))
|
||||
(junction (pt 600 88))
|
||||
(junction (pt 520 272))
|
||||
(title_block
|
||||
(rect 32 392 289 444)
|
||||
(name "title-custom-small")
|
||||
(section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border))
|
||||
(section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "data_switch_mask" (rect 43 2 171 17)(font "Arial" (font_size 9)(bold)))(border))
|
||||
(section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border))
|
||||
(section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "August 31, 2014" (rect 56 3 150 17)(font "Arial" (font_size 8)))(border))
|
||||
(section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.0" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border))
|
||||
(drawing
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,64 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
(rect 16 16 248 112)
|
||||
(text "data_switch_mask" (rect 5 0 112 14)(font "Arial" (font_size 8)))
|
||||
(text "inst" (rect 8 80 25 92)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "sw_up_en" (rect 0 0 61 14)(font "Arial" (font_size 8)))
|
||||
(text "sw_up_en" (rect 21 27 82 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "sw_down_en" (rect 0 0 80 14)(font "Arial" (font_size 8)))
|
||||
(text "sw_down_en" (rect 21 43 101 57)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 48)(pt 16 48))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "sw_mask543_en" (rect 0 0 97 14)(font "Arial" (font_size 8)))
|
||||
(text "sw_mask543_en" (rect 21 59 118 73)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 64)(pt 16 64))
|
||||
)
|
||||
(port
|
||||
(pt 232 32)
|
||||
(bidir)
|
||||
(text "db_down[7..0]" (rect 0 0 82 14)(font "Arial" (font_size 8)))
|
||||
(text "db_down[7..0]" (rect 129 27 211 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 232 32)(pt 216 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 232 48)
|
||||
(bidir)
|
||||
(text "db_up[7..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
|
||||
(text "db_up[7..0]" (rect 148 43 211 57)(font "Arial" (font_size 8)))
|
||||
(line (pt 232 48)(pt 216 48)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 216 80))
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,68 @@
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Mon Oct 13 12:32:03 2014"
|
||||
|
||||
module data_switch_mask(
|
||||
sw_up_en,
|
||||
sw_down_en,
|
||||
sw_mask543_en,
|
||||
db_down,
|
||||
db_up
|
||||
);
|
||||
|
||||
|
||||
input wire sw_up_en;
|
||||
input wire sw_down_en;
|
||||
input wire sw_mask543_en;
|
||||
inout wire [7:0] db_down;
|
||||
inout wire [7:0] db_up;
|
||||
|
||||
wire SYNTHESIZED_WIRE_4;
|
||||
wire [1:0] SYNTHESIZED_WIRE_1;
|
||||
wire [2:0] SYNTHESIZED_WIRE_2;
|
||||
|
||||
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_4 = ~sw_mask543_en;
|
||||
|
||||
assign SYNTHESIZED_WIRE_1 = db_up[7:6] & {SYNTHESIZED_WIRE_4,SYNTHESIZED_WIRE_4};
|
||||
|
||||
assign db_down[7] = sw_down_en ? SYNTHESIZED_WIRE_1[1] : 1'bz;
|
||||
assign db_down[6] = sw_down_en ? SYNTHESIZED_WIRE_1[0] : 1'bz;
|
||||
|
||||
assign db_down[2] = sw_down_en ? SYNTHESIZED_WIRE_2[2] : 1'bz;
|
||||
assign db_down[1] = sw_down_en ? SYNTHESIZED_WIRE_2[1] : 1'bz;
|
||||
assign db_down[0] = sw_down_en ? SYNTHESIZED_WIRE_2[0] : 1'bz;
|
||||
|
||||
assign SYNTHESIZED_WIRE_2 = db_up[2:0] & {SYNTHESIZED_WIRE_4,SYNTHESIZED_WIRE_4,SYNTHESIZED_WIRE_4};
|
||||
|
||||
assign db_up[7] = sw_up_en ? db_down[7] : 1'bz;
|
||||
assign db_up[6] = sw_up_en ? db_down[6] : 1'bz;
|
||||
assign db_up[5] = sw_up_en ? db_down[5] : 1'bz;
|
||||
assign db_up[4] = sw_up_en ? db_down[4] : 1'bz;
|
||||
assign db_up[3] = sw_up_en ? db_down[3] : 1'bz;
|
||||
assign db_up[2] = sw_up_en ? db_down[2] : 1'bz;
|
||||
assign db_up[1] = sw_up_en ? db_down[1] : 1'bz;
|
||||
assign db_up[0] = sw_up_en ? db_down[0] : 1'bz;
|
||||
|
||||
assign db_down[5] = sw_down_en ? db_up[5] : 1'bz;
|
||||
assign db_down[4] = sw_down_en ? db_up[4] : 1'bz;
|
||||
assign db_down[3] = sw_down_en ? db_up[3] : 1'bz;
|
||||
|
||||
|
||||
endmodule
|
||||
+2480
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,64 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
(rect 16 16 216 144)
|
||||
(text "inc_dec" (rect 5 0 49 14)(font "Arial" (font_size 8)))
|
||||
(text "inst" (rect 8 112 25 124)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "limit6" (rect 0 0 27 14)(font "Arial" (font_size 8)))
|
||||
(text "limit6" (rect 21 27 48 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "decrement" (rect 0 0 60 14)(font "Arial" (font_size 8)))
|
||||
(text "decrement" (rect 21 43 81 57)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 48)(pt 16 48))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "d[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
|
||||
(text "d[15..0]" (rect 21 59 63 73)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 64)(pt 16 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 80)
|
||||
(input)
|
||||
(text "carry_in" (rect 0 0 47 14)(font "Arial" (font_size 8)))
|
||||
(text "carry_in" (rect 21 75 68 89)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 80)(pt 16 80))
|
||||
)
|
||||
(port
|
||||
(pt 200 32)
|
||||
(output)
|
||||
(text "address[15..0]" (rect 0 0 82 14)(font "Arial" (font_size 8)))
|
||||
(text "address[15..0]" (rect 97 27 179 41)(font "Arial" (font_size 8)))
|
||||
(line (pt 200 32)(pt 184 32)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 184 112))
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,181 @@
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Mon Oct 13 12:30:20 2014"
|
||||
|
||||
module inc_dec(
|
||||
carry_in,
|
||||
limit6,
|
||||
decrement,
|
||||
d,
|
||||
address
|
||||
);
|
||||
|
||||
|
||||
input wire carry_in;
|
||||
input wire limit6;
|
||||
input wire decrement;
|
||||
input wire [15:0] d;
|
||||
output wire [15:0] address;
|
||||
|
||||
wire [15:0] address_ALTERA_SYNTHESIZED;
|
||||
wire SYNTHESIZED_WIRE_40;
|
||||
wire SYNTHESIZED_WIRE_41;
|
||||
wire SYNTHESIZED_WIRE_42;
|
||||
wire SYNTHESIZED_WIRE_43;
|
||||
wire SYNTHESIZED_WIRE_44;
|
||||
wire SYNTHESIZED_WIRE_5;
|
||||
wire SYNTHESIZED_WIRE_45;
|
||||
wire SYNTHESIZED_WIRE_46;
|
||||
wire SYNTHESIZED_WIRE_47;
|
||||
wire SYNTHESIZED_WIRE_48;
|
||||
wire SYNTHESIZED_WIRE_49;
|
||||
wire SYNTHESIZED_WIRE_50;
|
||||
wire SYNTHESIZED_WIRE_12;
|
||||
wire SYNTHESIZED_WIRE_51;
|
||||
wire SYNTHESIZED_WIRE_52;
|
||||
wire SYNTHESIZED_WIRE_53;
|
||||
wire SYNTHESIZED_WIRE_16;
|
||||
wire SYNTHESIZED_WIRE_22;
|
||||
wire SYNTHESIZED_WIRE_25;
|
||||
wire SYNTHESIZED_WIRE_31;
|
||||
wire SYNTHESIZED_WIRE_34;
|
||||
wire SYNTHESIZED_WIRE_35;
|
||||
wire SYNTHESIZED_WIRE_36;
|
||||
wire SYNTHESIZED_WIRE_37;
|
||||
wire SYNTHESIZED_WIRE_38;
|
||||
wire SYNTHESIZED_WIRE_39;
|
||||
|
||||
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_34 = carry_in & SYNTHESIZED_WIRE_40 & SYNTHESIZED_WIRE_41 & SYNTHESIZED_WIRE_42 & SYNTHESIZED_WIRE_43 & SYNTHESIZED_WIRE_44 & SYNTHESIZED_WIRE_5 & SYNTHESIZED_WIRE_45;
|
||||
|
||||
assign SYNTHESIZED_WIRE_51 = SYNTHESIZED_WIRE_46 & SYNTHESIZED_WIRE_47 & SYNTHESIZED_WIRE_48 & SYNTHESIZED_WIRE_49 & SYNTHESIZED_WIRE_50 & SYNTHESIZED_WIRE_12;
|
||||
|
||||
assign SYNTHESIZED_WIRE_38 = SYNTHESIZED_WIRE_51 & SYNTHESIZED_WIRE_52 & SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_16;
|
||||
|
||||
|
||||
inc_dec_2bit b2v_dual_adder_0(
|
||||
.carry_borrow_in(carry_in),
|
||||
.d1_in(d[1]),
|
||||
.d0_in(d[0]),
|
||||
.dec1_in(SYNTHESIZED_WIRE_40),
|
||||
.dec0_in(SYNTHESIZED_WIRE_41),
|
||||
.carry_borrow_out(SYNTHESIZED_WIRE_22),
|
||||
.d1_out(address_ALTERA_SYNTHESIZED[1]),
|
||||
.d0_out(address_ALTERA_SYNTHESIZED[0]));
|
||||
|
||||
|
||||
inc_dec_2bit b2v_dual_adder_10(
|
||||
.carry_borrow_in(SYNTHESIZED_WIRE_51),
|
||||
.d1_in(d[13]),
|
||||
.d0_in(d[12]),
|
||||
.dec1_in(SYNTHESIZED_WIRE_53),
|
||||
.dec0_in(SYNTHESIZED_WIRE_52),
|
||||
.carry_borrow_out(SYNTHESIZED_WIRE_37),
|
||||
.d1_out(address_ALTERA_SYNTHESIZED[13]),
|
||||
.d0_out(address_ALTERA_SYNTHESIZED[12]));
|
||||
|
||||
|
||||
inc_dec_2bit b2v_dual_adder_2(
|
||||
.carry_borrow_in(SYNTHESIZED_WIRE_22),
|
||||
.d1_in(d[3]),
|
||||
.d0_in(d[2]),
|
||||
.dec1_in(SYNTHESIZED_WIRE_45),
|
||||
.dec0_in(SYNTHESIZED_WIRE_42),
|
||||
.carry_borrow_out(SYNTHESIZED_WIRE_25),
|
||||
.d1_out(address_ALTERA_SYNTHESIZED[3]),
|
||||
.d0_out(address_ALTERA_SYNTHESIZED[2]));
|
||||
|
||||
|
||||
inc_dec_2bit b2v_dual_adder_4(
|
||||
.carry_borrow_in(SYNTHESIZED_WIRE_25),
|
||||
.d1_in(d[5]),
|
||||
.d0_in(d[4]),
|
||||
.dec1_in(SYNTHESIZED_WIRE_43),
|
||||
.dec0_in(SYNTHESIZED_WIRE_44),
|
||||
.carry_borrow_out(SYNTHESIZED_WIRE_39),
|
||||
.d1_out(address_ALTERA_SYNTHESIZED[5]),
|
||||
.d0_out(address_ALTERA_SYNTHESIZED[4]));
|
||||
|
||||
|
||||
inc_dec_2bit b2v_dual_adder_7(
|
||||
.carry_borrow_in(SYNTHESIZED_WIRE_47),
|
||||
.d1_in(d[8]),
|
||||
.d0_in(d[7]),
|
||||
.dec1_in(SYNTHESIZED_WIRE_46),
|
||||
.dec0_in(SYNTHESIZED_WIRE_48),
|
||||
.carry_borrow_out(SYNTHESIZED_WIRE_31),
|
||||
.d1_out(address_ALTERA_SYNTHESIZED[8]),
|
||||
.d0_out(address_ALTERA_SYNTHESIZED[7]));
|
||||
|
||||
|
||||
inc_dec_2bit b2v_dual_adder_9(
|
||||
.carry_borrow_in(SYNTHESIZED_WIRE_31),
|
||||
.d1_in(d[10]),
|
||||
.d0_in(d[9]),
|
||||
.dec1_in(SYNTHESIZED_WIRE_50),
|
||||
.dec0_in(SYNTHESIZED_WIRE_49),
|
||||
.carry_borrow_out(SYNTHESIZED_WIRE_36),
|
||||
.d1_out(address_ALTERA_SYNTHESIZED[10]),
|
||||
.d0_out(address_ALTERA_SYNTHESIZED[9]));
|
||||
|
||||
assign SYNTHESIZED_WIRE_47 = SYNTHESIZED_WIRE_34 & SYNTHESIZED_WIRE_35;
|
||||
|
||||
assign SYNTHESIZED_WIRE_35 = ~limit6;
|
||||
|
||||
assign SYNTHESIZED_WIRE_41 = d[0] ^ decrement;
|
||||
|
||||
assign SYNTHESIZED_WIRE_40 = d[1] ^ decrement;
|
||||
|
||||
assign SYNTHESIZED_WIRE_50 = d[10] ^ decrement;
|
||||
|
||||
assign SYNTHESIZED_WIRE_12 = d[11] ^ decrement;
|
||||
|
||||
assign address_ALTERA_SYNTHESIZED[11] = SYNTHESIZED_WIRE_36 ^ d[11];
|
||||
|
||||
assign SYNTHESIZED_WIRE_52 = d[12] ^ decrement;
|
||||
|
||||
assign SYNTHESIZED_WIRE_53 = d[13] ^ decrement;
|
||||
|
||||
assign SYNTHESIZED_WIRE_16 = d[14] ^ decrement;
|
||||
|
||||
assign address_ALTERA_SYNTHESIZED[14] = SYNTHESIZED_WIRE_37 ^ d[14];
|
||||
|
||||
assign address_ALTERA_SYNTHESIZED[15] = SYNTHESIZED_WIRE_38 ^ d[15];
|
||||
|
||||
assign SYNTHESIZED_WIRE_42 = d[2] ^ decrement;
|
||||
|
||||
assign SYNTHESIZED_WIRE_45 = d[3] ^ decrement;
|
||||
|
||||
assign SYNTHESIZED_WIRE_44 = d[4] ^ decrement;
|
||||
|
||||
assign SYNTHESIZED_WIRE_43 = d[5] ^ decrement;
|
||||
|
||||
assign SYNTHESIZED_WIRE_5 = d[6] ^ decrement;
|
||||
|
||||
assign address_ALTERA_SYNTHESIZED[6] = SYNTHESIZED_WIRE_39 ^ d[6];
|
||||
|
||||
assign SYNTHESIZED_WIRE_48 = d[7] ^ decrement;
|
||||
|
||||
assign SYNTHESIZED_WIRE_46 = d[8] ^ decrement;
|
||||
|
||||
assign SYNTHESIZED_WIRE_49 = d[9] ^ decrement;
|
||||
|
||||
assign address = address_ALTERA_SYNTHESIZED;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,378 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
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|
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|
||||
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|
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|
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|
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|
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|
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|
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
||||
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|
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|
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|
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|
||||
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|
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|
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|
||||
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|
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|
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(title_block
|
||||
(rect 24 256 281 308)
|
||||
(name "title-custom-small")
|
||||
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|
||||
(section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border))
|
||||
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|
||||
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|
||||
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|
||||
(drawing
|
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)
|
||||
)
|
||||
@@ -0,0 +1,86 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2011 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
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|
||||
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|
||||
(text "inc_dec_2bit" (rect 16 0 87 14)(font "Arial" (font_size 8)))
|
||||
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|
||||
(port
|
||||
(pt 0 24)
|
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|
||||
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|
||||
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(pt 0 40)
|
||||
(input)
|
||||
(text "d0_in" (rect 0 0 30 14)(font "Arial" (font_size 8)))
|
||||
(text "d0_in" (rect 21 35 51 49)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 40)(pt 16 40))
|
||||
)
|
||||
(port
|
||||
(pt 0 136)
|
||||
(input)
|
||||
(text "dec1_in" (rect 0 0 44 14)(font "Arial" (font_size 8)))
|
||||
(text "dec1_in" (rect 21 131 65 145)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 136)(pt 16 136))
|
||||
)
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "dec0_in" (rect 0 0 44 14)(font "Arial" (font_size 8)))
|
||||
(text "dec0_in" (rect 21 67 65 81)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 16 72))
|
||||
)
|
||||
(port
|
||||
(pt 248 128)
|
||||
(output)
|
||||
(text "carry_borrow_out" (rect -8 0 97 14)(font "Arial" (font_size 8)))
|
||||
(text "carry_borrow_out" (rect 122 123 227 137)(font "Arial" (font_size 8)))
|
||||
(line (pt 248 128)(pt 232 128))
|
||||
)
|
||||
(port
|
||||
(pt 248 80)
|
||||
(output)
|
||||
(text "d1_out" (rect -8 0 30 14)(font "Arial" (font_size 8)))
|
||||
(text "d1_out" (rect 189 75 227 89)(font "Arial" (font_size 8)))
|
||||
(line (pt 248 80)(pt 232 80))
|
||||
)
|
||||
(port
|
||||
(pt 248 56)
|
||||
(output)
|
||||
(text "d0_out" (rect -8 0 30 14)(font "Arial" (font_size 8)))
|
||||
(text "d0_out" (rect 189 51 227 65)(font "Arial" (font_size 8)))
|
||||
(line (pt 248 56)(pt 232 56))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 240 152))
|
||||
)
|
||||
(fill (color 253 211 206))
|
||||
)
|
||||
@@ -0,0 +1,54 @@
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Mon Oct 13 12:26:57 2014"
|
||||
|
||||
module inc_dec_2bit(
|
||||
carry_borrow_in,
|
||||
d1_in,
|
||||
d0_in,
|
||||
dec1_in,
|
||||
dec0_in,
|
||||
carry_borrow_out,
|
||||
d1_out,
|
||||
d0_out
|
||||
);
|
||||
|
||||
|
||||
input wire carry_borrow_in;
|
||||
input wire d1_in;
|
||||
input wire d0_in;
|
||||
input wire dec1_in;
|
||||
input wire dec0_in;
|
||||
output wire carry_borrow_out;
|
||||
output wire d1_out;
|
||||
output wire d0_out;
|
||||
|
||||
wire SYNTHESIZED_WIRE_0;
|
||||
|
||||
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_0 = dec0_in & carry_borrow_in;
|
||||
|
||||
assign carry_borrow_out = dec0_in & dec1_in & carry_borrow_in;
|
||||
|
||||
assign d1_out = d1_in ^ SYNTHESIZED_WIRE_0;
|
||||
|
||||
assign d0_out = carry_borrow_in ^ d0_in;
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1 @@
|
||||
restart -f ; run -all
|
||||
@@ -0,0 +1,511 @@
|
||||
; Copyright 1991-2009 Mentor Graphics Corporation
|
||||
;
|
||||
; All Rights Reserved.
|
||||
;
|
||||
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
|
||||
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
;
|
||||
|
||||
[Library]
|
||||
std = $MODEL_TECH/../std
|
||||
ieee = $MODEL_TECH/../ieee
|
||||
verilog = $MODEL_TECH/../verilog
|
||||
vital2000 = $MODEL_TECH/../vital2000
|
||||
std_developerskit = $MODEL_TECH/../std_developerskit
|
||||
synopsys = $MODEL_TECH/../synopsys
|
||||
modelsim_lib = $MODEL_TECH/../modelsim_lib
|
||||
sv_std = $MODEL_TECH/../sv_std
|
||||
|
||||
; Altera Primitive libraries
|
||||
;
|
||||
; VHDL Section
|
||||
;
|
||||
altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
|
||||
altera = $MODEL_TECH/../altera/vhdl/altera
|
||||
altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim
|
||||
lpm = $MODEL_TECH/../altera/vhdl/220model
|
||||
220model = $MODEL_TECH/../altera/vhdl/220model
|
||||
max = $MODEL_TECH/../altera/vhdl/max
|
||||
maxii = $MODEL_TECH/../altera/vhdl/maxii
|
||||
maxv = $MODEL_TECH/../altera/vhdl/maxv
|
||||
stratix = $MODEL_TECH/../altera/vhdl/stratix
|
||||
stratixii = $MODEL_TECH/../altera/vhdl/stratixii
|
||||
stratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx
|
||||
hardcopyii = $MODEL_TECH/../altera/vhdl/hardcopyii
|
||||
hardcopyiii = $MODEL_TECH/../altera/vhdl/hardcopyiii
|
||||
hardcopyiv = $MODEL_TECH/../altera/vhdl/hardcopyiv
|
||||
cyclone = $MODEL_TECH/../altera/vhdl/cyclone
|
||||
cycloneii = $MODEL_TECH/../altera/vhdl/cycloneii
|
||||
cycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii
|
||||
cycloneiiils = $MODEL_TECH/../altera/vhdl/cycloneiiils
|
||||
sgate = $MODEL_TECH/../altera/vhdl/sgate
|
||||
stratixgx = $MODEL_TECH/../altera/vhdl/stratixgx
|
||||
altgxb = $MODEL_TECH/../altera/vhdl/altgxb
|
||||
stratixgx_gxb = $MODEL_TECH/../altera/vhdl/stratixgx_gxb
|
||||
stratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi
|
||||
arriagx_hssi = $MODEL_TECH/../altera/vhdl/arriagx_hssi
|
||||
arriaii = $MODEL_TECH/../altera/vhdl/arriaii
|
||||
arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
|
||||
arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
|
||||
arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz
|
||||
arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi
|
||||
arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip
|
||||
arriagx = $MODEL_TECH/../altera/vhdl/arriagx
|
||||
altgxb_lib = $MODEL_TECH/../altera/vhdl/altgxb
|
||||
stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
|
||||
stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
|
||||
stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
|
||||
cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
|
||||
cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
|
||||
cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
|
||||
cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive
|
||||
hardcopyiv_hssi = $MODEL_TECH/../altera/vhdl/hardcopyiv_hssi
|
||||
hardcopyiv_pcie_hip = $MODEL_TECH/../altera/vhdl/hardcopyiv_pcie_hip
|
||||
stratixv = $MODEL_TECH/../altera/vhdl/stratixv
|
||||
stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi
|
||||
stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip
|
||||
arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz
|
||||
arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi
|
||||
arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip
|
||||
arriav = $MODEL_TECH/../altera/vhdl/arriav
|
||||
cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev
|
||||
;
|
||||
; Verilog Section
|
||||
;
|
||||
altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
|
||||
altera_ver = $MODEL_TECH/../altera/verilog/altera
|
||||
altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim
|
||||
lpm_ver = $MODEL_TECH/../altera/verilog/220model
|
||||
220model_ver = $MODEL_TECH/../altera/verilog/220model
|
||||
max_ver = $MODEL_TECH/../altera/verilog/max
|
||||
maxii_ver = $MODEL_TECH/../altera/verilog/maxii
|
||||
maxv_ver = $MODEL_TECH/../altera/verilog/maxv
|
||||
stratix_ver = $MODEL_TECH/../altera/verilog/stratix
|
||||
stratixii_ver = $MODEL_TECH/../altera/verilog/stratixii
|
||||
stratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx
|
||||
arriagx_ver = $MODEL_TECH/../altera/verilog/arriagx
|
||||
hardcopyii_ver = $MODEL_TECH/../altera/verilog/hardcopyii
|
||||
hardcopyiii_ver = $MODEL_TECH/../altera/verilog/hardcopyiii
|
||||
hardcopyiv_ver = $MODEL_TECH/../altera/verilog/hardcopyiv
|
||||
cyclone_ver = $MODEL_TECH/../altera/verilog/cyclone
|
||||
cycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii
|
||||
cycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii
|
||||
cycloneiiils_ver = $MODEL_TECH/../altera/verilog/cycloneiiils
|
||||
sgate_ver = $MODEL_TECH/../altera/verilog/sgate
|
||||
stratixgx_ver = $MODEL_TECH/../altera/verilog/stratixgx
|
||||
altgxb_ver = $MODEL_TECH/../altera/verilog/altgxb
|
||||
stratixgx_gxb_ver = $MODEL_TECH/../altera/verilog/stratixgx_gxb
|
||||
stratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi
|
||||
arriagx_hssi_ver = $MODEL_TECH/../altera/verilog/arriagx_hssi
|
||||
arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
|
||||
arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
|
||||
arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
|
||||
arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz
|
||||
arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi
|
||||
arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip
|
||||
stratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii
|
||||
stratixiii = $MODEL_TECH/../altera/vhdl/stratixiii
|
||||
stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
|
||||
stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
|
||||
stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
|
||||
stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv
|
||||
stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi
|
||||
stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip
|
||||
arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz
|
||||
arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi
|
||||
arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip
|
||||
arriav_ver = $MODEL_TECH/../altera/verilog/arriav
|
||||
arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi
|
||||
arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip
|
||||
cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev
|
||||
cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi
|
||||
cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip
|
||||
cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
|
||||
cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
|
||||
cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
|
||||
cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
|
||||
hardcopyiv_hssi_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_hssi
|
||||
hardcopyiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_pcie_hip
|
||||
|
||||
work = work
|
||||
[vcom]
|
||||
; VHDL93 variable selects language version as the default.
|
||||
; Default is VHDL-2002.
|
||||
; Value of 0 or 1987 for VHDL-1987.
|
||||
; Value of 1 or 1993 for VHDL-1993.
|
||||
; Default or value of 2 or 2002 for VHDL-2002.
|
||||
; Default or value of 3 or 2008 for VHDL-2008.
|
||||
VHDL93 = 2002
|
||||
|
||||
; Show source line containing error. Default is off.
|
||||
; Show_source = 1
|
||||
|
||||
; Turn off unbound-component warnings. Default is on.
|
||||
; Show_Warning1 = 0
|
||||
|
||||
; Turn off process-without-a-wait-statement warnings. Default is on.
|
||||
; Show_Warning2 = 0
|
||||
|
||||
; Turn off null-range warnings. Default is on.
|
||||
; Show_Warning3 = 0
|
||||
|
||||
; Turn off no-space-in-time-literal warnings. Default is on.
|
||||
; Show_Warning4 = 0
|
||||
|
||||
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
|
||||
; Show_Warning5 = 0
|
||||
|
||||
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
|
||||
; Optimize_1164 = 0
|
||||
|
||||
; Turn on resolving of ambiguous function overloading in favor of the
|
||||
; "explicit" function declaration (not the one automatically created by
|
||||
; the compiler for each type declaration). Default is off.
|
||||
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
|
||||
; will match the behavior of synthesis tools.
|
||||
Explicit = 1
|
||||
|
||||
; Turn off acceleration of the VITAL packages. Default is to accelerate.
|
||||
; NoVital = 1
|
||||
|
||||
; Turn off VITAL compliance checking. Default is checking on.
|
||||
; NoVitalCheck = 1
|
||||
|
||||
; Ignore VITAL compliance checking errors. Default is to not ignore.
|
||||
; IgnoreVitalErrors = 1
|
||||
|
||||
; Turn off VITAL compliance checking warnings. Default is to show warnings.
|
||||
; Show_VitalChecksWarnings = 0
|
||||
|
||||
; Keep silent about case statement static warnings.
|
||||
; Default is to give a warning.
|
||||
; NoCaseStaticError = 1
|
||||
|
||||
; Keep silent about warnings caused by aggregates that are not locally static.
|
||||
; Default is to give a warning.
|
||||
; NoOthersStaticError = 1
|
||||
|
||||
; Turn off inclusion of debugging info within design units.
|
||||
; Default is to include debugging info.
|
||||
; NoDebug = 1
|
||||
|
||||
; Turn off "Loading..." messages. Default is messages on.
|
||||
; Quiet = 1
|
||||
|
||||
; Turn on some limited synthesis rule compliance checking. Checks only:
|
||||
; -- signals used (read) by a process must be in the sensitivity list
|
||||
; CheckSynthesis = 1
|
||||
|
||||
; Activate optimizations on expressions that do not involve signals,
|
||||
; waits, or function/procedure/task invocations. Default is off.
|
||||
; ScalarOpts = 1
|
||||
|
||||
; Require the user to specify a configuration for all bindings,
|
||||
; and do not generate a compile time default binding for the
|
||||
; component. This will result in an elaboration error of
|
||||
; 'component not bound' if the user fails to do so. Avoids the rare
|
||||
; issue of a false dependency upon the unused default binding.
|
||||
; RequireConfigForAllDefaultBinding = 1
|
||||
|
||||
; Inhibit range checking on subscripts of arrays. Range checking on
|
||||
; scalars defined with subtypes is inhibited by default.
|
||||
; NoIndexCheck = 1
|
||||
|
||||
; Inhibit range checks on all (implicit and explicit) assignments to
|
||||
; scalar objects defined with subtypes.
|
||||
; NoRangeCheck = 1
|
||||
|
||||
[vlog]
|
||||
|
||||
; Turn off inclusion of debugging info within design units.
|
||||
; Default is to include debugging info.
|
||||
; NoDebug = 1
|
||||
|
||||
; Turn off "loading..." messages. Default is messages on.
|
||||
; Quiet = 1
|
||||
|
||||
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
|
||||
; Default is off.
|
||||
; Hazard = 1
|
||||
|
||||
; Turn on converting regular Verilog identifiers to uppercase. Allows case
|
||||
; insensitivity for module names. Default is no conversion.
|
||||
; UpCase = 1
|
||||
|
||||
; Turn on incremental compilation of modules. Default is off.
|
||||
; Incremental = 1
|
||||
|
||||
; Turns on lint-style checking.
|
||||
; Show_Lint = 1
|
||||
|
||||
[vsim]
|
||||
; Simulator resolution
|
||||
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
|
||||
Resolution = ps
|
||||
|
||||
; User time unit for run commands
|
||||
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
|
||||
; unit specified for Resolution. For example, if Resolution is 100ps,
|
||||
; then UserTimeUnit defaults to ps.
|
||||
; Should generally be set to default.
|
||||
UserTimeUnit = default
|
||||
|
||||
; Default run length
|
||||
RunLength = 1 us
|
||||
|
||||
; Maximum iterations that can be run without advancing simulation time
|
||||
IterationLimit = 5000
|
||||
|
||||
; Directive to license manager:
|
||||
; vhdl Immediately reserve a VHDL license
|
||||
; vlog Immediately reserve a Verilog license
|
||||
; plus Immediately reserve a VHDL and Verilog license
|
||||
; nomgc Do not look for Mentor Graphics Licenses
|
||||
; nomti Do not look for Model Technology Licenses
|
||||
; noqueue Do not wait in the license queue when a license isn't available
|
||||
; viewsim Try for viewer license but accept simulator license(s) instead
|
||||
; of queuing for viewer license
|
||||
; License = plus
|
||||
|
||||
; Stop the simulator after a VHDL/Verilog assertion message
|
||||
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
|
||||
BreakOnAssertion = 3
|
||||
|
||||
; Assertion Message Format
|
||||
; %S - Severity Level
|
||||
; %R - Report Message
|
||||
; %T - Time of assertion
|
||||
; %D - Delta
|
||||
; %I - Instance or Region pathname (if available)
|
||||
; %% - print '%' character
|
||||
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
|
||||
|
||||
; Assertion File - alternate file for storing VHDL/Verilog assertion messages
|
||||
; AssertFile = assert.log
|
||||
|
||||
; Default radix for all windows and commands...
|
||||
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
|
||||
DefaultRadix = hexadecimal
|
||||
|
||||
; VSIM Startup command
|
||||
; Startup = do startup.do
|
||||
|
||||
; File for saving command transcript
|
||||
TranscriptFile = transcript
|
||||
|
||||
; File for saving command history
|
||||
; CommandHistory = cmdhist.log
|
||||
|
||||
; Specify whether paths in simulator commands should be described
|
||||
; in VHDL or Verilog format.
|
||||
; For VHDL, PathSeparator = /
|
||||
; For Verilog, PathSeparator = .
|
||||
; Must not be the same character as DatasetSeparator.
|
||||
PathSeparator = /
|
||||
|
||||
; Specify the dataset separator for fully rooted contexts.
|
||||
; The default is ':'. For example, sim:/top
|
||||
; Must not be the same character as PathSeparator.
|
||||
DatasetSeparator = :
|
||||
|
||||
; Disable VHDL assertion messages
|
||||
; IgnoreNote = 1
|
||||
; IgnoreWarning = 1
|
||||
; IgnoreError = 1
|
||||
; IgnoreFailure = 1
|
||||
|
||||
; Default force kind. May be freeze, drive, deposit, or default
|
||||
; or in other terms, fixed, wired, or charged.
|
||||
; A value of "default" will use the signal kind to determine the
|
||||
; force kind, drive for resolved signals, freeze for unresolved signals
|
||||
; DefaultForceKind = freeze
|
||||
|
||||
; If zero, open files when elaborated; otherwise, open files on
|
||||
; first read or write. Default is 0.
|
||||
; DelayFileOpen = 1
|
||||
|
||||
; Control VHDL files opened for write.
|
||||
; 0 = Buffered, 1 = Unbuffered
|
||||
UnbufferedOutput = 0
|
||||
|
||||
; Control the number of VHDL files open concurrently.
|
||||
; This number should always be less than the current ulimit
|
||||
; setting for max file descriptors.
|
||||
; 0 = unlimited
|
||||
ConcurrentFileLimit = 40
|
||||
|
||||
; Control the number of hierarchical regions displayed as
|
||||
; part of a signal name shown in the Wave window.
|
||||
; A value of zero tells VSIM to display the full name.
|
||||
; The default is 0.
|
||||
; WaveSignalNameWidth = 0
|
||||
|
||||
; Turn off warnings from the std_logic_arith, std_logic_unsigned
|
||||
; and std_logic_signed packages.
|
||||
; StdArithNoWarnings = 1
|
||||
|
||||
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
|
||||
; NumericStdNoWarnings = 1
|
||||
|
||||
; Control the format of the (VHDL) FOR generate statement label
|
||||
; for each iteration. Do not quote it.
|
||||
; The format string here must contain the conversion codes %s and %d,
|
||||
; in that order, and no other conversion codes. The %s represents
|
||||
; the generate_label; the %d represents the generate parameter value
|
||||
; at a particular generate iteration (this is the position number if
|
||||
; the generate parameter is of an enumeration type). Embedded whitespace
|
||||
; is allowed (but discouraged); leading and trailing whitespace is ignored.
|
||||
; Application of the format must result in a unique scope name over all
|
||||
; such names in the design so that name lookup can function properly.
|
||||
; GenerateFormat = %s__%d
|
||||
|
||||
; Specify whether checkpoint files should be compressed.
|
||||
; The default is 1 (compressed).
|
||||
; CheckpointCompressMode = 0
|
||||
|
||||
; List of dynamically loaded objects for Verilog PLI applications
|
||||
; Veriuser = veriuser.sl
|
||||
|
||||
; Specify default options for the restart command. Options can be one
|
||||
; or more of: -force -nobreakpoint -nolist -nolog -nowave
|
||||
; DefaultRestartOptions = -force
|
||||
|
||||
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
|
||||
; (> 500 megabyte memory footprint). Default is disabled.
|
||||
; Specify number of megabytes to lock.
|
||||
; LockedMemory = 1000
|
||||
|
||||
; Turn on (1) or off (0) WLF file compression.
|
||||
; The default is 1 (compress WLF file).
|
||||
; WLFCompress = 0
|
||||
|
||||
; Specify whether to save all design hierarchy (1) in the WLF file
|
||||
; or only regions containing logged signals (0).
|
||||
; The default is 0 (save only regions with logged signals).
|
||||
; WLFSaveAllRegions = 1
|
||||
|
||||
; WLF file time limit. Limit WLF file by time, as closely as possible,
|
||||
; to the specified amount of simulation time. When the limit is exceeded
|
||||
; the earliest times get truncated from the file.
|
||||
; If both time and size limits are specified the most restrictive is used.
|
||||
; UserTimeUnits are used if time units are not specified.
|
||||
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
|
||||
; WLFTimeLimit = 0
|
||||
|
||||
; WLF file size limit. Limit WLF file size, as closely as possible,
|
||||
; to the specified number of megabytes. If both time and size limits
|
||||
; are specified then the most restrictive is used.
|
||||
; The default is 0 (no limit).
|
||||
; WLFSizeLimit = 1000
|
||||
|
||||
; Specify whether or not a WLF file should be deleted when the
|
||||
; simulation ends. A value of 1 will cause the WLF file to be deleted.
|
||||
; The default is 0 (do not delete WLF file when simulation ends).
|
||||
; WLFDeleteOnQuit = 1
|
||||
|
||||
; Automatic SDF compilation
|
||||
; Disables automatic compilation of SDF files in flows that support it.
|
||||
; Default is on, uncomment to turn off.
|
||||
; NoAutoSDFCompile = 1
|
||||
|
||||
[lmc]
|
||||
|
||||
[msg_system]
|
||||
; Change a message severity or suppress a message.
|
||||
; The format is: <msg directive> = <msg number>[,<msg number>...]
|
||||
; Examples:
|
||||
; note = 3009
|
||||
; warning = 3033
|
||||
; error = 3010,3016
|
||||
; fatal = 3016,3033
|
||||
; suppress = 3009,3016,3043
|
||||
; The command verror <msg number> can be used to get the complete
|
||||
; description of a message.
|
||||
|
||||
; Control transcripting of elaboration/runtime messages.
|
||||
; The default is to have messages appear in the transcript and
|
||||
; recorded in the wlf file (messages that are recorded in the
|
||||
; wlf file can be viewed in the MsgViewer). The other settings
|
||||
; are to send messages only to the transcript or only to the
|
||||
; wlf file. The valid values are
|
||||
; both {default}
|
||||
; tran {transcript only}
|
||||
; wlf {wlf file only}
|
||||
; msgmode = both
|
||||
[Project]
|
||||
; Warning -- Do not edit the project properties directly.
|
||||
; Property names are dynamic in nature and property
|
||||
; values have special syntax. Changing property data directly
|
||||
; can result in a corrupt MPF file. All project properties
|
||||
; can be modified through project window dialogs.
|
||||
Project_Version = 6
|
||||
Project_DefaultLib = work
|
||||
Project_SortMethod = unused
|
||||
Project_Files_Count = 8
|
||||
Project_File_0 = $ROOT/cpu/bus/address_latch.v
|
||||
Project_File_P_0 = compile_order 0 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_1 = $ROOT/cpu/bus/address_mux.v
|
||||
Project_File_P_1 = compile_order 7 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_2 = $ROOT/cpu/bus/address_pins.v
|
||||
Project_File_P_2 = compile_order 5 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_3 = $ROOT/cpu/bus/data_pins.v
|
||||
Project_File_P_3 = compile_order 6 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_4 = $ROOT/cpu/bus/inc_dec.v
|
||||
Project_File_P_4 = compile_order 1 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_5 = $ROOT/cpu/bus/inc_dec_2bit.v
|
||||
Project_File_P_5 = compile_order 3 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_6 = $ROOT/cpu/bus/test_bus.sv
|
||||
Project_File_P_6 = compile_order 2 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_File_7 = $ROOT/cpu/bus/test_pins.sv
|
||||
Project_File_P_7 = compile_order 4 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
||||
Project_Sim_Count = 2
|
||||
Project_Sim_0 = Test pins
|
||||
Project_Sim_P_0 = timing default -t default -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {Top Level} +pulse_e {} additional_dus work.test_pins -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}
|
||||
Project_Sim_1 = Test bus
|
||||
Project_Sim_P_1 = timing default -t default -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {Top Level} +pulse_e {} additional_dus work.test_bus -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}
|
||||
Project_Folder_Count = 0
|
||||
Echo_Compile_Output = 0
|
||||
Save_Compile_Report = 1
|
||||
Project_Opt_Count = 0
|
||||
ForceSoftPaths = 1
|
||||
ProjectStatusDelay = 5000
|
||||
VERILOG_DoubleClick = Edit
|
||||
VERILOG_CustomDoubleClick =
|
||||
SYSTEMVERILOG_DoubleClick = Edit
|
||||
SYSTEMVERILOG_CustomDoubleClick =
|
||||
VHDL_DoubleClick = Edit
|
||||
VHDL_CustomDoubleClick =
|
||||
PSL_DoubleClick = Edit
|
||||
PSL_CustomDoubleClick =
|
||||
TEXT_DoubleClick = Edit
|
||||
TEXT_CustomDoubleClick =
|
||||
SYSTEMC_DoubleClick = Edit
|
||||
SYSTEMC_CustomDoubleClick =
|
||||
TCL_DoubleClick = Edit
|
||||
TCL_CustomDoubleClick =
|
||||
MACRO_DoubleClick = Edit
|
||||
MACRO_CustomDoubleClick =
|
||||
VCD_DoubleClick = Edit
|
||||
VCD_CustomDoubleClick =
|
||||
SDF_DoubleClick = Edit
|
||||
SDF_CustomDoubleClick =
|
||||
XML_DoubleClick = Edit
|
||||
XML_CustomDoubleClick =
|
||||
LOGFILE_DoubleClick = Edit
|
||||
LOGFILE_CustomDoubleClick =
|
||||
UCDB_DoubleClick = Edit
|
||||
UCDB_CustomDoubleClick =
|
||||
UPF_DoubleClick = Edit
|
||||
UPF_CustomDoubleClick =
|
||||
PCF_DoubleClick = Edit
|
||||
PCF_CustomDoubleClick =
|
||||
PROJECT_DoubleClick = Edit
|
||||
PROJECT_CustomDoubleClick =
|
||||
VRM_DoubleClick = Edit
|
||||
VRM_CustomDoubleClick =
|
||||
DEBUGDATABASE_DoubleClick = Edit
|
||||
DEBUGDATABASE_CustomDoubleClick =
|
||||
DEBUGARCHIVE_DoubleClick = Edit
|
||||
DEBUGARCHIVE_CustomDoubleClick =
|
||||
Project_Major_Version = 10
|
||||
Project_Minor_Version = 1
|
||||
@@ -0,0 +1,34 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate /test_bus/nreset
|
||||
add wave -noupdate /test_bus/clk
|
||||
add wave -noupdate /test_bus/abusw
|
||||
add wave -noupdate /test_bus/abus
|
||||
add wave -noupdate -color Gold /test_bus/address
|
||||
add wave -noupdate /test_bus/ctl_al_we
|
||||
add wave -noupdate /test_bus/ctl_bus_inc_oe
|
||||
add wave -noupdate /test_bus/ctl_inc_dec
|
||||
add wave -noupdate /test_bus/ctl_inc_limit6
|
||||
add wave -noupdate /test_bus/ctl_inc_cy
|
||||
add wave -noupdate /test_bus/clrpc
|
||||
add wave -noupdate /test_bus/address_is_1
|
||||
add wave -noupdate /test_bus/address_latch_/ctl_apin_mux
|
||||
add wave -noupdate /test_bus/address_latch_/ctl_apin_mux2
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {5500 ns} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 141
|
||||
configure wave -valuecolwidth 62
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
configure wave -timelineunits ps
|
||||
update
|
||||
WaveRestoreZoom {0 ns} {39500 ns}
|
||||
@@ -0,0 +1,34 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate /test_pins/clk
|
||||
add wave -noupdate -divider apins
|
||||
add wave -noupdate -color Gold -radix hexadecimal /test_pins/apin
|
||||
add wave -noupdate -radix hexadecimal /test_pins/ab
|
||||
add wave -noupdate /test_pins/ctl_ab_we
|
||||
add wave -noupdate -divider dpins
|
||||
add wave -noupdate -radix hexadecimal /test_pins/dpin
|
||||
add wave -noupdate -color Gold -radix hexadecimal /test_pins/db
|
||||
add wave -noupdate /test_pins/ctl_db_we
|
||||
add wave -noupdate /test_pins/ctl_db_pin_re
|
||||
add wave -noupdate /test_pins/ctl_db_pin_oe
|
||||
add wave -noupdate /test_pins/ctl_db_oe
|
||||
add wave -noupdate -radix hexadecimal /test_pins/db_w
|
||||
add wave -noupdate -radix hexadecimal /test_pins/dpin_w
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {19000 ns} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 138
|
||||
configure wave -valuecolwidth 54
|
||||
configure wave -justifyvalue right
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
configure wave -timelineunits us
|
||||
update
|
||||
WaveRestoreZoom {0 ns} {57700 ns}
|
||||
@@ -0,0 +1,30 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
# Date created = 09:15:26 October 13, 2014
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "13.0"
|
||||
DATE = "09:15:26 October 13, 2014"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "test_bus"
|
||||
@@ -0,0 +1,77 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
# Date created = 09:15:26 October 13, 2014
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# test_bus_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY "Cyclone II"
|
||||
set_global_assignment -name DEVICE EP2C20F484C7
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY control_pins_n
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:15:26 OCTOBER 13, 2014"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
|
||||
set_global_assignment -name SMART_RECOMPILE ON
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
|
||||
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS OFF
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
|
||||
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
|
||||
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
|
||||
set_global_assignment -name BSF_FILE address_mux.bsf
|
||||
set_global_assignment -name BSF_FILE inc_dec_2bit.bsf
|
||||
set_global_assignment -name BDF_FILE inc_dec_2bit.bdf
|
||||
set_global_assignment -name BDF_FILE inc_dec.bdf
|
||||
set_global_assignment -name BDF_FILE data_switch_mask.bdf
|
||||
set_global_assignment -name BDF_FILE data_switch.bdf
|
||||
set_global_assignment -name BDF_FILE data_pins.bdf
|
||||
set_global_assignment -name BDF_FILE control_pins_n.bdf
|
||||
set_global_assignment -name BDF_FILE bus_control.bdf
|
||||
set_global_assignment -name BDF_FILE address_pins.bdf
|
||||
set_global_assignment -name BDF_FILE address_latch.bdf
|
||||
set_global_assignment -name BDF_FILE address_mux.bdf
|
||||
set_global_assignment -name VERILOG_FILE bus_switch.v
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@@ -0,0 +1,109 @@
|
||||
//==============================================================
|
||||
// Test address latch and increment block
|
||||
//==============================================================
|
||||
`timescale 1us/ 100 ns
|
||||
|
||||
module test_bus;
|
||||
|
||||
// ----------------- CLOCKS AND RESET -----------------
|
||||
// Define one full T-clock cycle delay
|
||||
`define T #2
|
||||
bit clk = 1;
|
||||
initial repeat (26) #1 clk = ~clk;
|
||||
reg nreset;
|
||||
|
||||
// ----------------------------------------------------
|
||||
// Bi-directional bus that can also be tri-stated
|
||||
reg [15:0] abusw; // Drive it using this bus
|
||||
wire [15:0] abus; // Read it using this bus
|
||||
wire [15:0] address; // Final address ouput
|
||||
|
||||
// ----------------- INPUT CONTROL -----------------
|
||||
reg ctl_al_we; // Write enable to address latch
|
||||
reg ctl_bus_inc_oe; // Write incrementer onto the internal data bus
|
||||
reg ctl_apin_mux; // Selects mux1
|
||||
reg ctl_apin_mux2; // Selects mux2
|
||||
|
||||
// ----------------- INC/DEC -----------------
|
||||
reg ctl_inc_dec; // Perform decrement (1) or increment (0)
|
||||
reg ctl_inc_limit6; // Limit increment to 6 bits (for incrementing IR)
|
||||
reg ctl_inc_cy; // Address increment, carry in value (+/-1 or 0)
|
||||
reg clrpc; // Force zero (to clear PC/IR)
|
||||
|
||||
// ----------------- OUTPUT/STATUS -----------------
|
||||
wire address_is_1; // Signals when the final address is 1
|
||||
|
||||
// ----------------- TEST -------------------
|
||||
`define CHECK(arg) \
|
||||
assert(address==arg);
|
||||
|
||||
initial begin
|
||||
nreset = 0;
|
||||
abusw = 'z;
|
||||
ctl_al_we = 0;
|
||||
ctl_bus_inc_oe = 0;
|
||||
ctl_inc_dec = 0;
|
||||
ctl_inc_limit6 = 0;
|
||||
ctl_inc_cy = 0;
|
||||
clrpc = 0;
|
||||
ctl_apin_mux = 0;
|
||||
ctl_apin_mux2 = 0;
|
||||
|
||||
//------------------------------------------------------------
|
||||
`T nreset = 1;
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Perform a simple increment and decrement
|
||||
`T abusw = 16'h1234;
|
||||
ctl_al_we = 1; // Write value to the latch
|
||||
ctl_apin_mux = 1; // Output incrementer to the address bus
|
||||
ctl_inc_cy = 1; // +1 show "1235"
|
||||
`T `CHECK(16'h1235);
|
||||
ctl_inc_dec = 1; // -1 show "1233"
|
||||
`T `CHECK(16'h1233);
|
||||
// ...through overflow
|
||||
abusw = 16'hffff;
|
||||
ctl_inc_dec = 0;
|
||||
ctl_inc_cy = 1; // +1 show "0"
|
||||
`T `CHECK(16'h0000);
|
||||
ctl_inc_dec = 1; // -1 show "FFFE"
|
||||
`T `CHECK(16'hFFFE);
|
||||
abusw = 16'h0;
|
||||
ctl_inc_dec = 0;
|
||||
ctl_inc_cy = 1; // +1 show "1"
|
||||
`T `CHECK(16'h0001);
|
||||
ctl_inc_dec = 1; // -1 show "FFFF"
|
||||
`T `CHECK(16'hFFFF);
|
||||
ctl_inc_cy = 0; // show "0000"
|
||||
`T `CHECK(16'h0000);
|
||||
ctl_inc_dec = 0; // show "0000"
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Test the address latch and the mux
|
||||
`T abusw = 16'hAA50;
|
||||
ctl_al_we = 1; // Write AA55 to the latch
|
||||
ctl_inc_cy = 1;
|
||||
`T ctl_al_we = 0; // show "AA51"
|
||||
`T `CHECK(16'hAA51);
|
||||
ctl_apin_mux = 0;
|
||||
ctl_apin_mux2 = 1;
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Test the tri-state db
|
||||
`T abusw = 'z;
|
||||
ctl_bus_inc_oe = 1; // Output latched value (AA50)
|
||||
`T `CHECK(16'hAA50);
|
||||
|
||||
`T $display("End of test");
|
||||
end
|
||||
|
||||
// Drive 3-state bidirectional bus with these statements
|
||||
assign abus = abusw;
|
||||
|
||||
//--------------------------------------------------------------
|
||||
// Instantiate address latch block
|
||||
//--------------------------------------------------------------
|
||||
|
||||
address_latch address_latch_( .* );
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,105 @@
|
||||
//==============================================================
|
||||
// Test address and data pins blocks
|
||||
//==============================================================
|
||||
`timescale 1us/ 100 ns
|
||||
|
||||
module test_pins;
|
||||
|
||||
// ----------------- CLOCKS AND RESET -----------------
|
||||
// Define one full T-clock cycle delay
|
||||
`define T #2
|
||||
bit clk = 1;
|
||||
initial repeat (24) #1 clk = ~clk;
|
||||
|
||||
// ------------------------ ADDRESS PINS ---------------------
|
||||
logic [15:0] ab; // Internal address bus
|
||||
logic ctl_ab_we; // Write enable to address pin latch
|
||||
logic pin_control_oe; // Output enable to address pins; otherwise tri-stated
|
||||
wire [15:0] apin; // Output address bus to address pins
|
||||
|
||||
// ------------------------ DATA PINS ------------------------
|
||||
logic ctl_db_we; // Write enable to data pin output latch
|
||||
logic ctl_db_oe; // Output enable to internal data bus
|
||||
logic ctl_db_pin_re; // Read from the data pin into the latch
|
||||
logic ctl_db_pin_oe; // Output enable to data pins; otherwise tri-stated
|
||||
logic ctl_pin_oe;
|
||||
|
||||
// ----------------------------------------------------
|
||||
// Bidirectional internal data bus
|
||||
logic [7:0] db_w; // Drive it using this bus
|
||||
wire [7:0] db; // Read it using this bus
|
||||
assign db = db_w; // Drive 3-state bidirectional bus
|
||||
always_comb // Output to pin bus only when our
|
||||
begin // test is not driving it
|
||||
if (db_w==='z)
|
||||
ctl_db_oe = 1;
|
||||
else
|
||||
ctl_db_oe = 0;
|
||||
end
|
||||
|
||||
// ----------------------------------------------------
|
||||
// Bidirectional external data pins
|
||||
logic [7:0] dpin_w; // Drive it using this bus
|
||||
wire [7:0] dpin; // Read it using this bus
|
||||
assign dpin = dpin_w; // Drive 3-state bidirectional
|
||||
always_comb // Output to pin bus only when our
|
||||
begin // test is not driving it
|
||||
if (dpin_w==='z)
|
||||
ctl_db_pin_oe = 1;
|
||||
else
|
||||
ctl_db_pin_oe = 0;
|
||||
end
|
||||
|
||||
// ----------------- TEST -------------------
|
||||
`define CHECKA(arg) \
|
||||
assert(apin===arg);
|
||||
|
||||
`define CHECKD(arg) \
|
||||
assert(dpin===arg);
|
||||
|
||||
initial begin
|
||||
ab = 16'h0;
|
||||
ctl_ab_we = 0;
|
||||
pin_control_oe = 0;
|
||||
db_w = 'z;
|
||||
dpin_w = 'z;
|
||||
ctl_db_we = 0;
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Test the address pin logic
|
||||
`T ab = 16'hAA55; // Latch a value and output it
|
||||
ctl_ab_we = 1;
|
||||
pin_control_oe = 1;
|
||||
`T ctl_ab_we = 0;
|
||||
`T `CHECKA(16'hAA55);
|
||||
pin_control_oe = 0;
|
||||
ab = 16'h1234; // Should not affect
|
||||
`T pin_control_oe = 1; // Toggle output on and off
|
||||
`T `CHECKA(16'hAA55);
|
||||
pin_control_oe = 0;
|
||||
`T `CHECKA(16'hz);
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Test the data pin logic
|
||||
`T dpin_w = 8'hAA; // Load and latch a value
|
||||
ctl_db_pin_re = 1; // Read into the latch
|
||||
|
||||
`T dpin_w = 'z;
|
||||
db_w = 8'h55;
|
||||
ctl_db_pin_re = 0;
|
||||
ctl_db_we = 1;
|
||||
`CHECKD(8'hAA);
|
||||
`T db_w = 'z;
|
||||
|
||||
`T $display("End of test");
|
||||
end
|
||||
|
||||
//--------------------------------------------------------------
|
||||
// Instantiate bus block and assign identical nets and variables
|
||||
//--------------------------------------------------------------
|
||||
|
||||
address_pins address_pins_inst( .*, .bus_ab_pin_we(ctl_ab_we), .address(ab[15:0]), .abus(apin[15:0]) );
|
||||
|
||||
data_pins data_pins_inst( .*, .ctl_bus_db_oe(ctl_db_pin_oe), .ctl_bus_db_we(ctl_db_we), .bus_db_pin_oe(ctl_db_pin_oe), .bus_db_pin_re(ctl_db_pin_re), .D(dpin[7:0]) );
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user