Merge branch 'sdram'

2022-04-06 14:02:22 +03:00
parent f114ff0549 9966f9a3a6
commit 1f14c8c3bd
401 changed files with 615659 additions and 422586 deletions
@@ -1,13 +1,13 @@
 |spectrum
-LED[0] <= SW[1].DB_MAX_OUTPUT_PORT_TYPE
-LED[1] <= <GND>
-LED[2] <= SW[2].DB_MAX_OUTPUT_PORT_TYPE
-LED[3] <= raw_loader_in.DB_MAX_OUTPUT_PORT_TYPE
-LED[4] <= <GND>
-LED[5] <= <GND>
-LED[6] <= <GND>
-LED[7] <= <GND>
-CLOCK_50 => CLOCK_50.IN2
+LED[0] << SW[1].DB_MAX_OUTPUT_PORT_TYPE
+LED[1] << raw_loader_in.DB_MAX_OUTPUT_PORT_TYPE
+LED[2] << turbo.DB_MAX_OUTPUT_PORT_TYPE
+LED[3] << kempston[0].DB_MAX_OUTPUT_PORT_TYPE
+LED[4] << kempston[1].DB_MAX_OUTPUT_PORT_TYPE
+LED[5] << kempston[2].DB_MAX_OUTPUT_PORT_TYPE
+LED[6] << kempston[3].DB_MAX_OUTPUT_PORT_TYPE
+LED[7] << LED.DB_MAX_OUTPUT_PORT_TYPE
+CLOCK_50 => CLOCK_50.IN6
 KEY[0] => reset.IN1
 KEY[1] => nNMI.IN1
 PS2_CLK => PS2_CLK.IN1
@@ -37,44 +37,150 @@ VGA_VS <= ula:ula_.VGA_VS
 SW[0] => ~NO_FANOUT~
 SW[1] => LED[0].DATAIN
 SW[1] => comb.OUTPUTSELECT
-SW[2] => SW[2].IN1
+SW[2] => ~NO_FANOUT~
 SW[3] => ~NO_FANOUT~
-GPIO_1[0] <= A[0].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[1] <= A[1].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[2] <= A[2].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[3] <= A[3].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[4] <= A[4].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[5] <= A[5].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[6] <= A[6].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[7] <= A[7].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[8] <= A[8].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[9] <= A[9].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[10] <= A[10].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[11] <= A[11].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[12] <= A[12].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[13] <= A[13].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[14] <= A[14].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[15] <= A[15].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[16] <= D[0].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[17] <= D[1].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[18] <= D[2].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[19] <= D[3].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[20] <= D[4].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[21] <= D[5].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[22] <= D[6].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[23] <= D[7].DB_MAX_OUTPUT_PORT_TYPE
-GPIO_1[24] <= z80_top_direct_n:z80_.nBUSACK
-GPIO_1[25] <= z80_top_direct_n:z80_.nHALT
-GPIO_1[26] <= z80_top_direct_n:z80_.nRFSH
-GPIO_1[27] <= z80_top_direct_n:z80_.nWR
-GPIO_1[28] <= z80_top_direct_n:z80_.nRD
-GPIO_1[29] <= z80_top_direct_n:z80_.nIORQ
-GPIO_1[30] <= z80_top_direct_n:z80_.nMREQ
-GPIO_1[31] <= z80_top_direct_n:z80_.nM1
-GPIO_1[32] <= <GND>
-GPIO_1[33] <= <GND>
-buzzer_out <= ula:ula_.beep
+GPIO_1[0] << A[0].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[1] << A[1].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[2] << A[2].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[3] << A[3].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[4] << A[4].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[5] << A[5].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[6] << A[6].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[7] << A[7].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[8] << A[8].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[9] << A[9].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[10] << A[10].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[11] << A[11].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[12] << A[12].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[13] << A[13].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[14] << A[14].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[15] << A[15].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[16] << D[0].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[17] << D[1].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[18] << D[2].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[19] << D[3].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[20] << D[4].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[21] << D[5].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[22] << D[6].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[23] << D[7].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1[24] << z80_top_direct_n:z80_.nBUSACK
+GPIO_1[25] << z80_top_direct_n:z80_.nHALT
+GPIO_1[26] << z80_top_direct_n:z80_.nRFSH
+GPIO_1[27] << z80_top_direct_n:z80_.nWR
+GPIO_1[28] << z80_top_direct_n:z80_.nRD
+GPIO_1[29] << z80_top_direct_n:z80_.nIORQ
+GPIO_1[30] << z80_top_direct_n:z80_.nMREQ
+GPIO_1[31] << z80_top_direct_n:z80_.nM1
+buzzer_out << ula:ula_.beep
 raw_loader_in => raw_loader_in.IN1
+DRAM_BA[0] << sdram_controller:sdram_.DRAM_BA
+DRAM_BA[1] << sdram_controller:sdram_.DRAM_BA
+DRAM_DQM[0] << sdram_controller:sdram_.DRAM_DQM
+DRAM_DQM[1] << sdram_controller:sdram_.DRAM_DQM
+DRAM_RAS_N << sdram_controller:sdram_.DRAM_RAS_N
+DRAM_CAS_N << sdram_controller:sdram_.DRAM_CAS_N
+DRAM_CKE << sdram_controller:sdram_.DRAM_CKE
+DRAM_CLK << sdram_controller:sdram_.DRAM_CLK
+DRAM_WE_N << sdram_controller:sdram_.DRAM_WE_N
+DRAM_CS_N << sdram_controller:sdram_.DRAM_CS_N
+DRAM_DQ[0] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_DQ[1] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_DQ[2] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_DQ[3] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_DQ[4] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_DQ[5] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_DQ[6] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_DQ[7] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_DQ[8] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_DQ[9] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_DQ[10] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_DQ[11] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_DQ[12] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_DQ[13] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_DQ[14] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_DQ[15] <> sdram_controller:sdram_.DRAM_DQ
+DRAM_ADDR[0] << sdram_controller:sdram_.DRAM_ADDR
+DRAM_ADDR[1] << sdram_controller:sdram_.DRAM_ADDR
+DRAM_ADDR[2] << sdram_controller:sdram_.DRAM_ADDR
+DRAM_ADDR[3] << sdram_controller:sdram_.DRAM_ADDR
+DRAM_ADDR[4] << sdram_controller:sdram_.DRAM_ADDR
+DRAM_ADDR[5] << sdram_controller:sdram_.DRAM_ADDR
+DRAM_ADDR[6] << sdram_controller:sdram_.DRAM_ADDR
+DRAM_ADDR[7] << sdram_controller:sdram_.DRAM_ADDR
+DRAM_ADDR[8] << sdram_controller:sdram_.DRAM_ADDR
+DRAM_ADDR[9] << sdram_controller:sdram_.DRAM_ADDR
+DRAM_ADDR[10] << sdram_controller:sdram_.DRAM_ADDR
+DRAM_ADDR[11] << sdram_controller:sdram_.DRAM_ADDR
+DRAM_ADDR[12] << sdram_controller:sdram_.DRAM_ADDR
+kempston[0] => LED[3].DATAIN
+kempston[0] => D.DATAB
+kempston[1] => LED[4].DATAIN
+kempston[1] => D.DATAB
+kempston[2] => LED[5].DATAIN
+kempston[2] => D.DATAB
+kempston[3] => LED[6].DATAIN
+kempston[3] => D.DATAB
+kempston[4] => LED.IN1
+kempston[4] => D.IN1
+kempston_gnd << <GND>
+turbo_button => turbo_button.IN1
+kempston_autofire_button => kempston_autofire_button.IN1
+
+
+|spectrum|debouncer:debounce_turbo
+i_Clk => r_State.CLK
+i_Clk => r_Count[0].CLK
+i_Clk => r_Count[1].CLK
+i_Clk => r_Count[2].CLK
+i_Clk => r_Count[3].CLK
+i_Clk => r_Count[4].CLK
+i_Clk => r_Count[5].CLK
+i_Clk => r_Count[6].CLK
+i_Clk => r_Count[7].CLK
+i_Clk => r_Count[8].CLK
+i_Clk => r_Count[9].CLK
+i_Clk => r_Count[10].CLK
+i_Clk => r_Count[11].CLK
+i_Clk => r_Count[12].CLK
+i_Clk => r_Count[13].CLK
+i_Clk => r_Count[14].CLK
+i_Clk => r_Count[15].CLK
+i_Clk => r_Count[16].CLK
+i_Clk => r_Count[17].CLK
+i_Clk => r_Count[18].CLK
+i_Clk => r_Count[19].CLK
+i_Clk => r_Count[20].CLK
+i_Switch => always0.IN1
+i_Switch => r_State.DATAB
+o_Switch <= r_State.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|spectrum|debouncer:debounce_autofire
+i_Clk => r_State.CLK
+i_Clk => r_Count[0].CLK
+i_Clk => r_Count[1].CLK
+i_Clk => r_Count[2].CLK
+i_Clk => r_Count[3].CLK
+i_Clk => r_Count[4].CLK
+i_Clk => r_Count[5].CLK
+i_Clk => r_Count[6].CLK
+i_Clk => r_Count[7].CLK
+i_Clk => r_Count[8].CLK
+i_Clk => r_Count[9].CLK
+i_Clk => r_Count[10].CLK
+i_Clk => r_Count[11].CLK
+i_Clk => r_Count[12].CLK
+i_Clk => r_Count[13].CLK
+i_Clk => r_Count[14].CLK
+i_Clk => r_Count[15].CLK
+i_Clk => r_Count[16].CLK
+i_Clk => r_Count[17].CLK
+i_Clk => r_Count[18].CLK
+i_Clk => r_Count[19].CLK
+i_Clk => r_Count[20].CLK
+i_Switch => always0.IN1
+i_Switch => r_State.DATAB
+o_Switch <= r_State.DB_MAX_OUTPUT_PORT_TYPE


 |spectrum|rom0:rom
@@ -1991,6 +2097,298 @@ sel[1] => _.IN0
 sel[1] => _.IN0


+|spectrum|sdram_controller:sdram_
+CLOCK_50 => sdram_clk_gen:sdram_clk_pll.inclk0
+DRAM_ADDR[0] <= r.address[0].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_ADDR[1] <= r.address[1].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_ADDR[2] <= r.address[2].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_ADDR[3] <= r.address[3].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_ADDR[4] <= r.address[4].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_ADDR[5] <= r.address[5].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_ADDR[6] <= r.address[6].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_ADDR[7] <= r.address[7].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_ADDR[8] <= r.address[8].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_ADDR[9] <= r.address[9].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_ADDR[10] <= r.address[10].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_ADDR[11] <= r.address[11].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_ADDR[12] <= r.address[12].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_BA[0] <= r.bank[0].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_BA[1] <= r.bank[1].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_CAS_N <= r.state[1].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_CKE <= <VCC>
+DRAM_CLK <= sdram_clk_gen:sdram_clk_pll.c1
+DRAM_CS_N <= r.state[3].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_DQ[0] <> DRAM_DQ[0]
+DRAM_DQ[1] <> DRAM_DQ[1]
+DRAM_DQ[2] <> DRAM_DQ[2]
+DRAM_DQ[3] <> DRAM_DQ[3]
+DRAM_DQ[4] <> DRAM_DQ[4]
+DRAM_DQ[5] <> DRAM_DQ[5]
+DRAM_DQ[6] <> DRAM_DQ[6]
+DRAM_DQ[7] <> DRAM_DQ[7]
+DRAM_DQ[8] <> DRAM_DQ[8]
+DRAM_DQ[9] <> DRAM_DQ[9]
+DRAM_DQ[10] <> DRAM_DQ[10]
+DRAM_DQ[11] <> DRAM_DQ[11]
+DRAM_DQ[12] <> DRAM_DQ[12]
+DRAM_DQ[13] <> DRAM_DQ[13]
+DRAM_DQ[14] <> DRAM_DQ[14]
+DRAM_DQ[15] <> DRAM_DQ[15]
+DRAM_DQM[0] <= r.dq_masks[0].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_DQM[1] <= r.dq_masks[1].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_RAS_N <= r.state[2].DB_MAX_OUTPUT_PORT_TYPE
+DRAM_WE_N <= r.state[0].DB_MAX_OUTPUT_PORT_TYPE
+address[0] => ~NO_FANOUT~
+address[1] => n.DATAB
+address[1] => n.DATAB
+address[1] => Mux22.IN36
+address[2] => n.DATAB
+address[2] => n.DATAB
+address[2] => Mux21.IN36
+address[3] => n.DATAB
+address[3] => n.DATAB
+address[3] => Mux20.IN36
+address[4] => n.DATAB
+address[4] => n.DATAB
+address[4] => Mux19.IN36
+address[5] => n.DATAB
+address[5] => n.DATAB
+address[5] => Mux18.IN36
+address[6] => n.DATAB
+address[6] => n.DATAB
+address[6] => Mux17.IN36
+address[7] => n.DATAB
+address[7] => n.DATAB
+address[7] => Mux16.IN36
+address[8] => n.DATAB
+address[8] => n.DATAB
+address[8] => Mux15.IN36
+address[9] => n.DATAB
+address[9] => n.DATAB
+address[9] => n.DATAB
+address[9] => Mux26.IN36
+address[10] => n.DATAB
+address[10] => n.DATAB
+address[10] => n.DATAB
+address[10] => Mux25.IN36
+address[11] => Equal7.IN25
+address[11] => n.DATAB
+address[11] => n.DATAB
+address[12] => Equal7.IN24
+address[12] => n.DATAB
+address[12] => n.DATAB
+address[13] => Equal7.IN23
+address[13] => n.DATAB
+address[13] => n.DATAB
+address[14] => Equal7.IN22
+address[14] => n.DATAB
+address[14] => n.DATAB
+address[15] => Equal7.IN21
+address[15] => n.DATAB
+address[15] => n.DATAB
+address[16] => Equal7.IN20
+address[16] => n.DATAB
+address[16] => n.DATAB
+address[17] => Equal7.IN19
+address[17] => n.DATAB
+address[17] => n.DATAB
+address[18] => Equal7.IN18
+address[18] => n.DATAB
+address[18] => n.DATAB
+address[19] => Equal7.IN17
+address[19] => n.DATAB
+address[19] => n.DATAB
+address[20] => Equal7.IN16
+address[20] => n.DATAB
+address[20] => n.DATAB
+address[21] => Equal7.IN15
+address[21] => n.DATAB
+address[21] => n.DATAB
+address[22] => Equal7.IN14
+address[22] => n.DATAB
+address[22] => n.DATAB
+address[23] => Equal7.IN13
+address[23] => n.DATAB
+address[23] => n.DATAB
+req_read => n.OUTPUTSELECT
+req_read => n.OUTPUTSELECT
+req_write => n.OUTPUTSELECT
+req_write => n.OUTPUTSELECT
+data_out[0] <= r.data_out_low[0].DB_MAX_OUTPUT_PORT_TYPE
+data_out[1] <= r.data_out_low[1].DB_MAX_OUTPUT_PORT_TYPE
+data_out[2] <= r.data_out_low[2].DB_MAX_OUTPUT_PORT_TYPE
+data_out[3] <= r.data_out_low[3].DB_MAX_OUTPUT_PORT_TYPE
+data_out[4] <= r.data_out_low[4].DB_MAX_OUTPUT_PORT_TYPE
+data_out[5] <= r.data_out_low[5].DB_MAX_OUTPUT_PORT_TYPE
+data_out[6] <= r.data_out_low[6].DB_MAX_OUTPUT_PORT_TYPE
+data_out[7] <= r.data_out_low[7].DB_MAX_OUTPUT_PORT_TYPE
+data_out[8] <= r.data_out_low[8].DB_MAX_OUTPUT_PORT_TYPE
+data_out[9] <= r.data_out_low[9].DB_MAX_OUTPUT_PORT_TYPE
+data_out[10] <= r.data_out_low[10].DB_MAX_OUTPUT_PORT_TYPE
+data_out[11] <= r.data_out_low[11].DB_MAX_OUTPUT_PORT_TYPE
+data_out[12] <= r.data_out_low[12].DB_MAX_OUTPUT_PORT_TYPE
+data_out[13] <= r.data_out_low[13].DB_MAX_OUTPUT_PORT_TYPE
+data_out[14] <= r.data_out_low[14].DB_MAX_OUTPUT_PORT_TYPE
+data_out[15] <= r.data_out_low[15].DB_MAX_OUTPUT_PORT_TYPE
+data_out[16] <= captured[0].DB_MAX_OUTPUT_PORT_TYPE
+data_out[17] <= captured[1].DB_MAX_OUTPUT_PORT_TYPE
+data_out[18] <= captured[2].DB_MAX_OUTPUT_PORT_TYPE
+data_out[19] <= captured[3].DB_MAX_OUTPUT_PORT_TYPE
+data_out[20] <= captured[4].DB_MAX_OUTPUT_PORT_TYPE
+data_out[21] <= captured[5].DB_MAX_OUTPUT_PORT_TYPE
+data_out[22] <= captured[6].DB_MAX_OUTPUT_PORT_TYPE
+data_out[23] <= captured[7].DB_MAX_OUTPUT_PORT_TYPE
+data_out[24] <= captured[8].DB_MAX_OUTPUT_PORT_TYPE
+data_out[25] <= captured[9].DB_MAX_OUTPUT_PORT_TYPE
+data_out[26] <= captured[10].DB_MAX_OUTPUT_PORT_TYPE
+data_out[27] <= captured[11].DB_MAX_OUTPUT_PORT_TYPE
+data_out[28] <= captured[12].DB_MAX_OUTPUT_PORT_TYPE
+data_out[29] <= captured[13].DB_MAX_OUTPUT_PORT_TYPE
+data_out[30] <= captured[14].DB_MAX_OUTPUT_PORT_TYPE
+data_out[31] <= captured[15].DB_MAX_OUTPUT_PORT_TYPE
+data_out_valid <= r.data_out_valid.DB_MAX_OUTPUT_PORT_TYPE
+data_in[0] => Mux72.IN30
+data_in[0] => Mux72.IN31
+data_in[1] => Mux3.IN30
+data_in[1] => Mux3.IN31
+data_in[2] => Mux2.IN30
+data_in[2] => Mux2.IN31
+data_in[3] => Mux1.IN30
+data_in[3] => Mux1.IN31
+data_in[4] => Mux0.IN30
+data_in[4] => Mux0.IN31
+data_in[5] => Mux73.IN30
+data_in[5] => Mux73.IN31
+data_in[6] => Mux74.IN30
+data_in[6] => Mux74.IN31
+data_in[7] => Mux75.IN30
+data_in[7] => Mux75.IN31
+data_in[8] => Mux76.IN30
+data_in[8] => Mux76.IN31
+data_in[9] => Mux77.IN30
+data_in[9] => Mux77.IN31
+data_in[10] => Mux78.IN30
+data_in[10] => Mux78.IN31
+data_in[11] => Mux79.IN30
+data_in[11] => Mux79.IN31
+data_in[12] => Mux80.IN30
+data_in[12] => Mux80.IN31
+data_in[13] => Mux81.IN30
+data_in[13] => Mux81.IN31
+data_in[14] => Mux82.IN30
+data_in[14] => Mux82.IN31
+data_in[15] => Mux83.IN30
+data_in[15] => Mux83.IN31
+data_in[16] => Mux72.IN28
+data_in[16] => Mux72.IN29
+data_in[17] => Mux3.IN28
+data_in[17] => Mux3.IN29
+data_in[18] => Mux2.IN28
+data_in[18] => Mux2.IN29
+data_in[19] => Mux1.IN28
+data_in[19] => Mux1.IN29
+data_in[20] => Mux0.IN28
+data_in[20] => Mux0.IN29
+data_in[21] => Mux73.IN28
+data_in[21] => Mux73.IN29
+data_in[22] => Mux74.IN28
+data_in[22] => Mux74.IN29
+data_in[23] => Mux75.IN28
+data_in[23] => Mux75.IN29
+data_in[24] => Mux76.IN28
+data_in[24] => Mux76.IN29
+data_in[25] => Mux77.IN28
+data_in[25] => Mux77.IN29
+data_in[26] => Mux78.IN28
+data_in[26] => Mux78.IN29
+data_in[27] => Mux79.IN28
+data_in[27] => Mux79.IN29
+data_in[28] => Mux80.IN28
+data_in[28] => Mux80.IN29
+data_in[29] => Mux81.IN28
+data_in[29] => Mux81.IN29
+data_in[30] => Mux82.IN28
+data_in[30] => Mux82.IN29
+data_in[31] => Mux83.IN28
+data_in[31] => Mux83.IN29
+
+
+|spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll
+inclk0 => sub_wire4[0].IN1
+c0 <= altpll:altpll_component.clk
+c1 <= altpll:altpll_component.clk
+
+
+|spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component
+inclk[0] => sdram_clk_gen_altpll:auto_generated.inclk[0]
+inclk[1] => sdram_clk_gen_altpll:auto_generated.inclk[1]
+fbin => ~NO_FANOUT~
+pllena => ~NO_FANOUT~
+clkswitch => ~NO_FANOUT~
+areset => ~NO_FANOUT~
+pfdena => ~NO_FANOUT~
+clkena[0] => ~NO_FANOUT~
+clkena[1] => ~NO_FANOUT~
+clkena[2] => ~NO_FANOUT~
+clkena[3] => ~NO_FANOUT~
+clkena[4] => ~NO_FANOUT~
+clkena[5] => ~NO_FANOUT~
+extclkena[0] => ~NO_FANOUT~
+extclkena[1] => ~NO_FANOUT~
+extclkena[2] => ~NO_FANOUT~
+extclkena[3] => ~NO_FANOUT~
+scanclk => ~NO_FANOUT~
+scanclkena => ~NO_FANOUT~
+scanaclr => ~NO_FANOUT~
+scanread => ~NO_FANOUT~
+scanwrite => ~NO_FANOUT~
+scandata => ~NO_FANOUT~
+phasecounterselect[0] => ~NO_FANOUT~
+phasecounterselect[1] => ~NO_FANOUT~
+phasecounterselect[2] => ~NO_FANOUT~
+phasecounterselect[3] => ~NO_FANOUT~
+phaseupdown => ~NO_FANOUT~
+phasestep => ~NO_FANOUT~
+configupdate => ~NO_FANOUT~
+fbmimicbidir <> <GND>
+clk[0] <= clk[0].DB_MAX_OUTPUT_PORT_TYPE
+clk[1] <= clk[1].DB_MAX_OUTPUT_PORT_TYPE
+clk[2] <= clk[2].DB_MAX_OUTPUT_PORT_TYPE
+clk[3] <= clk[3].DB_MAX_OUTPUT_PORT_TYPE
+clk[4] <= clk[4].DB_MAX_OUTPUT_PORT_TYPE
+extclk[0] <= <GND>
+extclk[1] <= <GND>
+extclk[2] <= <GND>
+extclk[3] <= <GND>
+clkbad[0] <= <GND>
+clkbad[1] <= <GND>
+enable1 <= <GND>
+enable0 <= <GND>
+activeclock <= <GND>
+clkloss <= <GND>
+locked <= <GND>
+scandataout <= <GND>
+scandone <= <GND>
+sclkout0 <= <GND>
+sclkout1 <= <GND>
+phasedone <= <GND>
+vcooverrange <= <GND>
+vcounderrange <= <GND>
+fbout <= <GND>
+fref <= <GND>
+icdrclk <= <GND>
+
+
+|spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated
+clk[0] <= pll1.CLK
+clk[1] <= pll1.CLK1
+clk[2] <= pll1.CLK2
+clk[3] <= pll1.CLK3
+clk[4] <= pll1.CLK4
+inclk[0] => pll1.CLK
+inclk[1] => pll1.CLK1
+
+
 |spectrum|ula:ula_
 CLOCK_50 => CLOCK_50.IN1
 turbo => clocks:clocks_.turbo