14 lines
176 B
Verilog
14 lines
176 B
Verilog
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module spectrum(
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input CLOCK_50,
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output reg[7:0] LED
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);
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reg[27:0] counter;
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always @(posedge CLOCK_50)
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begin
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counter <= counter + 1;
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LED <= counter[27:21];
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end
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endmodule
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