58 lines
3.1 KiB
Plaintext
58 lines
3.1 KiB
Plaintext
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--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_DECODES=6 LPM_WIDTH=3 data enable eq
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--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ VERSION_END
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-- Copyright (C) 1991-2013 Altera Corporation
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, Altera MegaCore Function License
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-- Agreement, or other applicable license agreement, including,
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-- without limitation, that your use is for the sole purpose of
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-- programming logic devices manufactured by Altera and sold by
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-- Altera or its authorized distributors. Please refer to the
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-- applicable agreement for further details.
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--synthesis_resources = lut 8
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SUBDESIGN decode_psa
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(
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data[2..0] : input;
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enable : input;
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eq[5..0] : output;
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)
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VARIABLE
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data_wire[2..0] : WIRE;
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enable_wire : WIRE;
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eq_node[5..0] : WIRE;
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eq_wire[7..0] : WIRE;
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w_anode653w[3..0] : WIRE;
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w_anode670w[3..0] : WIRE;
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w_anode680w[3..0] : WIRE;
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w_anode690w[3..0] : WIRE;
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w_anode700w[3..0] : WIRE;
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w_anode710w[3..0] : WIRE;
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w_anode720w[3..0] : WIRE;
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w_anode730w[3..0] : WIRE;
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BEGIN
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data_wire[] = data[];
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enable_wire = enable;
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eq[] = eq_node[];
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eq_node[5..0] = eq_wire[5..0];
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eq_wire[] = ( w_anode730w[3..3], w_anode720w[3..3], w_anode710w[3..3], w_anode700w[3..3], w_anode690w[3..3], w_anode680w[3..3], w_anode670w[3..3], w_anode653w[3..3]);
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w_anode653w[] = ( (w_anode653w[2..2] & (! data_wire[2..2])), (w_anode653w[1..1] & (! data_wire[1..1])), (w_anode653w[0..0] & (! data_wire[0..0])), enable_wire);
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w_anode670w[] = ( (w_anode670w[2..2] & (! data_wire[2..2])), (w_anode670w[1..1] & (! data_wire[1..1])), (w_anode670w[0..0] & data_wire[0..0]), enable_wire);
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w_anode680w[] = ( (w_anode680w[2..2] & (! data_wire[2..2])), (w_anode680w[1..1] & data_wire[1..1]), (w_anode680w[0..0] & (! data_wire[0..0])), enable_wire);
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w_anode690w[] = ( (w_anode690w[2..2] & (! data_wire[2..2])), (w_anode690w[1..1] & data_wire[1..1]), (w_anode690w[0..0] & data_wire[0..0]), enable_wire);
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w_anode700w[] = ( (w_anode700w[2..2] & data_wire[2..2]), (w_anode700w[1..1] & (! data_wire[1..1])), (w_anode700w[0..0] & (! data_wire[0..0])), enable_wire);
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w_anode710w[] = ( (w_anode710w[2..2] & data_wire[2..2]), (w_anode710w[1..1] & (! data_wire[1..1])), (w_anode710w[0..0] & data_wire[0..0]), enable_wire);
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w_anode720w[] = ( (w_anode720w[2..2] & data_wire[2..2]), (w_anode720w[1..1] & data_wire[1..1]), (w_anode720w[0..0] & (! data_wire[0..0])), enable_wire);
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w_anode730w[] = ( (w_anode730w[2..2] & data_wire[2..2]), (w_anode730w[1..1] & data_wire[1..1]), (w_anode730w[0..0] & data_wire[0..0]), enable_wire);
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END;
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--VALID FILE
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