34 lines
1.3 KiB
Plaintext
34 lines
1.3 KiB
Plaintext
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A-Z80 Logic Design
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==================
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Each functional block contains a Quartus project file:
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./<block>/test_<block>.qpf
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Quartus projects are only used as containers for files within individual
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modules; complete and working top-level solutions that use A-Z80 are in the
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"host" folder.
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Majority of sub-modules are designed in the Quartus schematic editor and then
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exported to Verilog for simulation and top-level integration.
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Simulation
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==========
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Before you can load and simulate any module through Modelsim, you need to set up
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the environment by running 'modelsim_setup.py'. The script creates relative file
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path mapping to source files in all module project folders.
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Each functional block, including the top level, contains a Modelsim simulation
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profile: ./<block>/simulation/modelsim/test_<block>.mpf
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After opening a Modelsim session, create a library and compile sources:
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ModelSim> vlib work
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Compile->Compile All
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Run a simulation through one of the defined configurations.
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If you get a message "Unable to compile", you likely forgot to run 'modelsim_setup.py'.
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Exit ModelSim, revert changes to ".mpf" file, delete "work" folder and run
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'modelsim_setup.py'.
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Each project contains a set of predefined waveform scripts which you can
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load before running a simulation:
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./<block>/simulation/modelsim/wave_<test>.do
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