59 lines
1.4 KiB
Verilog
59 lines
1.4 KiB
Verilog
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// Copyright (C) 1991-2013 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// CREATED "Sat Dec 10 08:56:46 2016"
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module ir(
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ctl_ir_we,
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clk,
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nreset,
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nhold_clk_wait,
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db,
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opcode
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);
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input wire ctl_ir_we;
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input wire clk;
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input wire nreset;
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input wire nhold_clk_wait;
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input wire [7:0] db;
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output reg [7:0] opcode;
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wire SYNTHESIZED_WIRE_0;
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assign SYNTHESIZED_WIRE_0 = ctl_ir_we & nhold_clk_wait;
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always@(posedge clk or negedge nreset)
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begin
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if (!nreset)
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begin
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opcode[7:0] <= 8'b00000000;
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end
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else
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if (SYNTHESIZED_WIRE_0)
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begin
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opcode[7:0] <= db[7:0];
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end
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end
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endmodule
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