87 lines
2.1 KiB
Systemverilog
87 lines
2.1 KiB
Systemverilog
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//==============================================================
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// Test ALU state preparation for DAA instruction
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//==============================================================
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`timescale 100 ns/ 100 ns
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module test_prep_daa;
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// ----------------- INPUT -----------------
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reg [3:0] low_sig; // Input data bus A (independent)
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reg [3:0] high_sig; // Input data bus B (independent)
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// ----------------- OUTPUT -----------------
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wire low_gt_9_sig; // low bus > 9
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wire high_gt_9_sig; // high bus > 9
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wire high_eq_9_sig; // high bus == 9
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// ----------------- TEST -------------------
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`define CHECK \
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assert(low_gt_9_sig==low_sig>9 && high_gt_9_sig==high_sig>9 && high_eq_9_sig==(high_sig==9));
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initial begin
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low_sig = 4'h0;
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high_sig = 4'h0;
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#1 `CHECK
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low_sig = 4'h1;
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high_sig = 4'h1;
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#1 `CHECK
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low_sig = 4'h2;
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high_sig = 4'h2;
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#1 `CHECK
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low_sig = 4'h3;
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high_sig = 4'h3;
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#1 `CHECK
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low_sig = 4'h4;
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high_sig = 4'h4;
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#1 `CHECK
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low_sig = 4'h5;
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high_sig = 4'h5;
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#1 `CHECK
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low_sig = 4'h6;
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high_sig = 4'h6;
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#1 `CHECK
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low_sig = 4'h7;
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high_sig = 4'h7;
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#1 `CHECK
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low_sig = 4'h8;
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high_sig = 4'h8;
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#1 `CHECK
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low_sig = 4'h9;
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high_sig = 4'h9;
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#1 `CHECK
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low_sig = 4'hA;
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high_sig = 4'hA;
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#1 `CHECK
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low_sig = 4'hB;
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high_sig = 4'hB;
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#1 `CHECK
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low_sig = 4'hC;
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high_sig = 4'hC;
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#1 `CHECK
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low_sig = 4'hD;
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high_sig = 4'hD;
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#1 `CHECK
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low_sig = 4'hE;
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high_sig = 4'hE;
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#1 `CHECK
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low_sig = 4'hF;
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high_sig = 4'hF;
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#1 `CHECK
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#1 $display("End of test");
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end
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//--------------------------------------------------------------
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// Instantiate prep-DAA block
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//--------------------------------------------------------------
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alu_prep_daa alu_prep_daa_inst
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(
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.low(low_sig) , // input [3:0] low_sig
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.high(high_sig) , // input [3:0] high_sig
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.low_gt_9(low_gt_9_sig) , // output low_gt_9_sig
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.high_eq_9(high_eq_9_sig) , // output high_eq_9_sig
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.high_gt_9(high_gt_9_sig) // output high_gt_9_sig
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);
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endmodule
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