50 lines
2.1 KiB
Systemverilog
50 lines
2.1 KiB
Systemverilog
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//============================================================================
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// Implementation of the Sinclair ZX Spectrum ULA
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//
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// This module contains the clocks section.
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//
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// TODO: Video RAM contention would cause a clock gating which would be
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// implemented in this module. RAM contention is not implemented since we are
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// using FPGA RAM cells configured in dual-port mode.
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//
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// Copyright (C) 2014-2016 Goran Devic
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//============================================================================
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module clocks
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(
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input wire clk_ula, // Input ULA clock of 14 MHz
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input wire turbo, // Turbo speed (3.5 MHz x 2 = 7.0 MHz)
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output reg clk_cpu // Output 3.5 MHz CPU clock
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);
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// Generate 3.5 MHz Z80 CPU clock by dividing input clock of 14 MHz by 4
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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reg [0:0] counter;
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// Note: In order to get to 3.5 MHz, the PLL needs to be set to generate 14 MHz
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// and then this divider-by-4 brings the effective clock down to 3.5 MHz
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// 1. always block at positive edge of clk_ula divides by 2
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// 2. counter flop further divides it by 2 unless the turbo mode is set
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always @(posedge clk_ula)
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begin
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if (counter=='0 | turbo)
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clk_cpu <= ~clk_cpu;
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counter <= counter - 1'b1;
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end
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endmodule
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