62 lines
2.6 KiB
Python
62 lines
2.6 KiB
Python
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#!/usr/bin/env python3
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#
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# This script reads and parses selected Verilog and SystemVerilog modules
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# and generates a set of Verilog include files for the control block.
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#
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#-------------------------------------------------------------------------------
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# Copyright (C) 2014 Goran Devic
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of the GNU General Public License as published by the Free
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# Software Foundation; either version 2 of the License, or (at your option)
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# any later version.
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#
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# This program is distributed in the hope that it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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# more details.
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#-------------------------------------------------------------------------------
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import glob
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import os
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with open('../top-level-files.txt') as f:
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files = f.read().splitlines()
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# Create 2 files that should be included by the execution engine:
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# 1. A file listing all control signals
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# 2. A file containing statements initializing control signals to zero
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with open('exec_module.vh', 'w') as file1, open('exec_zero.vh', 'w') as file0:
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file1.write("// Automatically generated by genref.py\n")
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file0.write("// Automatically generated by genref.py\n")
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# Read and parse each file from the list of input files
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for infile in files:
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wires = []
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if not os.path.isfile('../' + infile):
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continue
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with open('../' + infile, "r") as f:
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for line in f:
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info = line.split()
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# input wire register case
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if len(info)>2 and info[0]=="input" and info[1]=="wire" and info[2].startswith("ctl_"):
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wires.append(info[2].strip(';,'))
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# input wire bus case (ex. "[1:0]")
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if len(info)>3 and info[0]=="input" and info[1]=="wire" and info[2].startswith("[") and info[3].startswith("ctl_"):
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wires.append(info[2] + " " + info[3].strip(';,'))
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if len(wires)>0:
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with open('exec_module.vh', 'a') as file1, open('exec_zero.vh', 'a') as file0:
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print ("MODULE:", infile)
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file0.write("\n// Module: " + infile + "\n")
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file1.write("\n// Module: " + infile + "\n")
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for wire in wires:
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print (" ", wire)
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file1.write("output reg " + wire + ",\n")
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if "[" in wire:
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file0.write(wire.split()[1] + " = 0;\n")
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else:
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file0.write(wire + " = 0;\n")
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# Touch a file that includes 'exec_module.vh' and 'exec_zero.vh' to ensure it will recompile correctly
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os.utime("execute.v", None)
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