55 lines
1.4 KiB
Verilog
55 lines
1.4 KiB
Verilog
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// Copyright (C) 1991-2013 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// CREATED "Mon Oct 13 12:26:57 2014"
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module inc_dec_2bit(
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carry_borrow_in,
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d1_in,
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d0_in,
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dec1_in,
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dec0_in,
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carry_borrow_out,
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d1_out,
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d0_out
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);
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input wire carry_borrow_in;
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input wire d1_in;
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input wire d0_in;
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input wire dec1_in;
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input wire dec0_in;
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output wire carry_borrow_out;
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output wire d1_out;
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output wire d0_out;
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wire SYNTHESIZED_WIRE_0;
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assign SYNTHESIZED_WIRE_0 = dec0_in & carry_borrow_in;
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assign carry_borrow_out = dec0_in & dec1_in & carry_borrow_in;
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assign d1_out = d1_in ^ SYNTHESIZED_WIRE_0;
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assign d0_out = carry_borrow_in ^ d0_in;
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endmodule
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