2022-03-30 11:53:01 +03:00
Fitter report for spectrum
2022-03-30 12:47:42 +03:00
Wed Mar 30 12:38:34 2022
2022-03-30 11:53:01 +03:00
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Parallel Compilation
5. I/O Assignment Warnings
6. Ignored Assignments
7. Incremental Compilation Preservation Summary
8. Incremental Compilation Partition Settings
9. Incremental Compilation Placement Preservation
10. Pin-Out File
11. Fitter Resource Usage Summary
12. Fitter Partition Statistics
13. Input Pins
14. Output Pins
15. Dual Purpose and Dedicated Pins
16. I/O Bank Usage
17. All Package Pins
18. Fitter Resource Utilization by Entity
19. Delay Chain Summary
20. Pad To Core Delay Chain Fanout
21. Control Signals
22. Global & Other Fast Signals
23. Non-Global High Fan-Out Signals
2022-03-30 12:47:42 +03:00
24. Fitter RAM Summary
25. |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ALTSYNCRAM
26. Routing Usage Summary
27. LAB Logic Elements
28. LAB-wide Signals
29. LAB Signals Sourced
30. LAB Signals Sourced Out
31. LAB Distinct Inputs
32. I/O Rules Summary
33. I/O Rules Details
34. I/O Rules Matrix
35. Fitter Device Options
36. Operating Settings and Conditions
37. Fitter Messages
38. Fitter Suppressed Messages
2022-03-30 11:53:01 +03:00
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+--------------------------------------------+
2022-03-30 12:47:42 +03:00
; Fitter Status ; Successful - Wed Mar 30 12:38:34 2022 ;
2022-03-30 11:53:01 +03:00
; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ;
; Device ; EP4CE22F17C6 ;
; Timing Models ; Final ;
2022-03-30 12:47:42 +03:00
; Total logic elements ; 33 / 22,320 ( < 1 % ) ;
; Total combinational functions ; 33 / 22,320 ( < 1 % ) ;
; Dedicated logic registers ; 24 / 22,320 ( < 1 % ) ;
; Total registers ; 24 ;
2022-03-30 11:53:01 +03:00
; Total pins ; 9 / 154 ( 6 % ) ;
; Total virtual pins ; 0 ;
2022-03-30 12:47:42 +03:00
; Total memory bits ; 64 / 608,256 ( < 1 % ) ;
2022-03-30 11:53:01 +03:00
; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
+------------------------------------+--------------------------------------------+
+--------------------------------------------------------------------------------+
; Fitter Settings ;
+--------------------------------------------------------------------------------+
Option : Device
Setting : EP4CE22F17C6
Default Value :
Option : Nominal Core Supply Voltage
Setting : 1.2V
Default Value :
Option : Minimum Core Junction Temperature
Setting : 0
Default Value :
Option : Maximum Core Junction Temperature
Setting : 85
Default Value :
Option : Fit Attempts to Skip
Setting : 0
Default Value : 0.0
Option : Device I/O Standard
Setting : 2.5 V
Default Value :
Option : Use smart compilation
Setting : Off
Default Value : Off
Option : Enable parallel Assembler and TimeQuest Timing Analyzer during compilation
Setting : On
Default Value : On
Option : Enable compact report table
Setting : Off
Default Value : Off
Option : Auto Merge PLLs
Setting : On
Default Value : On
Option : Router Timing Optimization Level
Setting : Normal
Default Value : Normal
Option : Perform Clocking Topology Analysis During Routing
Setting : Off
Default Value : Off
Option : Placement Effort Multiplier
Setting : 1.0
Default Value : 1.0
Option : Router Effort Multiplier
Setting : 1.0
Default Value : 1.0
Option : Optimize Hold Timing
Setting : All Paths
Default Value : All Paths
Option : Optimize Multi-Corner Timing
Setting : On
Default Value : On
Option : PowerPlay Power Optimization
Setting : Normal compilation
Default Value : Normal compilation
Option : SSN Optimization
Setting : Off
Default Value : Off
Option : Optimize Timing
Setting : Normal compilation
Default Value : Normal compilation
Option : Optimize Timing for ECOs
Setting : Off
Default Value : Off
Option : Regenerate full fit report during ECO compiles
Setting : Off
Default Value : Off
Option : Optimize IOC Register Placement for Timing
Setting : Normal
Default Value : Normal
Option : Limit to One Fitting Attempt
Setting : Off
Default Value : Off
Option : Final Placement Optimizations
Setting : Automatically
Default Value : Automatically
Option : Fitter Aggressive Routability Optimizations
Setting : Automatically
Default Value : Automatically
Option : Fitter Initial Placement Seed
Setting : 1
Default Value : 1
Option : PCI I/O
Setting : Off
Default Value : Off
Option : Weak Pull-Up Resistor
Setting : Off
Default Value : Off
Option : Enable Bus-Hold Circuitry
Setting : Off
Default Value : Off
Option : Auto Packed Registers
Setting : Auto
Default Value : Auto
Option : Auto Delay Chains
Setting : On
Default Value : On
Option : Auto Delay Chains for High Fanout Input Pins
Setting : Off
Default Value : Off
Option : Allow Single-ended Buffer for Differential-XSTL Input
Setting : Off
Default Value : Off
Option : Treat Bidirectional Pin as Output Pin
Setting : Off
Default Value : Off
Option : Perform Physical Synthesis for Combinational Logic for Fitting
Setting : Off
Default Value : Off
Option : Perform Physical Synthesis for Combinational Logic for Performance
Setting : Off
Default Value : Off
Option : Perform Register Duplication for Performance
Setting : Off
Default Value : Off
Option : Perform Logic to Memory Mapping for Fitting
Setting : Off
Default Value : Off
Option : Perform Register Retiming for Performance
Setting : Off
Default Value : Off
Option : Perform Asynchronous Signal Pipelining
Setting : Off
Default Value : Off
Option : Fitter Effort
Setting : Auto Fit
Default Value : Auto Fit
Option : Physical Synthesis Effort Level
Setting : Normal
Default Value : Normal
Option : Logic Cell Insertion - Logic Duplication
Setting : Auto
Default Value : Auto
Option : Auto Register Duplication
Setting : Auto
Default Value : Auto
Option : Auto Global Clock
Setting : On
Default Value : On
Option : Auto Global Register Control Signals
Setting : On
Default Value : On
Option : Reserve all unused pins
Setting : As input tri-stated with weak pull-up
Default Value : As input tri-stated with weak pull-up
Option : Synchronizer Identification
Setting : Off
Default Value : Off
Option : Enable Beneficial Skew Optimization
Setting : On
Default Value : On
Option : Optimize Design for Metastability
Setting : On
Default Value : On
Option : Force Fitter to Avoid Periphery Placement Warnings
Setting : Off
Default Value : Off
Option : Enable input tri-state on active configuration pins in user mode
Setting : Off
Default Value : Off
+--------------------------------------------------------------------------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 12 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+-----------------------------------+
; I/O Assignment Warnings ;
+----------+------------------------+
; Pin Name ; Reason ;
+----------+------------------------+
; LED[0] ; Missing drive strength ;
; LED[1] ; Missing drive strength ;
; LED[2] ; Missing drive strength ;
; LED[3] ; Missing drive strength ;
; LED[4] ; Missing drive strength ;
; LED[5] ; Missing drive strength ;
; LED[6] ; Missing drive strength ;
; LED[7] ; Missing drive strength ;
+----------+------------------------+
+--------------------------------------------------------------------------------+
; Ignored Assignments ;
+--------------------------------------------------------------------------------+
Name : Location
Ignored Entity :
Ignored From :
Ignored To : ADC_CS_N
Ignored Value : PIN_A10
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : ADC_SADDR
Ignored Value : PIN_B10
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : ADC_SCLK
Ignored Value : PIN_B14
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : ADC_SDAT
Ignored Value : PIN_A9
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_ADDR[0]
Ignored Value : PIN_P2
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_ADDR[10]
Ignored Value : PIN_N2
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_ADDR[11]
Ignored Value : PIN_N1
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_ADDR[12]
Ignored Value : PIN_L4
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_ADDR[1]
Ignored Value : PIN_N5
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_ADDR[2]
Ignored Value : PIN_N6
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_ADDR[3]
Ignored Value : PIN_M8
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_ADDR[4]
Ignored Value : PIN_P8
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_ADDR[5]
Ignored Value : PIN_T7
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_ADDR[6]
Ignored Value : PIN_N8
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_ADDR[7]
Ignored Value : PIN_T6
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_ADDR[8]
Ignored Value : PIN_R1
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_ADDR[9]
Ignored Value : PIN_P1
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_BA[0]
Ignored Value : PIN_M7
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_BA[1]
Ignored Value : PIN_M6
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_CAS_N
Ignored Value : PIN_L1
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_CKE
Ignored Value : PIN_L7
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_CLK
Ignored Value : PIN_R4
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_CS_N
Ignored Value : PIN_P6
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_DQM[0]
Ignored Value : PIN_R6
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_DQM[1]
Ignored Value : PIN_T5
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_DQ[0]
Ignored Value : PIN_G2
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_DQ[10]
Ignored Value : PIN_T3
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_DQ[11]
Ignored Value : PIN_R3
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_DQ[12]
Ignored Value : PIN_R5
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_DQ[13]
Ignored Value : PIN_P3
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_DQ[14]
Ignored Value : PIN_N3
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_DQ[15]
Ignored Value : PIN_K1
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_DQ[1]
Ignored Value : PIN_G1
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_DQ[2]
Ignored Value : PIN_L8
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_DQ[3]
Ignored Value : PIN_K5
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_DQ[4]
Ignored Value : PIN_K2
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_DQ[5]
Ignored Value : PIN_J2
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_DQ[6]
Ignored Value : PIN_J1
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_DQ[7]
Ignored Value : PIN_R7
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_DQ[8]
Ignored Value : PIN_T4
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_DQ[9]
Ignored Value : PIN_T2
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_RAS_N
Ignored Value : PIN_L2
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : DRAM_WE_N
Ignored Value : PIN_C2
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : EPCS_ASDO
Ignored Value : PIN_C1
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : EPCS_DATA0
Ignored Value : PIN_H2
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : EPCS_DCLK
Ignored Value : PIN_H1
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : EPCS_NCSO
Ignored Value : PIN_D2
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[0]
Ignored Value : PIN_D3
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[10]
Ignored Value : PIN_B6
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[11]
Ignored Value : PIN_A6
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[12]
Ignored Value : PIN_B7
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[13]
Ignored Value : PIN_D6
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[14]
Ignored Value : PIN_A7
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[15]
Ignored Value : PIN_C6
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[16]
Ignored Value : PIN_C8
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[17]
Ignored Value : PIN_E6
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[18]
Ignored Value : PIN_E7
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[19]
Ignored Value : PIN_D8
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[1]
Ignored Value : PIN_C3
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[20]
Ignored Value : PIN_E8
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[21]
Ignored Value : PIN_F8
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[22]
Ignored Value : PIN_F9
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[23]
Ignored Value : PIN_E9
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[24]
Ignored Value : PIN_C9
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[25]
Ignored Value : PIN_D9
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[26]
Ignored Value : PIN_E11
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[27]
Ignored Value : PIN_E10
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[28]
Ignored Value : PIN_C11
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[29]
Ignored Value : PIN_B11
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[2]
Ignored Value : PIN_A2
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[30]
Ignored Value : PIN_A12
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[31]
Ignored Value : PIN_D11
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[32]
Ignored Value : PIN_D12
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[33]
Ignored Value : PIN_B12
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[3]
Ignored Value : PIN_A3
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[4]
Ignored Value : PIN_B3
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[5]
Ignored Value : PIN_B4
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[6]
Ignored Value : PIN_A4
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[7]
Ignored Value : PIN_B5
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[8]
Ignored Value : PIN_A5
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0[9]
Ignored Value : PIN_D5
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0_IN[0]
Ignored Value : PIN_A8
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_0_IN[1]
Ignored Value : PIN_B8
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[0]
Ignored Value : PIN_F13
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[10]
Ignored Value : PIN_P11
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[11]
Ignored Value : PIN_R10
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[12]
Ignored Value : PIN_N12
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[13]
Ignored Value : PIN_P9
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[14]
Ignored Value : PIN_N9
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[15]
Ignored Value : PIN_N11
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[16]
Ignored Value : PIN_L16
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[17]
Ignored Value : PIN_K16
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[18]
Ignored Value : PIN_R16
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[19]
Ignored Value : PIN_L15
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[1]
Ignored Value : PIN_T15
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[20]
Ignored Value : PIN_P15
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[21]
Ignored Value : PIN_P16
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[22]
Ignored Value : PIN_R14
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[23]
Ignored Value : PIN_N16
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[24]
Ignored Value : PIN_N15
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[25]
Ignored Value : PIN_P14
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[26]
Ignored Value : PIN_L14
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[27]
Ignored Value : PIN_N14
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[28]
Ignored Value : PIN_M10
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[29]
Ignored Value : PIN_L13
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[2]
Ignored Value : PIN_T14
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[30]
Ignored Value : PIN_J16
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[31]
Ignored Value : PIN_K15
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[32]
Ignored Value : PIN_J13
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[33]
Ignored Value : PIN_J14
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[3]
Ignored Value : PIN_T13
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[4]
Ignored Value : PIN_R13
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[5]
Ignored Value : PIN_T12
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[6]
Ignored Value : PIN_R12
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[7]
Ignored Value : PIN_T11
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[8]
Ignored Value : PIN_T10
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1[9]
Ignored Value : PIN_R11
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1_IN[0]
Ignored Value : PIN_T9
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_1_IN[1]
Ignored Value : PIN_R9
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_2[0]
Ignored Value : PIN_A14
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_2[10]
Ignored Value : PIN_F14
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_2[11]
Ignored Value : PIN_G16
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_2[12]
Ignored Value : PIN_G15
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_2[1]
Ignored Value : PIN_B16
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_2[2]
Ignored Value : PIN_C14
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_2[3]
Ignored Value : PIN_C16
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_2[4]
Ignored Value : PIN_C15
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_2[5]
Ignored Value : PIN_D16
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_2[6]
Ignored Value : PIN_D15
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_2[7]
Ignored Value : PIN_D14
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_2[8]
Ignored Value : PIN_F15
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_2[9]
Ignored Value : PIN_F16
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_2_IN[0]
Ignored Value : PIN_E15
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_2_IN[1]
Ignored Value : PIN_E16
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : GPIO_2_IN[2]
Ignored Value : PIN_M16
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : G_SENSOR_CS_N
Ignored Value : PIN_G5
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : G_SENSOR_INT
Ignored Value : PIN_M2
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : I2C_SCLK
Ignored Value : PIN_F2
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : I2C_SDAT
Ignored Value : PIN_F1
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : KEY[0]
Ignored Value : PIN_J15
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : KEY[1]
Ignored Value : PIN_E1
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : SW[0]
Ignored Value : PIN_M1
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : SW[1]
Ignored Value : PIN_T8
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : SW[2]
Ignored Value : PIN_B9
Ignored Source : QSF Assignment
Name : Location
Ignored Entity :
Ignored From :
Ignored To : SW[3]
Ignored Value : PIN_M15
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : ADC_CS_N
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : ADC_SADDR
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : ADC_SCLK
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : ADC_SDAT
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_ADDR[0]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_ADDR[10]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_ADDR[11]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_ADDR[12]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_ADDR[1]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_ADDR[2]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_ADDR[3]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_ADDR[4]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_ADDR[5]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_ADDR[6]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_ADDR[7]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_ADDR[8]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_ADDR[9]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_BA[0]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_BA[1]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_CAS_N
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_CKE
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_CLK
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_CS_N
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_DQM[0]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_DQM[1]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_DQ[0]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_DQ[10]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_DQ[11]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_DQ[12]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_DQ[13]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_DQ[14]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_DQ[15]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_DQ[1]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_DQ[2]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_DQ[3]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_DQ[4]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_DQ[5]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_DQ[6]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_DQ[7]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_DQ[8]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_DQ[9]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_RAS_N
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : DRAM_WE_N
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : EPCS_ASDO
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : EPCS_DATA0
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : EPCS_DCLK
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : EPCS_NCSO
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[0]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[10]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[11]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[12]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[13]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[14]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[15]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[16]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[17]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[18]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[19]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[1]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[20]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[21]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[22]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[23]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[24]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[25]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[26]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[27]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[28]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[29]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[2]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[30]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[31]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[32]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[33]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[3]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[4]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[5]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[6]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[7]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[8]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0[9]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0_IN[0]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_0_IN[1]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[0]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[10]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[11]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[12]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[13]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[14]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[15]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[16]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[17]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[18]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[19]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[1]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[20]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[21]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[22]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[23]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[24]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[25]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[26]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[27]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[28]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[29]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[2]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[30]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[31]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[32]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[33]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[3]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[4]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[5]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[6]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[7]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[8]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1[9]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1_IN[0]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_1_IN[1]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_2[0]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_2[10]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_2[11]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_2[12]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_2[1]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_2[2]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_2[3]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_2[4]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_2[5]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_2[6]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_2[7]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_2[8]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_2[9]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_2_IN[0]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_2_IN[1]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : GPIO_2_IN[2]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : G_SENSOR_CS_N
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : G_SENSOR_INT
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : I2C_SCLK
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : I2C_SDAT
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : KEY[0]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : KEY[1]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : SW[0]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : SW[1]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : SW[2]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
Name : I/O Standard
Ignored Entity : spectrum
Ignored From :
Ignored To : SW[3]
Ignored Value : 3.3-V LVTTL
Ignored Source : QSF Assignment
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Incremental Compilation Preservation Summary ;
+--------------------------------------------------------------------------------+
Type : Placement (by node)
Total [A + B] :
From Design Partitions [A] :
From Rapid Recompile [B] :
Type : -- Requested
2022-03-30 12:47:42 +03:00
Total [A + B] : 0.00 % ( 0 / 95 )
From Design Partitions [A] : 0.00 % ( 0 / 95 )
From Rapid Recompile [B] : 0.00 % ( 0 / 95 )
2022-03-30 11:53:01 +03:00
Type : -- Achieved
2022-03-30 12:47:42 +03:00
Total [A + B] : 0.00 % ( 0 / 95 )
From Design Partitions [A] : 0.00 % ( 0 / 95 )
From Rapid Recompile [B] : 0.00 % ( 0 / 95 )
2022-03-30 11:53:01 +03:00
Type :
Total [A + B] :
From Design Partitions [A] :
From Rapid Recompile [B] :
Type : Routing (by net)
Total [A + B] :
From Design Partitions [A] :
From Rapid Recompile [B] :
Type : -- Requested
Total [A + B] : 0.00 % ( 0 / 0 )
From Design Partitions [A] : 0.00 % ( 0 / 0 )
From Rapid Recompile [B] : 0.00 % ( 0 / 0 )
Type : -- Achieved
Total [A + B] : 0.00 % ( 0 / 0 )
From Design Partitions [A] : 0.00 % ( 0 / 0 )
From Rapid Recompile [B] : 0.00 % ( 0 / 0 )
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Incremental Compilation Partition Settings ;
+--------------------------------------------------------------------------------+
Partition Name : Top
Partition Type : User-created
Netlist Type Used : Source File
Preservation Level Used : N/A
Netlist Type Requested : Source File
Preservation Level Requested : N/A
Contents :
Partition Name : hard_block:auto_generated_inst
Partition Type : Auto-generated
Netlist Type Used : Source File
Preservation Level Used : N/A
Netlist Type Requested : Source File
Preservation Level Requested : N/A
Contents : hard_block:auto_generated_inst
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Incremental Compilation Placement Preservation ;
+--------------------------------------------------------------------------------+
Partition Name : Top
2022-03-30 12:47:42 +03:00
Preservation Achieved : 0.00 % ( 0 / 85 )
2022-03-30 11:53:01 +03:00
Preservation Level Used : N/A
Netlist Type Used : Source File
Preservation Method : N/A
Notes :
Partition Name : hard_block:auto_generated_inst
Preservation Achieved : 0.00 % ( 0 / 10 )
Preservation Level Used : N/A
Netlist Type Used : Source File
Preservation Method : N/A
Notes :
+--------------------------------------------------------------------------------+
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in /home/benny/work/fpga/projects/output_files/spectrum.pin.
2022-03-30 12:47:42 +03:00
+-----------------------------------------------------------------------+
; Fitter Resource Usage Summary ;
+---------------------------------------------+-------------------------+
; Resource ; Usage ;
+---------------------------------------------+-------------------------+
; Total logic elements ; 33 / 22,320 ( < 1 % ) ;
; -- Combinational with no register ; 9 ;
; -- Register only ; 0 ;
; -- Combinational with a register ; 24 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 10 ;
; -- 3 input functions ; 1 ;
; -- <=2 input functions ; 22 ;
; -- Register only ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 13 ;
; -- arithmetic mode ; 20 ;
; ; ;
; Total registers* ; 24 / 23,018 ( < 1 % ) ;
; -- Dedicated logic registers ; 24 / 22,320 ( < 1 % ) ;
; -- I/O registers ; 0 / 698 ( 0 % ) ;
; ; ;
; Total LABs: partially or completely used ; 3 / 1,395 ( < 1 % ) ;
; Virtual pins ; 0 ;
; I/O pins ; 9 / 154 ( 6 % ) ;
; -- Clock pins ; 1 / 7 ( 14 % ) ;
; -- Dedicated input pins ; 0 / 9 ( 0 % ) ;
; ; ;
; Global signals ; 1 ;
; M9Ks ; 1 / 66 ( 2 % ) ;
; Total block memory bits ; 64 / 608,256 ( < 1 % ) ;
; Total block memory implementation bits ; 9,216 / 608,256 ( 2 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ;
; PLLs ; 0 / 4 ( 0 % ) ;
; Global clocks ; 1 / 20 ( 5 % ) ;
; JTAGs ; 0 / 1 ( 0 % ) ;
; CRC blocks ; 0 / 1 ( 0 % ) ;
; ASMI blocks ; 0 / 1 ( 0 % ) ;
; Impedance control blocks ; 0 / 4 ( 0 % ) ;
; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ;
; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ;
; Maximum fan-out ; 25 ;
; Highest non-global fan-out ; 4 ;
; Total fan-out ; 161 ;
; Average fan-out ; 1.85 ;
+---------------------------------------------+-------------------------+
2022-03-30 11:53:01 +03:00
* Register count does not include registers inside RAM blocks or DSP blocks.
+--------------------------------------------------------------------------------+
; Fitter Partition Statistics ;
+--------------------------------------------------------------------------------+
Statistic : Difficulty Clustering Region
Top : Low
hard_block:auto_generated_inst : Low
Statistic :
Top :
hard_block:auto_generated_inst :
Statistic : Total logic elements
2022-03-30 12:47:42 +03:00
Top : 33 / 22320 ( < 1 % )
2022-03-30 11:53:01 +03:00
hard_block:auto_generated_inst : 0 / 22320 ( 0 % )
Statistic : -- Combinational with no register
2022-03-30 12:47:42 +03:00
Top : 9
2022-03-30 11:53:01 +03:00
hard_block:auto_generated_inst : 0
Statistic : -- Register only
2022-03-30 12:47:42 +03:00
Top : 0
2022-03-30 11:53:01 +03:00
hard_block:auto_generated_inst : 0
Statistic : -- Combinational with a register
2022-03-30 12:47:42 +03:00
Top : 24
2022-03-30 11:53:01 +03:00
hard_block:auto_generated_inst : 0
Statistic :
Top :
hard_block:auto_generated_inst :
Statistic : Logic element usage by number of LUT inputs
Top :
hard_block:auto_generated_inst :
Statistic : -- 4 input functions
2022-03-30 12:47:42 +03:00
Top : 10
2022-03-30 11:53:01 +03:00
hard_block:auto_generated_inst : 0
Statistic : -- 3 input functions
Top : 1
hard_block:auto_generated_inst : 0
Statistic : -- <=2 input functions
2022-03-30 12:47:42 +03:00
Top : 22
2022-03-30 11:53:01 +03:00
hard_block:auto_generated_inst : 0
Statistic : -- Register only
2022-03-30 12:47:42 +03:00
Top : 0
2022-03-30 11:53:01 +03:00
hard_block:auto_generated_inst : 0
Statistic :
Top :
hard_block:auto_generated_inst :
Statistic : Logic elements by mode
Top :
hard_block:auto_generated_inst :
Statistic : -- normal mode
2022-03-30 12:47:42 +03:00
Top : 13
2022-03-30 11:53:01 +03:00
hard_block:auto_generated_inst : 0
Statistic : -- arithmetic mode
2022-03-30 12:47:42 +03:00
Top : 20
2022-03-30 11:53:01 +03:00
hard_block:auto_generated_inst : 0
Statistic :
Top :
hard_block:auto_generated_inst :
Statistic : Total registers
2022-03-30 12:47:42 +03:00
Top : 24
2022-03-30 11:53:01 +03:00
hard_block:auto_generated_inst : 0
Statistic : -- Dedicated logic registers
2022-03-30 12:47:42 +03:00
Top : 24 / 22320 ( < 1 % )
2022-03-30 11:53:01 +03:00
hard_block:auto_generated_inst : 0 / 22320 ( 0 % )
Statistic : -- I/O registers
Top : 0
hard_block:auto_generated_inst : 0
Statistic :
Top :
hard_block:auto_generated_inst :
Statistic : Total LABs: partially or completely used
2022-03-30 12:47:42 +03:00
Top : 3 / 1395 ( < 1 % )
2022-03-30 11:53:01 +03:00
hard_block:auto_generated_inst : 0 / 1395 ( 0 % )
Statistic :
Top :
hard_block:auto_generated_inst :
Statistic : Virtual pins
Top : 0
hard_block:auto_generated_inst : 0
Statistic : I/O pins
Top : 9
hard_block:auto_generated_inst : 0
Statistic : Embedded Multiplier 9-bit elements
Top : 0 / 132 ( 0 % )
hard_block:auto_generated_inst : 0 / 132 ( 0 % )
Statistic : Total memory bits
2022-03-30 12:47:42 +03:00
Top : 64
2022-03-30 11:53:01 +03:00
hard_block:auto_generated_inst : 0
Statistic : Total RAM block bits
2022-03-30 12:47:42 +03:00
Top : 9216
2022-03-30 11:53:01 +03:00
hard_block:auto_generated_inst : 0
2022-03-30 12:47:42 +03:00
Statistic : M9K
Top : 1 / 66 ( 1 % )
hard_block:auto_generated_inst : 0 / 66 ( 0 % )
2022-03-30 11:53:01 +03:00
Statistic : Clock control block
Top : 1 / 24 ( 4 % )
hard_block:auto_generated_inst : 0 / 24 ( 0 % )
Statistic :
Top :
hard_block:auto_generated_inst :
Statistic : Connections
Top :
hard_block:auto_generated_inst :
Statistic : -- Input Connections
Top : 0
hard_block:auto_generated_inst : 0
Statistic : -- Registered Input Connections
Top : 0
hard_block:auto_generated_inst : 0
Statistic : -- Output Connections
Top : 0
hard_block:auto_generated_inst : 0
Statistic : -- Registered Output Connections
Top : 0
hard_block:auto_generated_inst : 0
Statistic :
Top :
hard_block:auto_generated_inst :
Statistic : Internal Connections
Top :
hard_block:auto_generated_inst :
Statistic : -- Total Connections
2022-03-30 12:47:42 +03:00
Top : 156
2022-03-30 11:53:01 +03:00
hard_block:auto_generated_inst : 5
Statistic : -- Registered Connections
2022-03-30 12:47:42 +03:00
Top : 38
2022-03-30 11:53:01 +03:00
hard_block:auto_generated_inst : 0
Statistic :
Top :
hard_block:auto_generated_inst :
Statistic : External Connections
Top :
hard_block:auto_generated_inst :
Statistic : -- Top
Top : 0
hard_block:auto_generated_inst : 0
Statistic : -- hard_block:auto_generated_inst
Top : 0
hard_block:auto_generated_inst : 0
Statistic :
Top :
hard_block:auto_generated_inst :
Statistic : Partition Interface
Top :
hard_block:auto_generated_inst :
Statistic : -- Input Ports
Top : 1
hard_block:auto_generated_inst : 0
Statistic : -- Output Ports
Top : 8
hard_block:auto_generated_inst : 0
Statistic : -- Bidir Ports
Top : 0
hard_block:auto_generated_inst : 0
Statistic :
Top :
hard_block:auto_generated_inst :
Statistic : Registered Ports
Top :
hard_block:auto_generated_inst :
Statistic : -- Registered Input Ports
Top : 0
hard_block:auto_generated_inst : 0
Statistic : -- Registered Output Ports
Top : 0
hard_block:auto_generated_inst : 0
Statistic :
Top :
hard_block:auto_generated_inst :
Statistic : Port Connectivity
Top :
hard_block:auto_generated_inst :
Statistic : -- Input Ports driven by GND
Top : 0
hard_block:auto_generated_inst : 0
Statistic : -- Output Ports driven by GND
Top : 0
hard_block:auto_generated_inst : 0
Statistic : -- Input Ports driven by VCC
Top : 0
hard_block:auto_generated_inst : 0
Statistic : -- Output Ports driven by VCC
Top : 0
hard_block:auto_generated_inst : 0
Statistic : -- Input Ports with no Source
Top : 0
hard_block:auto_generated_inst : 0
Statistic : -- Output Ports with no Source
Top : 0
hard_block:auto_generated_inst : 0
Statistic : -- Input Ports with no Fanout
Top : 0
hard_block:auto_generated_inst : 0
Statistic : -- Output Ports with no Fanout
Top : 0
hard_block:auto_generated_inst : 0
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Input Pins ;
+--------------------------------------------------------------------------------+
Name : CLOCK_50
Pin # : R8
I/O Bank : 3
X coordinate : 27
Y coordinate : 0
Z coordinate : 21
2022-03-30 12:47:42 +03:00
Combinational Fan-Out : 25
2022-03-30 11:53:01 +03:00
Registered Fan-Out : 0
Global : yes
Input Register : no
Power Up High : no
PCI I/O Enabled : yes
Bus Hold : no
Weak Pull Up : Off
I/O Standard : 3.3-V LVTTL
Termination Control Block : --
Location assigned by : User
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Output Pins ;
+--------------------------------------------------------------------------------+
Name : LED[0]
Pin # : A15
I/O Bank : 7
X coordinate : 38
Y coordinate : 34
Z coordinate : 14
Output Register : no
Output Enable Register : no
Power Up High : no
Slew Rate : 2
PCI I/O Enabled : no
Open Drain : no
TRI Primitive : no
Bus Hold : no
Weak Pull Up : Off
I/O Standard : 3.3-V LVTTL
Current Strength : 8mA
Termination : Off
Termination Control Block : --
Output Buffer Pre-emphasis : no
Voltage Output Differential : no
Location assigned by : User
Output Enable Source : -
Output Enable Group : -
Name : LED[1]
Pin # : A13
I/O Bank : 7
X coordinate : 49
Y coordinate : 34
Z coordinate : 0
Output Register : no
Output Enable Register : no
Power Up High : no
Slew Rate : 2
PCI I/O Enabled : no
Open Drain : no
TRI Primitive : no
Bus Hold : no
Weak Pull Up : Off
I/O Standard : 3.3-V LVTTL
Current Strength : 8mA
Termination : Off
Termination Control Block : --
Output Buffer Pre-emphasis : no
Voltage Output Differential : no
Location assigned by : User
Output Enable Source : -
Output Enable Group : -
Name : LED[2]
Pin # : B13
I/O Bank : 7
X coordinate : 49
Y coordinate : 34
Z coordinate : 7
Output Register : no
Output Enable Register : no
Power Up High : no
Slew Rate : 2
PCI I/O Enabled : no
Open Drain : no
TRI Primitive : no
Bus Hold : no
Weak Pull Up : Off
I/O Standard : 3.3-V LVTTL
Current Strength : 8mA
Termination : Off
Termination Control Block : --
Output Buffer Pre-emphasis : no
Voltage Output Differential : no
Location assigned by : User
Output Enable Source : -
Output Enable Group : -
Name : LED[3]
Pin # : A11
I/O Bank : 7
X coordinate : 40
Y coordinate : 34
Z coordinate : 0
Output Register : no
Output Enable Register : no
Power Up High : no
Slew Rate : 2
PCI I/O Enabled : no
Open Drain : no
TRI Primitive : no
Bus Hold : no
Weak Pull Up : Off
I/O Standard : 3.3-V LVTTL
Current Strength : 8mA
Termination : Off
Termination Control Block : --
Output Buffer Pre-emphasis : no
Voltage Output Differential : no
Location assigned by : User
Output Enable Source : -
Output Enable Group : -
Name : LED[4]
Pin # : D1
I/O Bank : 1
X coordinate : 0
Y coordinate : 25
Z coordinate : 7
Output Register : no
Output Enable Register : no
Power Up High : no
Slew Rate : 2
PCI I/O Enabled : no
Open Drain : no
TRI Primitive : no
Bus Hold : no
Weak Pull Up : Off
I/O Standard : 3.3-V LVTTL
Current Strength : 8mA
Termination : Off
Termination Control Block : --
Output Buffer Pre-emphasis : no
Voltage Output Differential : no
Location assigned by : User
Output Enable Source : -
Output Enable Group : -
Name : LED[5]
Pin # : F3
I/O Bank : 1
X coordinate : 0
Y coordinate : 26
Z coordinate : 14
Output Register : no
Output Enable Register : no
Power Up High : no
Slew Rate : 2
PCI I/O Enabled : no
Open Drain : no
TRI Primitive : no
Bus Hold : no
Weak Pull Up : Off
I/O Standard : 3.3-V LVTTL
Current Strength : 8mA
Termination : Off
Termination Control Block : --
Output Buffer Pre-emphasis : no
Voltage Output Differential : no
Location assigned by : User
Output Enable Source : -
Output Enable Group : -
Name : LED[6]
Pin # : B1
I/O Bank : 1
X coordinate : 0
Y coordinate : 28
Z coordinate : 7
Output Register : no
Output Enable Register : no
Power Up High : no
Slew Rate : 2
PCI I/O Enabled : no
Open Drain : no
TRI Primitive : no
Bus Hold : no
Weak Pull Up : Off
I/O Standard : 3.3-V LVTTL
Current Strength : 8mA
Termination : Off
Termination Control Block : --
Output Buffer Pre-emphasis : no
Voltage Output Differential : no
Location assigned by : User
Output Enable Source : -
Output Enable Group : -
Name : LED[7]
Pin # : L3
I/O Bank : 2
X coordinate : 0
Y coordinate : 10
Z coordinate : 21
Output Register : no
Output Enable Register : no
Power Up High : no
Slew Rate : 2
PCI I/O Enabled : no
Open Drain : no
TRI Primitive : no
Bus Hold : no
Weak Pull Up : Off
I/O Standard : 3.3-V LVTTL
Current Strength : 8mA
Termination : Off
Termination Control Block : --
Output Buffer Pre-emphasis : no
Voltage Output Differential : no
Location assigned by : User
Output Enable Source : -
Output Enable Group : -
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Dual Purpose and Dedicated Pins ;
+--------------------------------------------------------------------------------+
Location : C1
Pin Name : DIFFIO_L3n, DATA1, ASDO
Reserved As : As input tri-stated
User Signal Name : ~ALTERA_ASDO_DATA1~
Pin Type : Dual Purpose Pin
Location : D2
Pin Name : DIFFIO_L4p, FLASH_nCE, nCSO
Reserved As : As input tri-stated
User Signal Name : ~ALTERA_FLASH_nCE_nCSO~
Pin Type : Dual Purpose Pin
Location : F4
Pin Name : nSTATUS
Reserved As : -
User Signal Name : -
Pin Type : Dedicated Programming Pin
Location : H1
Pin Name : DCLK
Reserved As : As output driving ground
User Signal Name : ~ALTERA_DCLK~
Pin Type : Dual Purpose Pin
Location : H2
Pin Name : DATA0
Reserved As : As input tri-stated
User Signal Name : ~ALTERA_DATA0~
Pin Type : Dual Purpose Pin
Location : H5
Pin Name : nCONFIG
Reserved As : -
User Signal Name : -
Pin Type : Dedicated Programming Pin
Location : J3
Pin Name : nCE
Reserved As : -
User Signal Name : -
Pin Type : Dedicated Programming Pin
Location : H14
Pin Name : CONF_DONE
Reserved As : -
User Signal Name : -
Pin Type : Dedicated Programming Pin
Location : H13
Pin Name : MSEL0
Reserved As : -
User Signal Name : -
Pin Type : Dedicated Programming Pin
Location : H12
Pin Name : MSEL1
Reserved As : -
User Signal Name : -
Pin Type : Dedicated Programming Pin
Location : G12
Pin Name : MSEL2
Reserved As : -
User Signal Name : -
Pin Type : Dedicated Programming Pin
Location : G12
Pin Name : MSEL3
Reserved As : -
User Signal Name : -
Pin Type : Dedicated Programming Pin
Location : F16
Pin Name : DIFFIO_R4n, nCEO
Reserved As : Use as programming pin
User Signal Name : ~ALTERA_nCEO~
Pin Type : Dual Purpose Pin
Location : A15
Pin Name : DIFFIO_T19n, PADD1
Reserved As : Use as regular IO
User Signal Name : LED[0]
Pin Type : Dual Purpose Pin
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; I/O Bank Usage ;
+--------------------------------------------------------------------------------+
I/O Bank : 1
Usage : 7 / 14 ( 50 % )
VCCIO Voltage : 3.3V
VREF Voltage : --
I/O Bank : 2
Usage : 1 / 16 ( 6 % )
VCCIO Voltage : 3.3V
VREF Voltage : --
I/O Bank : 3
Usage : 1 / 25 ( 4 % )
VCCIO Voltage : 3.3V
VREF Voltage : --
I/O Bank : 4
Usage : 0 / 20 ( 0 % )
VCCIO Voltage : 2.5V
VREF Voltage : --
I/O Bank : 5
Usage : 0 / 18 ( 0 % )
VCCIO Voltage : 2.5V
VREF Voltage : --
I/O Bank : 6
Usage : 1 / 13 ( 8 % )
VCCIO Voltage : 2.5V
VREF Voltage : --
I/O Bank : 7
Usage : 4 / 24 ( 17 % )
VCCIO Voltage : 3.3V
VREF Voltage : --
I/O Bank : 8
Usage : 0 / 24 ( 0 % )
VCCIO Voltage : 2.5V
VREF Voltage : --
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; All Package Pins ;
+--------------------------------------------------------------------------------+
Location : A1
Pad Number :
I/O Bank : 8
Pin Name/Usage : VCCIO8
Dir. : power
I/O Standard :
Voltage : 2.5V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : A2
Pad Number : 238
I/O Bank : 8
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : A3
Pad Number : 239
I/O Bank : 8
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : A4
Pad Number : 236
I/O Bank : 8
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : A5
Pad Number : 232
I/O Bank : 8
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : A6
Pad Number : 225
I/O Bank : 8
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : A7
Pad Number : 220
I/O Bank : 8
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : A8
Pad Number : 211
I/O Bank : 8
Pin Name/Usage : GND+
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : A9
Pad Number : 209
I/O Bank : 7
Pin Name/Usage : GND+
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : A10
Pad Number : 198
I/O Bank : 7
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : A11
Pad Number : 188
I/O Bank : 7
Pin Name/Usage : LED[3]
Dir. : output
I/O Standard : 3.3-V LVTTL
Voltage :
I/O Type : Column I/O
User Assignment : Y
Bus Hold : no
Weak Pull Up : Off
Location : A12
Pad Number : 186
I/O Bank : 7
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : A13
Pad Number : 179
I/O Bank : 7
Pin Name/Usage : LED[1]
Dir. : output
I/O Standard : 3.3-V LVTTL
Voltage :
I/O Type : Column I/O
User Assignment : Y
Bus Hold : no
Weak Pull Up : Off
Location : A14
Pad Number : 181
I/O Bank : 7
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : A15
Pad Number : 191
I/O Bank : 7
Pin Name/Usage : LED[0]
Dir. : output
I/O Standard : 3.3-V LVTTL
Voltage :
I/O Type : Column I/O
User Assignment : Y
Bus Hold : no
Weak Pull Up : Off
Location : A16
Pad Number :
I/O Bank : 7
Pin Name/Usage : VCCIO7
Dir. : power
I/O Standard :
Voltage : 3.3V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : B1
Pad Number : 5
I/O Bank : 1
Pin Name/Usage : LED[6]
Dir. : output
I/O Standard : 3.3-V LVTTL
Voltage :
I/O Type : Row I/O
User Assignment : Y
Bus Hold : no
Weak Pull Up : Off
Location : B2
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : B3
Pad Number : 242
I/O Bank : 8
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : B4
Pad Number : 237
I/O Bank : 8
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : B5
Pad Number : 233
I/O Bank : 8
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : B6
Pad Number : 226
I/O Bank : 8
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : B7
Pad Number : 221
I/O Bank : 8
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : B8
Pad Number : 212
I/O Bank : 8
Pin Name/Usage : GND+
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : B9
Pad Number : 210
I/O Bank : 7
Pin Name/Usage : GND+
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : B10
Pad Number : 199
I/O Bank : 7
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : B11
Pad Number : 189
I/O Bank : 7
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : B12
Pad Number : 187
I/O Bank : 7
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : B13
Pad Number : 180
I/O Bank : 7
Pin Name/Usage : LED[2]
Dir. : output
I/O Standard : 3.3-V LVTTL
Voltage :
I/O Type : Column I/O
User Assignment : Y
Bus Hold : no
Weak Pull Up : Off
Location : B14
Pad Number : 182
I/O Bank : 7
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : B15
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : B16
Pad Number : 164
I/O Bank : 6
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : C1
Pad Number : 7
I/O Bank : 1
Pin Name/Usage : ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. : input
I/O Standard : 3.3-V LVTTL
Voltage :
I/O Type : Row I/O
User Assignment : N
Bus Hold : no
Weak Pull Up : On
Location : C2
Pad Number : 6
I/O Bank : 1
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : C3
Pad Number : 245
I/O Bank : 8
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : C4
Pad Number :
I/O Bank : 8
Pin Name/Usage : VCCIO8
Dir. : power
I/O Standard :
Voltage : 2.5V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : C5
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : C6
Pad Number : 224
I/O Bank : 8
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : C7
Pad Number :
I/O Bank : 8
Pin Name/Usage : VCCIO8
Dir. : power
I/O Standard :
Voltage : 2.5V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : C8
Pad Number : 215
I/O Bank : 8
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : C9
Pad Number : 200
I/O Bank : 7
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : C10
Pad Number :
I/O Bank : 7
Pin Name/Usage : VCCIO7
Dir. : power
I/O Standard :
Voltage : 3.3V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : C11
Pad Number : 190
I/O Bank : 7
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : C12
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : C13
Pad Number :
I/O Bank : 7
Pin Name/Usage : VCCIO7
Dir. : power
I/O Standard :
Voltage : 3.3V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : C14
Pad Number : 175
I/O Bank : 7
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : C15
Pad Number : 174
I/O Bank : 6
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : C16
Pad Number : 173
I/O Bank : 6
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : D1
Pad Number : 10
I/O Bank : 1
Pin Name/Usage : LED[4]
Dir. : output
I/O Standard : 3.3-V LVTTL
Voltage :
I/O Type : Row I/O
User Assignment : Y
Bus Hold : no
Weak Pull Up : Off
Location : D2
Pad Number : 9
I/O Bank : 1
Pin Name/Usage : ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. : input
I/O Standard : 3.3-V LVTTL
Voltage :
I/O Type : Row I/O
User Assignment : N
Bus Hold : no
Weak Pull Up : On
Location : D3
Pad Number : 246
I/O Bank : 8
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : D4
Pad Number :
I/O Bank :
Pin Name/Usage : VCCD_PLL3
Dir. : power
I/O Standard :
Voltage : 1.2V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : D5
Pad Number : 241
I/O Bank : 8
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : D6
Pad Number : 234
I/O Bank : 8
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : D7
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : D8
Pad Number : 216
I/O Bank : 8
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : D9
Pad Number : 201
I/O Bank : 7
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : D10
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : D11
Pad Number : 177
I/O Bank : 7
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : D12
Pad Number : 178
I/O Bank : 7
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : D13
Pad Number :
I/O Bank :
Pin Name/Usage : VCCD_PLL2
Dir. : power
I/O Standard :
Voltage : 1.2V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : D14
Pad Number : 176
I/O Bank : 7
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : D15
Pad Number : 170
I/O Bank : 6
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : D16
Pad Number : 169
I/O Bank : 6
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : E1
Pad Number : 26
I/O Bank : 1
Pin Name/Usage : GND+
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : E2
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : E3
Pad Number :
I/O Bank : 1
Pin Name/Usage : VCCIO1
Dir. : power
I/O Standard :
Voltage : 3.3V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : E4
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : E5
Pad Number :
I/O Bank :
Pin Name/Usage : GNDA3
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : E6
Pad Number : 231
I/O Bank : 8
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : E7
Pad Number : 227
I/O Bank : 8
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : E8
Pad Number : 218
I/O Bank : 8
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : E9
Pad Number : 205
I/O Bank : 7
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : E10
Pad Number : 184
I/O Bank : 7
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : E11
Pad Number : 183
I/O Bank : 7
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : E12
Pad Number :
I/O Bank :
Pin Name/Usage : GNDA2
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : E13
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : E14
Pad Number :
I/O Bank : 6
Pin Name/Usage : VCCIO6
Dir. : power
I/O Standard :
Voltage : 2.5V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : E15
Pad Number : 151
I/O Bank : 6
Pin Name/Usage : GND+
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : E16
Pad Number : 150
I/O Bank : 6
Pin Name/Usage : GND+
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : F1
Pad Number : 14
I/O Bank : 1
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : F2
Pad Number : 13
I/O Bank : 1
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : F3
Pad Number : 8
I/O Bank : 1
Pin Name/Usage : LED[5]
Dir. : output
I/O Standard : 3.3-V LVTTL
Voltage :
I/O Type : Row I/O
User Assignment : Y
Bus Hold : no
Weak Pull Up : Off
Location : F4
Pad Number : 11
I/O Bank : 1
Pin Name/Usage : ^nSTATUS
Dir. :
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : F5
Pad Number :
I/O Bank : --
Pin Name/Usage : VCCA3
Dir. : power
I/O Standard :
Voltage : 2.5V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : F6
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : F7
Pad Number :
I/O Bank :
Pin Name/Usage : VCCINT
Dir. : power
I/O Standard :
Voltage : 1.2V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : F8
Pad Number : 219
I/O Bank : 8
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : F9
Pad Number : 197
I/O Bank : 7
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : F10
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : F11
Pad Number :
I/O Bank :
Pin Name/Usage : VCCINT
Dir. : power
I/O Standard :
Voltage : 1.2V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : F12
Pad Number :
I/O Bank : --
Pin Name/Usage : VCCA2
Dir. : power
I/O Standard :
Voltage : 2.5V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : F13
Pad Number : 161
I/O Bank : 6
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : F14
Pad Number : 167
I/O Bank : 6
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : F15
Pad Number : 163
I/O Bank : 6
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : F16
Pad Number : 162
I/O Bank : 6
Pin Name/Usage : ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN
Dir. : output
I/O Standard : 2.5 V
Voltage :
I/O Type : Row I/O
User Assignment : N
Bus Hold : no
Weak Pull Up : Off
Location : G1
Pad Number : 16
I/O Bank : 1
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : G2
Pad Number : 15
I/O Bank : 1
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : G3
Pad Number :
I/O Bank : 1
Pin Name/Usage : VCCIO1
Dir. : power
I/O Standard :
Voltage : 3.3V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : G4
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : G5
Pad Number : 12
I/O Bank : 1
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : G6
Pad Number :
I/O Bank :
Pin Name/Usage : VCCINT
Dir. : power
I/O Standard :
Voltage : 1.2V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : G7
Pad Number :
I/O Bank :
Pin Name/Usage : VCCINT
Dir. : power
I/O Standard :
Voltage : 1.2V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : G8
Pad Number :
I/O Bank :
Pin Name/Usage : VCCINT
Dir. : power
I/O Standard :
Voltage : 1.2V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : G9
Pad Number :
I/O Bank :
Pin Name/Usage : VCCINT
Dir. : power
I/O Standard :
Voltage : 1.2V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : G10
Pad Number :
I/O Bank :
Pin Name/Usage : VCCINT
Dir. : power
I/O Standard :
Voltage : 1.2V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : G11
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : G12
Pad Number : 155
I/O Bank : 6
Pin Name/Usage : ^MSEL2
Dir. :
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : G12
Pad Number : 156
I/O Bank : 6
Pin Name/Usage : ^MSEL3
Dir. :
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : G13
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : G14
Pad Number :
I/O Bank : 6
Pin Name/Usage : VCCIO6
Dir. : power
I/O Standard :
Voltage : 2.5V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : G15
Pad Number : 160
I/O Bank : 6
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : G16
Pad Number : 159
I/O Bank : 6
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : H1
Pad Number : 17
I/O Bank : 1
Pin Name/Usage : ~ALTERA_DCLK~
Dir. : output
I/O Standard : 3.3-V LVTTL
Voltage :
I/O Type : Row I/O
User Assignment : N
Bus Hold : no
Weak Pull Up : On
Location : H2
Pad Number : 18
I/O Bank : 1
Pin Name/Usage : ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. : input
I/O Standard : 3.3-V LVTTL
Voltage :
I/O Type : Row I/O
User Assignment : N
Bus Hold : no
Weak Pull Up : On
Location : H3
Pad Number : 21
I/O Bank : 1
Pin Name/Usage : #TCK
Dir. : input
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : H4
Pad Number : 20
I/O Bank : 1
Pin Name/Usage : #TDI
Dir. : input
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : H5
Pad Number : 19
I/O Bank : 1
Pin Name/Usage : ^nCONFIG
Dir. :
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : H6
Pad Number :
I/O Bank :
Pin Name/Usage : VCCINT
Dir. : power
I/O Standard :
Voltage : 1.2V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : H7
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : H8
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : H9
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : H10
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : H11
Pad Number :
I/O Bank :
Pin Name/Usage : VCCINT
Dir. : power
I/O Standard :
Voltage : 1.2V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : H12
Pad Number : 154
I/O Bank : 6
Pin Name/Usage : ^MSEL1
Dir. :
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : H13
Pad Number : 153
I/O Bank : 6
Pin Name/Usage : ^MSEL0
Dir. :
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : H14
Pad Number : 152
I/O Bank : 6
Pin Name/Usage : ^CONF_DONE
Dir. :
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : H15
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : H16
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : J1
Pad Number : 30
I/O Bank : 2
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : J2
Pad Number : 29
I/O Bank : 2
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : J3
Pad Number : 24
I/O Bank : 1
Pin Name/Usage : ^nCE
Dir. :
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : J4
Pad Number : 23
I/O Bank : 1
Pin Name/Usage : #TDO
Dir. : output
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : J5
Pad Number : 22
I/O Bank : 1
Pin Name/Usage : #TMS
Dir. : input
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : J6
Pad Number :
I/O Bank :
Pin Name/Usage : VCCINT
Dir. : power
I/O Standard :
Voltage : 1.2V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : J7
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : J8
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : J9
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : J10
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : J11
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : J12
Pad Number :
I/O Bank :
Pin Name/Usage : VCCINT
Dir. : power
I/O Standard :
Voltage : 1.2V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : J13
Pad Number : 146
I/O Bank : 5
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : J14
Pad Number : 144
I/O Bank : 5
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : J15
Pad Number : 143
I/O Bank : 5
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : J16
Pad Number : 142
I/O Bank : 5
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : K1
Pad Number : 37
I/O Bank : 2
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : K2
Pad Number : 36
I/O Bank : 2
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : K3
Pad Number :
I/O Bank : 2
Pin Name/Usage : VCCIO2
Dir. : power
I/O Standard :
Voltage : 3.3V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : K4
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : K5
Pad Number : 45
I/O Bank : 2
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : K6
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : K7
Pad Number :
I/O Bank :
Pin Name/Usage : VCCINT
Dir. : power
I/O Standard :
Voltage : 1.2V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : K8
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : K9
Pad Number :
I/O Bank :
Pin Name/Usage : VCCINT
Dir. : power
I/O Standard :
Voltage : 1.2V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : K10
Pad Number :
I/O Bank :
Pin Name/Usage : VCCINT
Dir. : power
I/O Standard :
Voltage : 1.2V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : K11
Pad Number :
I/O Bank :
Pin Name/Usage : VCCINT
Dir. : power
I/O Standard :
Voltage : 1.2V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : K12
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : K13
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : K14
Pad Number :
I/O Bank : 5
Pin Name/Usage : VCCIO5
Dir. : power
I/O Standard :
Voltage : 2.5V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : K15
Pad Number : 141
I/O Bank : 5
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : K16
Pad Number : 140
I/O Bank : 5
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : L1
Pad Number : 39
I/O Bank : 2
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : L2
Pad Number : 38
I/O Bank : 2
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : L3
Pad Number : 40
I/O Bank : 2
Pin Name/Usage : LED[7]
Dir. : output
I/O Standard : 3.3-V LVTTL
Voltage :
I/O Type : Row I/O
User Assignment : Y
Bus Hold : no
Weak Pull Up : Off
Location : L4
Pad Number : 46
I/O Bank : 2
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : L5
Pad Number :
I/O Bank : --
Pin Name/Usage : VCCA1
Dir. : power
I/O Standard :
Voltage : 2.5V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : L6
Pad Number :
I/O Bank :
Pin Name/Usage : VCCINT
Dir. : power
I/O Standard :
Voltage : 1.2V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : L7
Pad Number : 75
I/O Bank : 3
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : L8
Pad Number : 79
I/O Bank : 3
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : L9
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : L10
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : L11
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : L12
Pad Number :
I/O Bank : --
Pin Name/Usage : VCCA4
Dir. : power
I/O Standard :
Voltage : 2.5V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : L13
Pad Number : 136
I/O Bank : 5
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : L14
Pad Number : 134
I/O Bank : 5
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : L15
Pad Number : 138
I/O Bank : 5
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : L16
Pad Number : 137
I/O Bank : 5
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : M1
Pad Number : 28
I/O Bank : 2
Pin Name/Usage : GND+
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : M2
Pad Number : 27
I/O Bank : 2
Pin Name/Usage : GND+
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : M3
Pad Number :
I/O Bank : 2
Pin Name/Usage : VCCIO2
Dir. : power
I/O Standard :
Voltage : 3.3V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : M4
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : M5
Pad Number :
I/O Bank :
Pin Name/Usage : GNDA1
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : M6
Pad Number : 64
I/O Bank : 3
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : M7
Pad Number : 68
I/O Bank : 3
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : M8
Pad Number : 81
I/O Bank : 3
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : M9
Pad Number :
I/O Bank :
Pin Name/Usage : VCCINT
Dir. : power
I/O Standard :
Voltage : 1.2V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : M10
Pad Number : 111
I/O Bank : 4
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : M11
Pad Number :
I/O Bank :
Pin Name/Usage : VCCINT
Dir. : power
I/O Standard :
Voltage : 1.2V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : M12
Pad Number :
I/O Bank :
Pin Name/Usage : GNDA4
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : M13
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : M14
Pad Number :
I/O Bank : 5
Pin Name/Usage : VCCIO5
Dir. : power
I/O Standard :
Voltage : 2.5V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : M15
Pad Number : 149
I/O Bank : 5
Pin Name/Usage : GND+
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : M16
Pad Number : 148
I/O Bank : 5
Pin Name/Usage : GND+
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : N1
Pad Number : 44
I/O Bank : 2
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : N2
Pad Number : 43
I/O Bank : 2
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : N3
Pad Number : 52
I/O Bank : 3
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : N4
Pad Number :
I/O Bank :
Pin Name/Usage : VCCD_PLL1
Dir. : power
I/O Standard :
Voltage : 1.2V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : N5
Pad Number : 62
I/O Bank : 3
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : N6
Pad Number : 63
I/O Bank : 3
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : N7
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : N8
Pad Number : 82
I/O Bank : 3
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : N9
Pad Number : 93
I/O Bank : 4
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : N10
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : N11
Pad Number : 112
I/O Bank : 4
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : N12
Pad Number : 117
I/O Bank : 4
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : N13
Pad Number :
I/O Bank :
Pin Name/Usage : VCCD_PLL4
Dir. : power
I/O Standard :
Voltage : 1.2V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : N14
Pad Number : 126
I/O Bank : 5
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : N15
Pad Number : 133
I/O Bank : 5
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : N16
Pad Number : 132
I/O Bank : 5
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : P1
Pad Number : 51
I/O Bank : 2
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : P2
Pad Number : 50
I/O Bank : 2
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : P3
Pad Number : 53
I/O Bank : 3
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : P4
Pad Number :
I/O Bank : 3
Pin Name/Usage : VCCIO3
Dir. : power
I/O Standard :
Voltage : 3.3V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : P5
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : P6
Pad Number : 67
I/O Bank : 3
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : P7
Pad Number :
I/O Bank : 3
Pin Name/Usage : VCCIO3
Dir. : power
I/O Standard :
Voltage : 3.3V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : P8
Pad Number : 85
I/O Bank : 3
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : P9
Pad Number : 105
I/O Bank : 4
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : P10
Pad Number :
I/O Bank : 4
Pin Name/Usage : VCCIO4
Dir. : power
I/O Standard :
Voltage : 2.5V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : P11
Pad Number : 106
I/O Bank : 4
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : P12
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : P13
Pad Number :
I/O Bank : 4
Pin Name/Usage : VCCIO4
Dir. : power
I/O Standard :
Voltage : 2.5V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : P14
Pad Number : 119
I/O Bank : 4
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : P15
Pad Number : 127
I/O Bank : 5
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : P16
Pad Number : 128
I/O Bank : 5
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : R1
Pad Number : 49
I/O Bank : 2
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : R2
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : R3
Pad Number : 54
I/O Bank : 3
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : R4
Pad Number : 60
I/O Bank : 3
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : R5
Pad Number : 71
I/O Bank : 3
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : R6
Pad Number : 73
I/O Bank : 3
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : R7
Pad Number : 76
I/O Bank : 3
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : R8
Pad Number : 86
I/O Bank : 3
Pin Name/Usage : CLOCK_50
Dir. : input
I/O Standard : 3.3-V LVTTL
Voltage :
I/O Type : Column I/O
User Assignment : Y
Bus Hold : no
Weak Pull Up : Off
Location : R9
Pad Number : 88
I/O Bank : 4
Pin Name/Usage : GND+
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : R10
Pad Number : 96
I/O Bank : 4
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : R11
Pad Number : 98
I/O Bank : 4
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : R12
Pad Number : 100
I/O Bank : 4
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : R13
Pad Number : 107
I/O Bank : 4
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : R14
Pad Number : 120
I/O Bank : 4
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : R15
Pad Number :
I/O Bank :
Pin Name/Usage : GND
Dir. : gnd
I/O Standard :
Voltage :
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : R16
Pad Number : 129
I/O Bank : 5
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Row I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : T1
Pad Number :
I/O Bank : 3
Pin Name/Usage : VCCIO3
Dir. : power
I/O Standard :
Voltage : 3.3V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : T2
Pad Number : 59
I/O Bank : 3
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : T3
Pad Number : 55
I/O Bank : 3
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : T4
Pad Number : 61
I/O Bank : 3
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : T5
Pad Number : 72
I/O Bank : 3
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : T6
Pad Number : 74
I/O Bank : 3
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : T7
Pad Number : 77
I/O Bank : 3
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : T8
Pad Number : 87
I/O Bank : 3
Pin Name/Usage : GND+
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : T9
Pad Number : 89
I/O Bank : 4
Pin Name/Usage : GND+
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : --
Weak Pull Up : --
Location : T10
Pad Number : 97
I/O Bank : 4
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : T11
Pad Number : 99
I/O Bank : 4
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : T12
Pad Number : 101
I/O Bank : 4
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : T13
Pad Number : 108
I/O Bank : 4
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : T14
Pad Number : 115
I/O Bank : 4
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : T15
Pad Number : 116
I/O Bank : 4
Pin Name/Usage : RESERVED_INPUT_WITH_WEAK_PULLUP
Dir. :
I/O Standard :
Voltage :
I/O Type : Column I/O
User Assignment :
Bus Hold : no
Weak Pull Up : On
Location : T16
Pad Number :
I/O Bank : 4
Pin Name/Usage : VCCIO4
Dir. : power
I/O Standard :
Voltage : 2.5V
I/O Type : --
User Assignment :
Bus Hold : --
Weak Pull Up : --
+--------------------------------------------------------------------------------+
Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+--------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity ;
+--------------------------------------------------------------------------------+
Compilation Hierarchy Node : |spectrum
2022-03-30 12:47:42 +03:00
Logic Cells : 33 (33)
Dedicated Logic Registers : 24 (24)
2022-03-30 11:53:01 +03:00
I/O Registers : 0 (0)
2022-03-30 12:47:42 +03:00
Memory Bits : 64
M9Ks : 1
2022-03-30 11:53:01 +03:00
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 9
Virtual Pins : 0
2022-03-30 12:47:42 +03:00
LUT-Only LCs : 9 (9)
Register-Only LCs : 0 (0)
LUT/Register LCs : 24 (24)
2022-03-30 11:53:01 +03:00
Full Hierarchy Name : |spectrum
Library Name : work
2022-03-30 12:47:42 +03:00
Compilation Hierarchy Node : |rom0:rom|
Logic Cells : 0 (0)
Dedicated Logic Registers : 0 (0)
I/O Registers : 0 (0)
Memory Bits : 64
M9Ks : 1
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
LUT-Only LCs : 0 (0)
Register-Only LCs : 0 (0)
LUT/Register LCs : 0 (0)
Full Hierarchy Name : |spectrum|rom0:rom
Library Name : work
Compilation Hierarchy Node : |altsyncram:altsyncram_component|
Logic Cells : 0 (0)
Dedicated Logic Registers : 0 (0)
I/O Registers : 0 (0)
Memory Bits : 64
M9Ks : 1
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
LUT-Only LCs : 0 (0)
Register-Only LCs : 0 (0)
LUT/Register LCs : 0 (0)
Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component
Library Name : work
Compilation Hierarchy Node : |altsyncram_ro91:auto_generated|
Logic Cells : 0 (0)
Dedicated Logic Registers : 0 (0)
I/O Registers : 0 (0)
Memory Bits : 64
M9Ks : 1
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
LUT-Only LCs : 0 (0)
Register-Only LCs : 0 (0)
LUT/Register LCs : 0 (0)
Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated
Library Name : work
2022-03-30 11:53:01 +03:00
+--------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+--------------------------------------------------------------------------------+
; Delay Chain Summary ;
+--------------------------------------------------------------------------------+
Name : LED[0]
Pin Type : Output
Pad to Core 0 : --
Pad to Core 1 : --
Pad to Input Register : --
TCO : --
TCOE : --
Name : LED[1]
Pin Type : Output
Pad to Core 0 : --
Pad to Core 1 : --
Pad to Input Register : --
TCO : --
TCOE : --
Name : LED[2]
Pin Type : Output
Pad to Core 0 : --
Pad to Core 1 : --
Pad to Input Register : --
TCO : --
TCOE : --
Name : LED[3]
Pin Type : Output
Pad to Core 0 : --
Pad to Core 1 : --
Pad to Input Register : --
TCO : --
TCOE : --
Name : LED[4]
Pin Type : Output
Pad to Core 0 : --
Pad to Core 1 : --
Pad to Input Register : --
TCO : --
TCOE : --
Name : LED[5]
Pin Type : Output
Pad to Core 0 : --
Pad to Core 1 : --
Pad to Input Register : --
TCO : --
TCOE : --
Name : LED[6]
Pin Type : Output
Pad to Core 0 : --
Pad to Core 1 : --
Pad to Input Register : --
TCO : --
TCOE : --
Name : LED[7]
Pin Type : Output
Pad to Core 0 : --
Pad to Core 1 : --
Pad to Input Register : --
TCO : --
TCOE : --
Name : CLOCK_50
Pin Type : Input
Pad to Core 0 : (0) 0 ps
Pad to Core 1 : --
Pad to Input Register : --
TCO : --
TCOE : --
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Pad To Core Delay Chain Fanout ;
+--------------------------------------------------------------------------------+
Source Pin / Fanout : CLOCK_50
Pad To Core Index :
Setting :
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Control Signals ;
+--------------------------------------------------------------------------------+
Name : CLOCK_50
Location : PIN_R8
2022-03-30 12:47:42 +03:00
Fan-Out : 25
2022-03-30 11:53:01 +03:00
Usage : Clock
Global : yes
Global Resource Used : Global Clock
Global Line Name : GCLK18
Enable Signal Source Name : --
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Global & Other Fast Signals ;
+--------------------------------------------------------------------------------+
Name : CLOCK_50
Location : PIN_R8
2022-03-30 12:47:42 +03:00
Fan-Out : 25
Fan-Out Using Intentional Clock Skew : 3
2022-03-30 11:53:01 +03:00
Global Resource Used : Global Clock
Global Line Name : GCLK18
Enable Signal Source Name : --
+--------------------------------------------------------------------------------+
2022-03-30 12:47:42 +03:00
+------------------------------------------------------------------------------------------+
; Non-Global High Fan-Out Signals ;
+--------------------------------------------------------------------------------+---------+
; Name ; Fan-Out ;
+--------------------------------------------------------------------------------+---------+
; address[0] ; 4 ;
; Add0~40 ; 4 ;
; Equal0~4 ; 3 ;
; address[1] ; 3 ;
; Add0~38 ; 3 ;
; Add0~36 ; 3 ;
; Add0~34 ; 3 ;
; Add0~32 ; 3 ;
; Equal0~5 ; 2 ;
; address[2] ; 2 ;
; Add0~30 ; 2 ;
; Add0~28 ; 2 ;
; Add0~26 ; 2 ;
; Add0~24 ; 2 ;
; Add0~22 ; 2 ;
; Add0~20 ; 2 ;
; Add0~18 ; 2 ;
; Add0~16 ; 2 ;
; Add0~14 ; 2 ;
; Add0~12 ; 2 ;
; Add0~10 ; 2 ;
; Add0~8 ; 2 ;
; Add0~6 ; 2 ;
; Add0~4 ; 2 ;
; Add0~2 ; 2 ;
; Add0~0 ; 2 ;
; address[2]~3 ; 1 ;
; address[1]~2 ; 1 ;
; address[1]~1 ; 1 ;
; Equal0~7 ; 1 ;
; Equal0~6 ; 1 ;
; address[0]~0 ; 1 ;
; Equal0~3 ; 1 ;
; Equal0~2 ; 1 ;
; Equal0~1 ; 1 ;
; Equal0~0 ; 1 ;
; counter[0] ; 1 ;
; counter[1] ; 1 ;
; counter[2] ; 1 ;
; counter[3] ; 1 ;
; counter[4] ; 1 ;
; counter[5] ; 1 ;
; counter[6] ; 1 ;
; counter[7] ; 1 ;
; counter[8] ; 1 ;
; counter[9] ; 1 ;
; counter[10] ; 1 ;
; counter[11] ; 1 ;
; counter[12] ; 1 ;
; counter[13] ; 1 ;
; counter[14] ; 1 ;
; counter[15] ; 1 ;
; counter[16] ; 1 ;
; counter[17] ; 1 ;
; counter[18] ; 1 ;
; counter[19] ; 1 ;
; counter[20] ; 1 ;
; Add0~39 ; 1 ;
; Add0~37 ; 1 ;
; Add0~35 ; 1 ;
; Add0~33 ; 1 ;
; Add0~31 ; 1 ;
; Add0~29 ; 1 ;
; Add0~27 ; 1 ;
; Add0~25 ; 1 ;
; Add0~23 ; 1 ;
; Add0~21 ; 1 ;
; Add0~19 ; 1 ;
; Add0~17 ; 1 ;
; Add0~15 ; 1 ;
; Add0~13 ; 1 ;
; Add0~11 ; 1 ;
; Add0~9 ; 1 ;
; Add0~7 ; 1 ;
; Add0~5 ; 1 ;
; Add0~3 ; 1 ;
; Add0~1 ; 1 ;
; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[1] ; 1 ;
; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[2] ; 1 ;
; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[3] ; 1 ;
; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[4] ; 1 ;
; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[5] ; 1 ;
; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[6] ; 1 ;
; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[7] ; 1 ;
; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[0] ; 1 ;
+--------------------------------------------------------------------------------+---------+
+--------------------------------------------------------------------------------+
; Fitter RAM Summary ;
+--------------------------------------------------------------------------------+
Name : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ALTSYNCRAM
Type : AUTO
Mode : ROM
Clock Mode : Single Clock
Port A Depth : 8
Port A Width : 8
Port B Depth : --
Port B Width : --
Port A Input Registers : yes
Port A Output Registers : yes
Port B Input Registers : --
Port B Output Registers : --
Size : 64
Implementation Port A Depth : 8
Implementation Port A Width : 8
Implementation Port B Depth : --
Implementation Port B Width : --
Implementation Bits : 64
M9Ks : 1
MIF : led_patterns.mif
Location : M9K_X33_Y26_N0
Mixed Width RDW Mode : Don't care
Port A RDW Mode : Old data
Port B RDW Mode : Old data
Fits in MLABs : No - Unknown
+--------------------------------------------------------------------------------+
Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
RAM content values are presented in the following format: (Binary) (Octal) (Decimal) (Hexadecimal)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ALTSYNCRAM ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Addr ; +0 ; +1 ; +2 ; +3 ; +4 ; +5 ; +6 ; +7 ;
+----------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+
;0;(10000001) (201) (129) (81) ;(01000010) (102) (66) (42) ;(00100100) (44) (36) (24) ;(00011000) (30) (24) (18) ;(00011000) (30) (24) (18) ;(00100100) (44) (36) (24) ;(01000010) (102) (66) (42) ;(10000001) (201) (129) (81) ;
2022-03-30 11:53:01 +03:00
+-----------------------------------------------+
; Routing Usage Summary ;
+-----------------------+-----------------------+
; Routing Resource Type ; Usage ;
+-----------------------+-----------------------+
2022-03-30 12:47:42 +03:00
; Block interconnects ; 42 / 71,559 ( < 1 % ) ;
; C16 interconnects ; 3 / 2,597 ( < 1 % ) ;
; C4 interconnects ; 20 / 46,848 ( < 1 % ) ;
; Direct links ; 24 / 71,559 ( < 1 % ) ;
2022-03-30 11:53:01 +03:00
; Global clocks ; 1 / 20 ( 5 % ) ;
2022-03-30 12:47:42 +03:00
; Local interconnects ; 24 / 24,624 ( < 1 % ) ;
; R24 interconnects ; 7 / 2,496 ( < 1 % ) ;
; R4 interconnects ; 27 / 62,424 ( < 1 % ) ;
2022-03-30 11:53:01 +03:00
+-----------------------+-----------------------+
2022-03-30 12:47:42 +03:00
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+---------------------------------------------+-----------------------------+
; Number of Logic Elements (Average = 11.00) ; Number of LABs (Total = 3) ;
+---------------------------------------------+-----------------------------+
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 1 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 1 ;
; 16 ; 0 ;
+---------------------------------------------+-----------------------------+
2022-03-30 11:53:01 +03:00
+------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+-----------------------------+
2022-03-30 12:47:42 +03:00
; LAB-wide Signals (Average = 1.00) ; Number of LABs (Total = 3) ;
2022-03-30 11:53:01 +03:00
+------------------------------------+-----------------------------+
2022-03-30 12:47:42 +03:00
; 1 Clock ; 3 ;
2022-03-30 11:53:01 +03:00
+------------------------------------+-----------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+----------------------------------------------+-----------------------------+
2022-03-30 12:47:42 +03:00
; Number of Signals Sourced (Average = 19.00) ; Number of LABs (Total = 3) ;
2022-03-30 11:53:01 +03:00
+----------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
2022-03-30 12:47:42 +03:00
; 2 ; 0 ;
2022-03-30 11:53:01 +03:00
; 3 ; 0 ;
2022-03-30 12:47:42 +03:00
; 4 ; 0 ;
2022-03-30 11:53:01 +03:00
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
2022-03-30 12:47:42 +03:00
; 8 ; 0 ;
; 9 ; 1 ;
2022-03-30 11:53:01 +03:00
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 0 ;
; 17 ; 0 ;
; 18 ; 0 ;
; 19 ; 0 ;
; 20 ; 0 ;
; 21 ; 0 ;
2022-03-30 12:47:42 +03:00
; 22 ; 1 ;
2022-03-30 11:53:01 +03:00
; 23 ; 0 ;
; 24 ; 0 ;
; 25 ; 0 ;
2022-03-30 12:47:42 +03:00
; 26 ; 1 ;
2022-03-30 11:53:01 +03:00
+----------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+-----------------------------+
2022-03-30 12:47:42 +03:00
; Number of Signals Sourced Out (Average = 4.33) ; Number of LABs (Total = 3) ;
2022-03-30 11:53:01 +03:00
+-------------------------------------------------+-----------------------------+
2022-03-30 12:47:42 +03:00
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 1 ;
2022-03-30 11:53:01 +03:00
; 4 ; 1 ;
; 5 ; 0 ;
2022-03-30 12:47:42 +03:00
; 6 ; 1 ;
2022-03-30 11:53:01 +03:00
+-------------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+-----------------------------+
2022-03-30 12:47:42 +03:00
; Number of Distinct Inputs (Average = 4.67) ; Number of LABs (Total = 3) ;
2022-03-30 11:53:01 +03:00
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
2022-03-30 12:47:42 +03:00
; 2 ; 1 ;
; 3 ; 0 ;
2022-03-30 11:53:01 +03:00
; 4 ; 0 ;
2022-03-30 12:47:42 +03:00
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 1 ;
2022-03-30 11:53:01 +03:00
+---------------------------------------------+-----------------------------+
+------------------------------------------+
; I/O Rules Summary ;
+----------------------------------+-------+
; I/O Rules Statistic ; Total ;
+----------------------------------+-------+
; Total I/O Rules ; 30 ;
; Number of I/O Rules Passed ; 9 ;
; Number of I/O Rules Failed ; 0 ;
; Number of I/O Rules Unchecked ; 0 ;
; Number of I/O Rules Inapplicable ; 21 ;
+----------------------------------+-------+
+--------------------------------------------------------------------------------+
; I/O Rules Details ;
+--------------------------------------------------------------------------------+
Status : Pass
ID : IO_000001
Category : Capacity Checks
Rule Description : Number of pins in an I/O bank should not exceed the number of locations available.
Severity : Critical
Information : 0 such failures found.
Area : I/O
Extra Information :
Status : Inapplicable
ID : IO_000002
Category : Capacity Checks
Rule Description : Number of clocks in an I/O bank should not exceed the number of clocks available.
Severity : Critical
Information : No Global Signal assignments found.
Area : I/O
Extra Information :
Status : Pass
ID : IO_000003
Category : Capacity Checks
Rule Description : Number of pins in a Vrefgroup should not exceed the number of locations available.
Severity : Critical
Information : 0 such failures found.
Area : I/O
Extra Information :
Status : Inapplicable
ID : IO_000004
Category : Voltage Compatibility Checks
Rule Description : The I/O bank should support the requested VCCIO.
Severity : Critical
Information : No IOBANK_VCCIO assignments found.
Area : I/O
Extra Information :
Status : Inapplicable
ID : IO_000005
Category : Voltage Compatibility Checks
Rule Description : The I/O bank should not have competing VREF values.
Severity : Critical
Information : No VREF I/O Standard assignments found.
Area : I/O
Extra Information :
Status : Pass
ID : IO_000006
Category : Voltage Compatibility Checks
Rule Description : The I/O bank should not have competing VCCIO values.
Severity : Critical
Information : 0 such failures found.
Area : I/O
Extra Information :
Status : Pass
ID : IO_000007
Category : Valid Location Checks
Rule Description : Checks for unavailable locations.
Severity : Critical
Information : 0 such failures found.
Area : I/O
Extra Information :
Status : Inapplicable
ID : IO_000008
Category : Valid Location Checks
Rule Description : Checks for reserved locations.
Severity : Critical
Information : No reserved LogicLock region found.
Area : I/O
Extra Information :
Status : Pass
ID : IO_000009
Category : I/O Properties Checks for One I/O
Rule Description : The location should support the requested I/O standard.
Severity : Critical
Information : 0 such failures found.
Area : I/O
Extra Information :
Status : Pass
ID : IO_000010
Category : I/O Properties Checks for One I/O
Rule Description : The location should support the requested I/O direction.
Severity : Critical
Information : 0 such failures found.
Area : I/O
Extra Information :
Status : Inapplicable
ID : IO_000011
Category : I/O Properties Checks for One I/O
Rule Description : The location should support the requested Current Strength.
Severity : Critical
Information : No Current Strength assignments found.
Area : I/O
Extra Information :
Status : Inapplicable
ID : IO_000012
Category : I/O Properties Checks for One I/O
Rule Description : The location should support the requested On Chip Termination value.
Severity : Critical
Information : No Termination assignments found.
Area : I/O
Extra Information :
Status : Inapplicable
ID : IO_000013
Category : I/O Properties Checks for One I/O
Rule Description : The location should support the requested Bus Hold value.
Severity : Critical
Information : No Enable Bus-Hold Circuitry assignments found.
Area : I/O
Extra Information :
Status : Inapplicable
ID : IO_000014
Category : I/O Properties Checks for One I/O
Rule Description : The location should support the requested Weak Pull Up value.
Severity : Critical
Information : No Weak Pull-Up Resistor assignments found.
Area : I/O
Extra Information :
Status : Pass
ID : IO_000015
Category : I/O Properties Checks for One I/O
Rule Description : The location should support the requested PCI Clamp Diode.
Severity : Critical
Information : 0 such failures found.
Area : I/O
Extra Information :
Status : Inapplicable
ID : IO_000018
Category : I/O Properties Checks for One I/O
Rule Description : The I/O standard should support the requested Current Strength.
Severity : Critical
Information : No Current Strength assignments found.
Area : I/O
Extra Information :
Status : Inapplicable
ID : IO_000019
Category : I/O Properties Checks for One I/O
Rule Description : The I/O standard should support the requested On Chip Termination value.
Severity : Critical
Information : No Termination assignments found.
Area : I/O
Extra Information :
Status : Pass
ID : IO_000020
Category : I/O Properties Checks for One I/O
Rule Description : The I/O standard should support the requested PCI Clamp Diode.
Severity : Critical
Information : 0 such failures found.
Area : I/O
Extra Information :
Status : Inapplicable
ID : IO_000021
Category : I/O Properties Checks for One I/O
Rule Description : The I/O standard should support the requested Weak Pull Up value.
Severity : Critical
Information : No Weak Pull-Up Resistor assignments found.
Area : I/O
Extra Information :
Status : Inapplicable
ID : IO_000022
Category : I/O Properties Checks for One I/O
Rule Description : The I/O standard should support the requested Bus Hold value.
Severity : Critical
Information : No Enable Bus-Hold Circuitry assignments found.
Area : I/O
Extra Information :
Status : Inapplicable
ID : IO_000023
Category : I/O Properties Checks for One I/O
Rule Description : The I/O standard should support the Open Drain value.
Severity : Critical
Information : No open drain assignments found.
Area : I/O
Extra Information :
Status : Inapplicable
ID : IO_000024
Category : I/O Properties Checks for One I/O
Rule Description : The I/O direction should support the On Chip Termination value.
Severity : Critical
Information : No Termination assignments found.
Area : I/O
Extra Information :
Status : Inapplicable
ID : IO_000026
Category : I/O Properties Checks for One I/O
Rule Description : On Chip Termination and Current Strength should not be used at the same time.
Severity : Critical
Information : No Current Strength or Termination assignments found.
Area : I/O
Extra Information :
Status : Inapplicable
ID : IO_000027
Category : I/O Properties Checks for One I/O
Rule Description : Weak Pull Up and Bus Hold should not be used at the same time.
Severity : Critical
Information : No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.
Area : I/O
Extra Information :
Status : Inapplicable
ID : IO_000045
Category : I/O Properties Checks for One I/O
Rule Description : The I/O standard should support the requested Slew Rate value.
Severity : Critical
Information : No Slew Rate assignments found.
Area : I/O
Extra Information :
Status : Inapplicable
ID : IO_000046
Category : I/O Properties Checks for One I/O
Rule Description : The location should support the requested Slew Rate value.
Severity : Critical
Information : No Slew Rate assignments found.
Area : I/O
Extra Information :
Status : Inapplicable
ID : IO_000047
Category : I/O Properties Checks for One I/O
Rule Description : On Chip Termination and Slew Rate should not be used at the same time.
Severity : Critical
Information : No Slew Rate assignments found.
Area : I/O
Extra Information :
Status : Pass
ID : IO_000033
Category : Electromigration Checks
Rule Description : Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.
Severity : Critical
Information : 0 such failures found.
Area : I/O
Extra Information :
Status : Inapplicable
ID : IO_000034
Category : SI Related Distance Checks
Rule Description : Single-ended outputs should be 5 LAB row(s) away from a differential I/O.
Severity : High
Information : No Differential I/O Standard assignments found.
Area : I/O
Extra Information :
Status : Inapplicable
ID : IO_000042
Category : SI Related SSO Limit Checks
Rule Description : No more than 20 outputs are allowed in a VREF group when VREF is being read from.
Severity : High
Information : No VREF I/O Standard assignments found.
Area : I/O
Extra Information :
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; I/O Rules Matrix ;
+--------------------------------------------------------------------------------+
Pin/Rules : Total Pass
IO_000001 : 9
IO_000002 : 0
IO_000003 : 9
IO_000004 : 0
IO_000005 : 0
IO_000006 : 9
IO_000007 : 9
IO_000008 : 0
IO_000009 : 9
IO_000010 : 9
IO_000011 : 0
IO_000012 : 0
IO_000013 : 0
IO_000014 : 0
IO_000015 : 1
IO_000018 : 0
IO_000019 : 0
IO_000020 : 1
IO_000021 : 0
IO_000022 : 0
IO_000023 : 0
IO_000024 : 0
IO_000026 : 0
IO_000027 : 0
IO_000045 : 0
IO_000046 : 0
IO_000047 : 0
IO_000033 : 9
IO_000034 : 0
IO_000042 : 0
Pin/Rules : Total Unchecked
IO_000001 : 0
IO_000002 : 0
IO_000003 : 0
IO_000004 : 0
IO_000005 : 0
IO_000006 : 0
IO_000007 : 0
IO_000008 : 0
IO_000009 : 0
IO_000010 : 0
IO_000011 : 0
IO_000012 : 0
IO_000013 : 0
IO_000014 : 0
IO_000015 : 0
IO_000018 : 0
IO_000019 : 0
IO_000020 : 0
IO_000021 : 0
IO_000022 : 0
IO_000023 : 0
IO_000024 : 0
IO_000026 : 0
IO_000027 : 0
IO_000045 : 0
IO_000046 : 0
IO_000047 : 0
IO_000033 : 0
IO_000034 : 0
IO_000042 : 0
Pin/Rules : Total Inapplicable
IO_000001 : 0
IO_000002 : 9
IO_000003 : 0
IO_000004 : 9
IO_000005 : 9
IO_000006 : 0
IO_000007 : 0
IO_000008 : 9
IO_000009 : 0
IO_000010 : 0
IO_000011 : 9
IO_000012 : 9
IO_000013 : 9
IO_000014 : 9
IO_000015 : 8
IO_000018 : 9
IO_000019 : 9
IO_000020 : 8
IO_000021 : 9
IO_000022 : 9
IO_000023 : 9
IO_000024 : 9
IO_000026 : 9
IO_000027 : 9
IO_000045 : 9
IO_000046 : 9
IO_000047 : 9
IO_000033 : 0
IO_000034 : 9
IO_000042 : 9
Pin/Rules : Total Fail
IO_000001 : 0
IO_000002 : 0
IO_000003 : 0
IO_000004 : 0
IO_000005 : 0
IO_000006 : 0
IO_000007 : 0
IO_000008 : 0
IO_000009 : 0
IO_000010 : 0
IO_000011 : 0
IO_000012 : 0
IO_000013 : 0
IO_000014 : 0
IO_000015 : 0
IO_000018 : 0
IO_000019 : 0
IO_000020 : 0
IO_000021 : 0
IO_000022 : 0
IO_000023 : 0
IO_000024 : 0
IO_000026 : 0
IO_000027 : 0
IO_000045 : 0
IO_000046 : 0
IO_000047 : 0
IO_000033 : 0
IO_000034 : 0
IO_000042 : 0
Pin/Rules : LED[0]
IO_000001 : Pass
IO_000002 : Inapplicable
IO_000003 : Pass
IO_000004 : Inapplicable
IO_000005 : Inapplicable
IO_000006 : Pass
IO_000007 : Pass
IO_000008 : Inapplicable
IO_000009 : Pass
IO_000010 : Pass
IO_000011 : Inapplicable
IO_000012 : Inapplicable
IO_000013 : Inapplicable
IO_000014 : Inapplicable
IO_000015 : Inapplicable
IO_000018 : Inapplicable
IO_000019 : Inapplicable
IO_000020 : Inapplicable
IO_000021 : Inapplicable
IO_000022 : Inapplicable
IO_000023 : Inapplicable
IO_000024 : Inapplicable
IO_000026 : Inapplicable
IO_000027 : Inapplicable
IO_000045 : Inapplicable
IO_000046 : Inapplicable
IO_000047 : Inapplicable
IO_000033 : Pass
IO_000034 : Inapplicable
IO_000042 : Inapplicable
Pin/Rules : LED[1]
IO_000001 : Pass
IO_000002 : Inapplicable
IO_000003 : Pass
IO_000004 : Inapplicable
IO_000005 : Inapplicable
IO_000006 : Pass
IO_000007 : Pass
IO_000008 : Inapplicable
IO_000009 : Pass
IO_000010 : Pass
IO_000011 : Inapplicable
IO_000012 : Inapplicable
IO_000013 : Inapplicable
IO_000014 : Inapplicable
IO_000015 : Inapplicable
IO_000018 : Inapplicable
IO_000019 : Inapplicable
IO_000020 : Inapplicable
IO_000021 : Inapplicable
IO_000022 : Inapplicable
IO_000023 : Inapplicable
IO_000024 : Inapplicable
IO_000026 : Inapplicable
IO_000027 : Inapplicable
IO_000045 : Inapplicable
IO_000046 : Inapplicable
IO_000047 : Inapplicable
IO_000033 : Pass
IO_000034 : Inapplicable
IO_000042 : Inapplicable
Pin/Rules : LED[2]
IO_000001 : Pass
IO_000002 : Inapplicable
IO_000003 : Pass
IO_000004 : Inapplicable
IO_000005 : Inapplicable
IO_000006 : Pass
IO_000007 : Pass
IO_000008 : Inapplicable
IO_000009 : Pass
IO_000010 : Pass
IO_000011 : Inapplicable
IO_000012 : Inapplicable
IO_000013 : Inapplicable
IO_000014 : Inapplicable
IO_000015 : Inapplicable
IO_000018 : Inapplicable
IO_000019 : Inapplicable
IO_000020 : Inapplicable
IO_000021 : Inapplicable
IO_000022 : Inapplicable
IO_000023 : Inapplicable
IO_000024 : Inapplicable
IO_000026 : Inapplicable
IO_000027 : Inapplicable
IO_000045 : Inapplicable
IO_000046 : Inapplicable
IO_000047 : Inapplicable
IO_000033 : Pass
IO_000034 : Inapplicable
IO_000042 : Inapplicable
Pin/Rules : LED[3]
IO_000001 : Pass
IO_000002 : Inapplicable
IO_000003 : Pass
IO_000004 : Inapplicable
IO_000005 : Inapplicable
IO_000006 : Pass
IO_000007 : Pass
IO_000008 : Inapplicable
IO_000009 : Pass
IO_000010 : Pass
IO_000011 : Inapplicable
IO_000012 : Inapplicable
IO_000013 : Inapplicable
IO_000014 : Inapplicable
IO_000015 : Inapplicable
IO_000018 : Inapplicable
IO_000019 : Inapplicable
IO_000020 : Inapplicable
IO_000021 : Inapplicable
IO_000022 : Inapplicable
IO_000023 : Inapplicable
IO_000024 : Inapplicable
IO_000026 : Inapplicable
IO_000027 : Inapplicable
IO_000045 : Inapplicable
IO_000046 : Inapplicable
IO_000047 : Inapplicable
IO_000033 : Pass
IO_000034 : Inapplicable
IO_000042 : Inapplicable
Pin/Rules : LED[4]
IO_000001 : Pass
IO_000002 : Inapplicable
IO_000003 : Pass
IO_000004 : Inapplicable
IO_000005 : Inapplicable
IO_000006 : Pass
IO_000007 : Pass
IO_000008 : Inapplicable
IO_000009 : Pass
IO_000010 : Pass
IO_000011 : Inapplicable
IO_000012 : Inapplicable
IO_000013 : Inapplicable
IO_000014 : Inapplicable
IO_000015 : Inapplicable
IO_000018 : Inapplicable
IO_000019 : Inapplicable
IO_000020 : Inapplicable
IO_000021 : Inapplicable
IO_000022 : Inapplicable
IO_000023 : Inapplicable
IO_000024 : Inapplicable
IO_000026 : Inapplicable
IO_000027 : Inapplicable
IO_000045 : Inapplicable
IO_000046 : Inapplicable
IO_000047 : Inapplicable
IO_000033 : Pass
IO_000034 : Inapplicable
IO_000042 : Inapplicable
Pin/Rules : LED[5]
IO_000001 : Pass
IO_000002 : Inapplicable
IO_000003 : Pass
IO_000004 : Inapplicable
IO_000005 : Inapplicable
IO_000006 : Pass
IO_000007 : Pass
IO_000008 : Inapplicable
IO_000009 : Pass
IO_000010 : Pass
IO_000011 : Inapplicable
IO_000012 : Inapplicable
IO_000013 : Inapplicable
IO_000014 : Inapplicable
IO_000015 : Inapplicable
IO_000018 : Inapplicable
IO_000019 : Inapplicable
IO_000020 : Inapplicable
IO_000021 : Inapplicable
IO_000022 : Inapplicable
IO_000023 : Inapplicable
IO_000024 : Inapplicable
IO_000026 : Inapplicable
IO_000027 : Inapplicable
IO_000045 : Inapplicable
IO_000046 : Inapplicable
IO_000047 : Inapplicable
IO_000033 : Pass
IO_000034 : Inapplicable
IO_000042 : Inapplicable
Pin/Rules : LED[6]
IO_000001 : Pass
IO_000002 : Inapplicable
IO_000003 : Pass
IO_000004 : Inapplicable
IO_000005 : Inapplicable
IO_000006 : Pass
IO_000007 : Pass
IO_000008 : Inapplicable
IO_000009 : Pass
IO_000010 : Pass
IO_000011 : Inapplicable
IO_000012 : Inapplicable
IO_000013 : Inapplicable
IO_000014 : Inapplicable
IO_000015 : Inapplicable
IO_000018 : Inapplicable
IO_000019 : Inapplicable
IO_000020 : Inapplicable
IO_000021 : Inapplicable
IO_000022 : Inapplicable
IO_000023 : Inapplicable
IO_000024 : Inapplicable
IO_000026 : Inapplicable
IO_000027 : Inapplicable
IO_000045 : Inapplicable
IO_000046 : Inapplicable
IO_000047 : Inapplicable
IO_000033 : Pass
IO_000034 : Inapplicable
IO_000042 : Inapplicable
Pin/Rules : LED[7]
IO_000001 : Pass
IO_000002 : Inapplicable
IO_000003 : Pass
IO_000004 : Inapplicable
IO_000005 : Inapplicable
IO_000006 : Pass
IO_000007 : Pass
IO_000008 : Inapplicable
IO_000009 : Pass
IO_000010 : Pass
IO_000011 : Inapplicable
IO_000012 : Inapplicable
IO_000013 : Inapplicable
IO_000014 : Inapplicable
IO_000015 : Inapplicable
IO_000018 : Inapplicable
IO_000019 : Inapplicable
IO_000020 : Inapplicable
IO_000021 : Inapplicable
IO_000022 : Inapplicable
IO_000023 : Inapplicable
IO_000024 : Inapplicable
IO_000026 : Inapplicable
IO_000027 : Inapplicable
IO_000045 : Inapplicable
IO_000046 : Inapplicable
IO_000047 : Inapplicable
IO_000033 : Pass
IO_000034 : Inapplicable
IO_000042 : Inapplicable
Pin/Rules : CLOCK_50
IO_000001 : Pass
IO_000002 : Inapplicable
IO_000003 : Pass
IO_000004 : Inapplicable
IO_000005 : Inapplicable
IO_000006 : Pass
IO_000007 : Pass
IO_000008 : Inapplicable
IO_000009 : Pass
IO_000010 : Pass
IO_000011 : Inapplicable
IO_000012 : Inapplicable
IO_000013 : Inapplicable
IO_000014 : Inapplicable
IO_000015 : Pass
IO_000018 : Inapplicable
IO_000019 : Inapplicable
IO_000020 : Pass
IO_000021 : Inapplicable
IO_000022 : Inapplicable
IO_000023 : Inapplicable
IO_000024 : Inapplicable
IO_000026 : Inapplicable
IO_000027 : Inapplicable
IO_000045 : Inapplicable
IO_000046 : Inapplicable
IO_000047 : Inapplicable
IO_000033 : Pass
IO_000034 : Inapplicable
IO_000042 : Inapplicable
+--------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------+
; Fitter Device Options ;
+------------------------------------------------------------------+--------------------------+
; Option ; Setting ;
+------------------------------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Active Serial ;
; Error detection CRC ; Off ;
; Enable open drain on CRC_ERROR pin ; Off ;
; Enable input tri-state on active configuration pins in user mode ; Off ;
; Configuration Voltage Level ; Auto ;
; Force Configuration Voltage Level ; Off ;
; nCEO ; As output driving ground ;
; Data[0] ; As input tri-stated ;
; Data[1]/ASDO ; As input tri-stated ;
; Data[7..2] ; Unreserved ;
; FLASH_nCE/nCSO ; As input tri-stated ;
; Other Active Parallel pins ; Unreserved ;
; DCLK ; As output driving ground ;
; Base pin-out file on sameframe device ; Off ;
+------------------------------------------------------------------+--------------------------+
+------------------------------------+
; Operating Settings and Conditions ;
+---------------------------+--------+
; Setting ; Value ;
+---------------------------+--------+
; Nominal Core Voltage ; 1.20 V ;
; Low Junction Temperature ; 0 °C ;
; High Junction Temperature ; 85 °C ;
+---------------------------+--------+
+-----------------+
; Fitter Messages ;
+-----------------+
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (119006): Selected device EP4CE22F17C6 for design "spectrum"
Info (21077): Core supply voltage is 1.2V
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info (176445): Device EP4CE10F17C6 is compatible
Info (176445): Device EP4CE6F17C6 is compatible
Info (176445): Device EP4CE15F17C6 is compatible
Info (169124): Fitter converted 5 user pins into dedicated programming pins
Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1
Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2
Info (169125): Pin ~ALTERA_DCLK~ is reserved at location H1
Info (169125): Pin ~ALTERA_DATA0~ is reserved at location H2
Info (169125): Pin ~ALTERA_nCEO~ is reserved at location F16
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
2022-03-30 12:47:42 +03:00
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
2022-03-30 11:53:01 +03:00
Critical Warning (332012): Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332144): No user constrained base clocks found in the design
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
Info (176353): Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18
Info (176233): Starting register packing
Info (176235): Finished register packing
Extra Info (176219): No registers were packed into other blocks
Warning (15705): Ignored locations or region assignments to the following nodes
Warning (15706): Node "ADC_CS_N" is assigned to location or region, but does not exist in design
Warning (15706): Node "ADC_SADDR" is assigned to location or region, but does not exist in design
Warning (15706): Node "ADC_SCLK" is assigned to location or region, but does not exist in design
Warning (15706): Node "ADC_SDAT" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_BA[0]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_BA[1]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_DQM[0]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_DQM[1]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design
Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design
Warning (15706): Node "EPCS_ASDO" is assigned to location or region, but does not exist in design
Warning (15706): Node "EPCS_DATA0" is assigned to location or region, but does not exist in design
Warning (15706): Node "EPCS_DCLK" is assigned to location or region, but does not exist in design
Warning (15706): Node "EPCS_NCSO" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[0]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[10]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[11]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[12]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[13]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[14]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[15]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[16]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[17]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[18]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[19]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[1]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[20]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[21]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[22]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[23]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[24]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[25]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[26]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[27]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[28]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[29]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[2]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[30]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[31]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[32]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[33]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[3]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[4]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[5]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[6]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[7]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[8]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0[9]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0_IN[0]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_0_IN[1]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[0]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[10]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[11]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[12]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[13]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[14]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[15]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[16]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[17]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[18]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[19]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[1]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[20]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[21]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[22]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[23]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[24]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[25]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[26]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[27]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[28]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[29]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[2]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[30]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[31]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[32]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[33]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[3]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[4]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[5]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[6]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[7]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[8]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1[9]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1_IN[0]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_1_IN[1]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_2[0]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_2[10]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_2[11]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_2[12]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_2[1]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_2[2]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_2[3]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_2[4]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_2[5]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_2[6]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_2[7]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_2[8]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_2[9]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_2_IN[0]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_2_IN[1]" is assigned to location or region, but does not exist in design
Warning (15706): Node "GPIO_2_IN[2]" is assigned to location or region, but does not exist in design
Warning (15706): Node "G_SENSOR_CS_N" is assigned to location or region, but does not exist in design
Warning (15706): Node "G_SENSOR_INT" is assigned to location or region, but does not exist in design
Warning (15706): Node "I2C_SCLK" is assigned to location or region, but does not exist in design
Warning (15706): Node "I2C_SDAT" is assigned to location or region, but does not exist in design
Warning (15706): Node "KEY[0]" is assigned to location or region, but does not exist in design
Warning (15706): Node "KEY[1]" is assigned to location or region, but does not exist in design
Warning (15706): Node "SW[0]" is assigned to location or region, but does not exist in design
Warning (15706): Node "SW[1]" is assigned to location or region, but does not exist in design
Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design
Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 0% of the available device resources
Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34
2022-03-30 12:47:42 +03:00
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
2022-03-30 11:53:01 +03:00
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info (170201): Optimizations that may affect the design's routability were skipped
2022-03-30 12:47:42 +03:00
Info (11888): Total time spent on timing analysis during the Fitter is 0.16 seconds.
2022-03-30 11:53:01 +03:00
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
Warning (169177): 1 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
Info (169178): Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8
Info (144001): Generated suppressed messages file /home/benny/work/fpga/projects/output_files/spectrum.fit.smsg
Info: Quartus II 32-bit Fitter was successful. 0 errors, 152 warnings
2022-03-30 12:47:42 +03:00
Info: Peak virtual memory: 600 megabytes
Info: Processing ended: Wed Mar 30 12:38:34 2022
Info: Elapsed time: 00:00:05
2022-03-30 11:53:01 +03:00
Info: Total CPU time (on all processors): 00:00:06
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in /home/benny/work/fpga/projects/output_files/spectrum.fit.smsg.
