2022-03-30 11:53:01 +03:00
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|spectrum
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2022-03-30 12:47:42 +03:00
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CLOCK_50 => CLOCK_50.IN1
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LED[0] <= rom0:rom.q
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LED[1] <= rom0:rom.q
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LED[2] <= rom0:rom.q
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LED[3] <= rom0:rom.q
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LED[4] <= rom0:rom.q
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LED[5] <= rom0:rom.q
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LED[6] <= rom0:rom.q
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LED[7] <= rom0:rom.q
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|spectrum|rom0:rom
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address[0] => address[0].IN1
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address[1] => address[1].IN1
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address[2] => address[2].IN1
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clock => clock.IN1
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q[0] <= altsyncram:altsyncram_component.q_a
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q[1] <= altsyncram:altsyncram_component.q_a
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q[2] <= altsyncram:altsyncram_component.q_a
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q[3] <= altsyncram:altsyncram_component.q_a
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q[4] <= altsyncram:altsyncram_component.q_a
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q[5] <= altsyncram:altsyncram_component.q_a
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q[6] <= altsyncram:altsyncram_component.q_a
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q[7] <= altsyncram:altsyncram_component.q_a
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|spectrum|rom0:rom|altsyncram:altsyncram_component
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wren_a => ~NO_FANOUT~
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rden_a => ~NO_FANOUT~
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wren_b => ~NO_FANOUT~
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rden_b => ~NO_FANOUT~
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data_a[0] => ~NO_FANOUT~
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data_a[1] => ~NO_FANOUT~
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data_a[2] => ~NO_FANOUT~
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data_a[3] => ~NO_FANOUT~
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data_a[4] => ~NO_FANOUT~
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data_a[5] => ~NO_FANOUT~
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data_a[6] => ~NO_FANOUT~
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data_a[7] => ~NO_FANOUT~
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data_b[0] => ~NO_FANOUT~
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address_a[0] => altsyncram_ro91:auto_generated.address_a[0]
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address_a[1] => altsyncram_ro91:auto_generated.address_a[1]
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address_a[2] => altsyncram_ro91:auto_generated.address_a[2]
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address_b[0] => ~NO_FANOUT~
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addressstall_a => ~NO_FANOUT~
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addressstall_b => ~NO_FANOUT~
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clock0 => altsyncram_ro91:auto_generated.clock0
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clock1 => ~NO_FANOUT~
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clocken0 => ~NO_FANOUT~
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clocken1 => ~NO_FANOUT~
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clocken2 => ~NO_FANOUT~
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clocken3 => ~NO_FANOUT~
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aclr0 => ~NO_FANOUT~
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aclr1 => ~NO_FANOUT~
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byteena_a[0] => ~NO_FANOUT~
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byteena_b[0] => ~NO_FANOUT~
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q_a[0] <= altsyncram_ro91:auto_generated.q_a[0]
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q_a[1] <= altsyncram_ro91:auto_generated.q_a[1]
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q_a[2] <= altsyncram_ro91:auto_generated.q_a[2]
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q_a[3] <= altsyncram_ro91:auto_generated.q_a[3]
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q_a[4] <= altsyncram_ro91:auto_generated.q_a[4]
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q_a[5] <= altsyncram_ro91:auto_generated.q_a[5]
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q_a[6] <= altsyncram_ro91:auto_generated.q_a[6]
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q_a[7] <= altsyncram_ro91:auto_generated.q_a[7]
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q_b[0] <= <GND>
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eccstatus[0] <= <GND>
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eccstatus[1] <= <GND>
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eccstatus[2] <= <GND>
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|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated
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address_a[0] => ram_block1a0.PORTAADDR
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address_a[0] => ram_block1a1.PORTAADDR
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address_a[0] => ram_block1a2.PORTAADDR
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address_a[0] => ram_block1a3.PORTAADDR
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address_a[0] => ram_block1a4.PORTAADDR
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address_a[0] => ram_block1a5.PORTAADDR
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address_a[0] => ram_block1a6.PORTAADDR
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address_a[0] => ram_block1a7.PORTAADDR
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address_a[1] => ram_block1a0.PORTAADDR1
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address_a[1] => ram_block1a1.PORTAADDR1
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address_a[1] => ram_block1a2.PORTAADDR1
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address_a[1] => ram_block1a3.PORTAADDR1
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address_a[1] => ram_block1a4.PORTAADDR1
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address_a[1] => ram_block1a5.PORTAADDR1
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address_a[1] => ram_block1a6.PORTAADDR1
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address_a[1] => ram_block1a7.PORTAADDR1
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address_a[2] => ram_block1a0.PORTAADDR2
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address_a[2] => ram_block1a1.PORTAADDR2
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address_a[2] => ram_block1a2.PORTAADDR2
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address_a[2] => ram_block1a3.PORTAADDR2
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address_a[2] => ram_block1a4.PORTAADDR2
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address_a[2] => ram_block1a5.PORTAADDR2
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address_a[2] => ram_block1a6.PORTAADDR2
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address_a[2] => ram_block1a7.PORTAADDR2
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clock0 => ram_block1a0.CLK0
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clock0 => ram_block1a1.CLK0
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clock0 => ram_block1a2.CLK0
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clock0 => ram_block1a3.CLK0
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clock0 => ram_block1a4.CLK0
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clock0 => ram_block1a5.CLK0
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clock0 => ram_block1a6.CLK0
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clock0 => ram_block1a7.CLK0
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q_a[0] <= ram_block1a0.PORTADATAOUT
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q_a[1] <= ram_block1a1.PORTADATAOUT
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q_a[2] <= ram_block1a2.PORTADATAOUT
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q_a[3] <= ram_block1a3.PORTADATAOUT
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q_a[4] <= ram_block1a4.PORTADATAOUT
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q_a[5] <= ram_block1a5.PORTADATAOUT
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q_a[6] <= ram_block1a6.PORTADATAOUT
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q_a[7] <= ram_block1a7.PORTADATAOUT
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2022-03-30 11:53:01 +03:00
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