de0-zx-spectrum/output_files/spectrum.sta.rpt

TimeQuest Timing Analyzer report for spectrum
Wed Mar 30 13:12:26 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. Clocks
  5. Slow 1200mV 85C Model Fmax Summary
  6. Timing Closure Recommendations
  7. Slow 1200mV 85C Model Setup Summary
  8. Slow 1200mV 85C Model Hold Summary
  9. Slow 1200mV 85C Model Recovery Summary
 10. Slow 1200mV 85C Model Removal Summary
 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
 12. Slow 1200mV 85C Model Setup: 'CLOCK_50'
 13. Slow 1200mV 85C Model Hold: 'CLOCK_50'
 14. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50'
 15. Clock to Output Times
 16. Minimum Clock to Output Times
 17. Slow 1200mV 85C Model Metastability Report
 18. Slow 1200mV 0C Model Fmax Summary
 19. Slow 1200mV 0C Model Setup Summary
 20. Slow 1200mV 0C Model Hold Summary
 21. Slow 1200mV 0C Model Recovery Summary
 22. Slow 1200mV 0C Model Removal Summary
 23. Slow 1200mV 0C Model Minimum Pulse Width Summary
 24. Slow 1200mV 0C Model Setup: 'CLOCK_50'
 25. Slow 1200mV 0C Model Hold: 'CLOCK_50'
 26. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
 27. Clock to Output Times
 28. Minimum Clock to Output Times
 29. Slow 1200mV 0C Model Metastability Report
 30. Fast 1200mV 0C Model Setup Summary
 31. Fast 1200mV 0C Model Hold Summary
 32. Fast 1200mV 0C Model Recovery Summary
 33. Fast 1200mV 0C Model Removal Summary
 34. Fast 1200mV 0C Model Minimum Pulse Width Summary
 35. Fast 1200mV 0C Model Setup: 'CLOCK_50'
 36. Fast 1200mV 0C Model Hold: 'CLOCK_50'
 37. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
 38. Clock to Output Times
 39. Minimum Clock to Output Times
 40. Fast 1200mV 0C Model Metastability Report
 41. Multicorner Timing Analysis Summary
 42. Clock to Output Times
 43. Minimum Clock to Output Times
 44. Board Trace Model Assignments
 45. Input Transition Times
 46. Signal Integrity Metrics (Slow 1200mv 0c Model)
 47. Signal Integrity Metrics (Slow 1200mv 85c Model)
 48. Signal Integrity Metrics (Fast 1200mv 0c Model)
 49. Setup Transfers
 50. Hold Transfers
 51. Report TCCS
 52. Report RSKM
 53. Unconstrained Paths
 54. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                       ;
+--------------------+----------------------------------------------------+
; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name      ; spectrum                                           ;
; Device Family      ; Cyclone IV E                                       ;
; Device Name        ; EP4CE22F17C6                                       ;
; Timing Models      ; Final                                              ;
; Delay Model        ; Combined                                           ;
; Rise/Fall Delays   ; Enabled                                            ;
+--------------------+----------------------------------------------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 12     ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+--------------------------------------------------------------------------------+
; Clocks                                                                         ;
+--------------------------------------------------------------------------------+
Clock Name  : CLOCK_50
Type        : Base
Period      : 1.000
Frequency   : 1000.0 MHz
Rise        : 0.000
Fall        : 0.500
Duty Cycle  : 
Divide by   : 
Multiply by : 
Phase       : 
Offset      : 
Edge List   : 
Edge Shift  : 
Inverted    : 
Master      : 
Source      : 
Targets     : { CLOCK_50 }
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                             ;
+--------------------------------------------------------------------------------+
Fmax            : 358.68 MHz
Restricted Fmax : 250.0 MHz
Clock Name      : CLOCK_50
Note            : limit due to minimum period restriction (max I/O toggle rate)
+--------------------------------------------------------------------------------+

This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                            ;
+--------------------------------------------------------------------------------+
Clock         : CLOCK_50
Slack         : -1.788
End Point TNS : -88.557
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                             ;
+--------------------------------------------------------------------------------+
Clock         : CLOCK_50
Slack         : 0.260
End Point TNS : 0.000
+--------------------------------------------------------------------------------+



------------------------------------------
; Slow 1200mV 85C Model Recovery Summary ;
------------------------------------------
No paths to report.


-----------------------------------------
; Slow 1200mV 85C Model Removal Summary ;
-----------------------------------------
No paths to report.


+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                              ;
+--------------------------------------------------------------------------------+
Clock         : CLOCK_50
Slack         : -3.000
End Point TNS : -110.836
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'CLOCK_50'                                        ;
+--------------------------------------------------------------------------------+
Slack        : -1.788
From Node    : counter[14]
To Node      : address[13]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.720

Slack        : -1.788
From Node    : counter[14]
To Node      : address[12]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.720

Slack        : -1.788
From Node    : counter[14]
To Node      : address[11]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.720

Slack        : -1.788
From Node    : counter[14]
To Node      : address[10]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.720

Slack        : -1.788
From Node    : counter[14]
To Node      : address[9]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.720

Slack        : -1.788
From Node    : counter[14]
To Node      : address[8]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.720

Slack        : -1.788
From Node    : counter[14]
To Node      : address[7]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.720

Slack        : -1.788
From Node    : counter[14]
To Node      : address[6]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.720

Slack        : -1.788
From Node    : counter[14]
To Node      : address[5]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.720

Slack        : -1.788
From Node    : counter[14]
To Node      : address[4]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.720

Slack        : -1.788
From Node    : counter[14]
To Node      : address[3]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.720

Slack        : -1.788
From Node    : counter[14]
To Node      : address[2]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.720

Slack        : -1.788
From Node    : counter[14]
To Node      : address[1]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.720

Slack        : -1.781
From Node    : counter[13]
To Node      : address[13]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.713

Slack        : -1.781
From Node    : counter[13]
To Node      : address[12]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.713

Slack        : -1.781
From Node    : counter[13]
To Node      : address[11]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.713

Slack        : -1.781
From Node    : counter[13]
To Node      : address[10]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.713

Slack        : -1.781
From Node    : counter[13]
To Node      : address[9]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.713

Slack        : -1.781
From Node    : counter[13]
To Node      : address[8]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.713

Slack        : -1.781
From Node    : counter[13]
To Node      : address[7]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.713

Slack        : -1.781
From Node    : counter[13]
To Node      : address[6]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.713

Slack        : -1.781
From Node    : counter[13]
To Node      : address[5]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.713

Slack        : -1.781
From Node    : counter[13]
To Node      : address[4]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.713

Slack        : -1.781
From Node    : counter[13]
To Node      : address[3]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.713

Slack        : -1.781
From Node    : counter[13]
To Node      : address[2]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.713

Slack        : -1.781
From Node    : counter[13]
To Node      : address[1]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.713

Slack        : -1.756
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.616

Slack        : -1.756
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.616

Slack        : -1.756
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.616

Slack        : -1.756
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.616

Slack        : -1.756
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.616

Slack        : -1.756
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.616

Slack        : -1.756
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.616

Slack        : -1.756
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.616

Slack        : -1.756
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.616

Slack        : -1.756
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.616

Slack        : -1.756
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.616

Slack        : -1.756
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.616

Slack        : -1.756
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.616

Slack        : -1.756
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.616

Slack        : -1.756
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.616

Slack        : -1.756
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.616

Slack        : -1.705
From Node    : counter[6]
To Node      : address[13]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.637

Slack        : -1.705
From Node    : counter[6]
To Node      : address[12]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.637

Slack        : -1.705
From Node    : counter[6]
To Node      : address[11]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.637

Slack        : -1.705
From Node    : counter[6]
To Node      : address[10]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.637

Slack        : -1.705
From Node    : counter[6]
To Node      : address[9]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.637

Slack        : -1.705
From Node    : counter[6]
To Node      : address[8]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.637

Slack        : -1.705
From Node    : counter[6]
To Node      : address[7]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.637

Slack        : -1.705
From Node    : counter[6]
To Node      : address[6]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.637

Slack        : -1.705
From Node    : counter[6]
To Node      : address[5]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.637

Slack        : -1.705
From Node    : counter[6]
To Node      : address[4]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.637

Slack        : -1.705
From Node    : counter[6]
To Node      : address[3]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.637

Slack        : -1.705
From Node    : counter[6]
To Node      : address[2]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.637

Slack        : -1.705
From Node    : counter[6]
To Node      : address[1]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.637

Slack        : -1.698
From Node    : counter[7]
To Node      : address[13]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.630

Slack        : -1.698
From Node    : counter[7]
To Node      : address[12]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.630

Slack        : -1.698
From Node    : counter[7]
To Node      : address[11]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.630

Slack        : -1.698
From Node    : counter[7]
To Node      : address[10]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.630

Slack        : -1.698
From Node    : counter[7]
To Node      : address[9]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.630

Slack        : -1.698
From Node    : counter[7]
To Node      : address[8]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.630

Slack        : -1.698
From Node    : counter[7]
To Node      : address[7]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.630

Slack        : -1.698
From Node    : counter[7]
To Node      : address[6]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.630

Slack        : -1.698
From Node    : counter[7]
To Node      : address[5]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.630

Slack        : -1.698
From Node    : counter[7]
To Node      : address[4]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.630

Slack        : -1.698
From Node    : counter[7]
To Node      : address[3]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.630

Slack        : -1.698
From Node    : counter[7]
To Node      : address[2]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.630

Slack        : -1.698
From Node    : counter[7]
To Node      : address[1]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.630

Slack        : -1.691
From Node    : counter[1]
To Node      : address[13]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.623

Slack        : -1.691
From Node    : counter[1]
To Node      : address[12]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.623

Slack        : -1.691
From Node    : counter[1]
To Node      : address[11]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.623

Slack        : -1.691
From Node    : counter[1]
To Node      : address[10]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.623

Slack        : -1.691
From Node    : counter[1]
To Node      : address[9]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.623

Slack        : -1.691
From Node    : counter[1]
To Node      : address[8]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.623

Slack        : -1.691
From Node    : counter[1]
To Node      : address[7]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.623

Slack        : -1.691
From Node    : counter[1]
To Node      : address[6]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.623

Slack        : -1.691
From Node    : counter[1]
To Node      : address[5]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.623

Slack        : -1.691
From Node    : counter[1]
To Node      : address[4]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.623

Slack        : -1.691
From Node    : counter[1]
To Node      : address[3]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.623

Slack        : -1.691
From Node    : counter[1]
To Node      : address[2]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.623

Slack        : -1.691
From Node    : counter[1]
To Node      : address[1]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.623

Slack        : -1.684
From Node    : counter[0]
To Node      : address[13]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.616

Slack        : -1.684
From Node    : counter[0]
To Node      : address[12]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.616

Slack        : -1.684
From Node    : counter[0]
To Node      : address[11]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.616

Slack        : -1.684
From Node    : counter[0]
To Node      : address[10]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.616

Slack        : -1.684
From Node    : counter[0]
To Node      : address[9]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.616

Slack        : -1.684
From Node    : counter[0]
To Node      : address[8]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.616

Slack        : -1.684
From Node    : counter[0]
To Node      : address[7]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.616

Slack        : -1.684
From Node    : counter[0]
To Node      : address[6]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.616

Slack        : -1.684
From Node    : counter[0]
To Node      : address[5]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.616

Slack        : -1.684
From Node    : counter[0]
To Node      : address[4]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.616

Slack        : -1.684
From Node    : counter[0]
To Node      : address[3]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.616

Slack        : -1.684
From Node    : counter[0]
To Node      : address[2]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.616

Slack        : -1.684
From Node    : counter[0]
To Node      : address[1]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.616

Slack        : -1.673
From Node    : counter[5]
To Node      : address[13]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.605

Slack        : -1.673
From Node    : counter[5]
To Node      : address[12]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.605

Slack        : -1.673
From Node    : counter[5]
To Node      : address[11]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.605

Slack        : -1.673
From Node    : counter[5]
To Node      : address[10]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.605

Slack        : -1.673
From Node    : counter[5]
To Node      : address[9]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.605

Slack        : -1.673
From Node    : counter[5]
To Node      : address[8]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.063
Data Delay   : 2.605
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'CLOCK_50'                                         ;
+--------------------------------------------------------------------------------+
Slack        : 0.260
From Node    : address[1]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.377
Data Delay   : 0.824

Slack        : 0.260
From Node    : address[1]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.377
Data Delay   : 0.824

Slack        : 0.267
From Node    : address[4]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.377
Data Delay   : 0.831

Slack        : 0.319
From Node    : address[2]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.377
Data Delay   : 0.883

Slack        : 0.339
From Node    : address[5]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.377
Data Delay   : 0.903

Slack        : 0.344
From Node    : address[0]
To Node      : address[0]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.076
Data Delay   : 0.577

Slack        : 0.345
From Node    : address[7]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.377
Data Delay   : 0.909

Slack        : 0.346
From Node    : address[11]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.377
Data Delay   : 0.910

Slack        : 0.355
From Node    : address[12]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.377
Data Delay   : 0.919

Slack        : 0.360
From Node    : address[8]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.377
Data Delay   : 0.924

Slack        : 0.361
From Node    : counter[0]
To Node      : counter[0]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.062
Data Delay   : 0.580

Slack        : 0.364
From Node    : address[3]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.377
Data Delay   : 0.928

Slack        : 0.365
From Node    : address[6]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.377
Data Delay   : 0.929

Slack        : 0.373
From Node    : address[9]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.377
Data Delay   : 0.937

Slack        : 0.375
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.062
Data Delay   : 0.594

Slack        : 0.376
From Node    : counter[21]
To Node      : counter[21]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.077
Data Delay   : 0.610

Slack        : 0.408
From Node    : address[13]
To Node      : address[13]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.063
Data Delay   : 0.628

Slack        : 0.484
From Node    : counter[19]
To Node      : counter[20]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.428
Data Delay   : 1.069

Slack        : 0.486
From Node    : counter[19]
To Node      : counter[21]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.428
Data Delay   : 1.071

Slack        : 0.526
From Node    : address[4]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.377
Data Delay   : 1.090

Slack        : 0.537
From Node    : address[7]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.385
Data Delay   : 1.109

Slack        : 0.545
From Node    : address[4]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.393
Data Delay   : 1.125

Slack        : 0.546
From Node    : address[11]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.385
Data Delay   : 1.118

Slack        : 0.552
From Node    : address[4]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.377
Data Delay   : 1.116

Slack        : 0.552
From Node    : address[1]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.393
Data Delay   : 1.132

Slack        : 0.556
From Node    : address[12]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.385
Data Delay   : 1.128

Slack        : 0.556
From Node    : counter[14]
To Node      : counter[14]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.062
Data Delay   : 0.775

Slack        : 0.556
From Node    : counter[10]
To Node      : counter[10]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.062
Data Delay   : 0.775

Slack        : 0.556
From Node    : counter[8]
To Node      : counter[8]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.062
Data Delay   : 0.775

Slack        : 0.557
From Node    : counter[12]
To Node      : counter[12]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.062
Data Delay   : 0.776

Slack        : 0.557
From Node    : counter[6]
To Node      : counter[6]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.062
Data Delay   : 0.776

Slack        : 0.558
From Node    : counter[16]
To Node      : counter[16]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.062
Data Delay   : 0.777

Slack        : 0.558
From Node    : counter[20]
To Node      : counter[20]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.077
Data Delay   : 0.792

Slack        : 0.559
From Node    : counter[17]
To Node      : counter[17]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.062
Data Delay   : 0.778

Slack        : 0.559
From Node    : counter[4]
To Node      : counter[4]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.062
Data Delay   : 0.778

Slack        : 0.560
From Node    : counter[13]
To Node      : counter[13]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.062
Data Delay   : 0.779

Slack        : 0.560
From Node    : counter[9]
To Node      : counter[9]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.062
Data Delay   : 0.779

Slack        : 0.560
From Node    : counter[2]
To Node      : counter[2]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.062
Data Delay   : 0.779

Slack        : 0.561
From Node    : counter[18]
To Node      : counter[18]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.062
Data Delay   : 0.780

Slack        : 0.561
From Node    : counter[7]
To Node      : counter[7]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.062
Data Delay   : 0.780

Slack        : 0.561
From Node    : counter[3]
To Node      : counter[3]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.062
Data Delay   : 0.780

Slack        : 0.562
From Node    : counter[15]
To Node      : counter[15]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.062
Data Delay   : 0.781

Slack        : 0.563
From Node    : address[4]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.385
Data Delay   : 1.135

Slack        : 0.563
From Node    : counter[19]
To Node      : counter[19]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.062
Data Delay   : 0.782

Slack        : 0.567
From Node    : address[10]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.385
Data Delay   : 1.139

Slack        : 0.568
From Node    : address[4]
To Node      : address[4]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.063
Data Delay   : 0.788

Slack        : 0.569
From Node    : address[4]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.393
Data Delay   : 1.149

Slack        : 0.569
From Node    : address[12]
To Node      : address[12]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.063
Data Delay   : 0.789

Slack        : 0.569
From Node    : address[6]
To Node      : address[6]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.063
Data Delay   : 0.789

Slack        : 0.569
From Node    : address[2]
To Node      : address[2]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.063
Data Delay   : 0.789

Slack        : 0.570
From Node    : address[7]
To Node      : address[7]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.063
Data Delay   : 0.790

Slack        : 0.571
From Node    : address[10]
To Node      : address[10]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.063
Data Delay   : 0.791

Slack        : 0.571
From Node    : counter[0]
To Node      : counter[1]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.062
Data Delay   : 0.790

Slack        : 0.572
From Node    : address[8]
To Node      : address[8]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.063
Data Delay   : 0.792

Slack        : 0.573
From Node    : address[5]
To Node      : address[5]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.063
Data Delay   : 0.793

Slack        : 0.573
From Node    : counter[1]
To Node      : counter[1]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.062
Data Delay   : 0.792

Slack        : 0.574
From Node    : address[13]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.062
Data Delay   : 0.793

Slack        : 0.574
From Node    : address[3]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.385
Data Delay   : 1.146

Slack        : 0.574
From Node    : address[1]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.377
Data Delay   : 1.138

Slack        : 0.574
From Node    : address[11]
To Node      : address[11]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.063
Data Delay   : 0.794

Slack        : 0.574
From Node    : address[9]
To Node      : address[9]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.063
Data Delay   : 0.794

Slack        : 0.574
From Node    : counter[5]
To Node      : counter[5]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.062
Data Delay   : 0.793

Slack        : 0.579
From Node    : address[1]
To Node      : address[1]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.063
Data Delay   : 0.799

Slack        : 0.579
From Node    : counter[18]
To Node      : counter[20]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.428
Data Delay   : 1.164

Slack        : 0.581
From Node    : counter[18]
To Node      : counter[21]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.428
Data Delay   : 1.166

Slack        : 0.582
From Node    : address[6]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.385
Data Delay   : 1.154

Slack        : 0.584
From Node    : address[9]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.385
Data Delay   : 1.156

Slack        : 0.591
From Node    : address[3]
To Node      : address[3]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.063
Data Delay   : 0.811

Slack        : 0.593
From Node    : counter[17]
To Node      : counter[20]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.428
Data Delay   : 1.178

Slack        : 0.595
From Node    : counter[17]
To Node      : counter[21]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.428
Data Delay   : 1.180

Slack        : 0.600
From Node    : address[10]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.393
Data Delay   : 1.180

Slack        : 0.601
From Node    : address[5]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.377
Data Delay   : 1.165

Slack        : 0.611
From Node    : address[2]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.393
Data Delay   : 1.191

Slack        : 0.624
From Node    : address[2]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.393
Data Delay   : 1.204

Slack        : 0.628
From Node    : address[8]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.393
Data Delay   : 1.208

Slack        : 0.629
From Node    : address[8]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.393
Data Delay   : 1.209

Slack        : 0.632
From Node    : address[2]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.393
Data Delay   : 1.212

Slack        : 0.635
From Node    : address[10]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.377
Data Delay   : 1.199

Slack        : 0.636
From Node    : address[9]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.393
Data Delay   : 1.216

Slack        : 0.637
From Node    : address[10]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.377
Data Delay   : 1.201

Slack        : 0.641
From Node    : address[5]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.377
Data Delay   : 1.205

Slack        : 0.641
From Node    : address[9]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.377
Data Delay   : 1.205

Slack        : 0.642
From Node    : address[5]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.393
Data Delay   : 1.222

Slack        : 0.650
From Node    : address[3]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.377
Data Delay   : 1.214

Slack        : 0.650
From Node    : address[3]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.393
Data Delay   : 1.230

Slack        : 0.663
From Node    : address[3]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.393
Data Delay   : 1.243

Slack        : 0.672
From Node    : address[2]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.377
Data Delay   : 1.236

Slack        : 0.675
From Node    : address[9]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.393
Data Delay   : 1.255

Slack        : 0.677
From Node    : address[9]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.377
Data Delay   : 1.241

Slack        : 0.689
From Node    : counter[16]
To Node      : counter[20]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.428
Data Delay   : 1.274

Slack        : 0.691
From Node    : counter[16]
To Node      : counter[21]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.428
Data Delay   : 1.276

Slack        : 0.707
From Node    : counter[15]
To Node      : counter[20]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.428
Data Delay   : 1.292

Slack        : 0.709
From Node    : counter[15]
To Node      : counter[21]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.428
Data Delay   : 1.294

Slack        : 0.787
From Node    : address[11]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.384
Data Delay   : 1.358

Slack        : 0.790
From Node    : address[11]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.377
Data Delay   : 1.354

Slack        : 0.799
From Node    : counter[14]
To Node      : counter[20]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.428
Data Delay   : 1.384

Slack        : 0.801
From Node    : counter[14]
To Node      : counter[21]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.428
Data Delay   : 1.386

Slack        : 0.808
From Node    : address[5]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.393
Data Delay   : 1.388

Slack        : 0.808
From Node    : address[9]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.384
Data Delay   : 1.379

Slack        : 0.810
From Node    : address[1]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.393
Data Delay   : 1.390
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50'                          ;
+--------------------------------------------------------------------------------+
Slack          : -3.000
Actual Width   : 1.000
Required Width : 4.000
Type           : Port Rate
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : CLOCK_50

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[0]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[10]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[11]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[12]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[13]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[1]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[2]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[3]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[4]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[5]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[6]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[7]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[8]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[9]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[0]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[10]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[11]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[12]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[13]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[14]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[15]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[16]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[17]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[18]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[19]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[1]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[20]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[21]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[2]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[3]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[4]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[5]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[6]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[7]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[8]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[9]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0]

Slack          : -0.011
Actual Width   : 0.219
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0

Slack          : -0.011
Actual Width   : 0.219
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0

Slack          : -0.011
Actual Width   : 0.219
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0

Slack          : -0.011
Actual Width   : 0.219
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0

Slack          : -0.011
Actual Width   : 0.219
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0

Slack          : -0.011
Actual Width   : 0.219
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0

Slack          : -0.011
Actual Width   : 0.219
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0

Slack          : -0.010
Actual Width   : 0.220
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0

Slack          : -0.010
Actual Width   : 0.220
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0

Slack          : -0.010
Actual Width   : 0.220
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0

Slack          : -0.010
Actual Width   : 0.220
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0

Slack          : -0.010
Actual Width   : 0.220
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0

Slack          : -0.010
Actual Width   : 0.220
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0

Slack          : -0.010
Actual Width   : 0.220
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0

Slack          : -0.010
Actual Width   : 0.220
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0

Slack          : -0.009
Actual Width   : 0.221
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0

Slack          : -0.007
Actual Width   : 0.223
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1

Slack          : -0.007
Actual Width   : 0.223
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11

Slack          : -0.007
Actual Width   : 0.223
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13

Slack          : -0.007
Actual Width   : 0.223
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3

Slack          : -0.007
Actual Width   : 0.223
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5

Slack          : -0.007
Actual Width   : 0.223
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7

Slack          : -0.007
Actual Width   : 0.223
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9

Slack          : -0.006
Actual Width   : 0.224
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0

Slack          : -0.006
Actual Width   : 0.224
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10

Slack          : -0.006
Actual Width   : 0.224
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12

Slack          : -0.006
Actual Width   : 0.224
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14

Slack          : -0.006
Actual Width   : 0.224
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15

Slack          : -0.006
Actual Width   : 0.224
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Clock to Output Times                                                          ;
+--------------------------------------------------------------------------------+
Data Port       : LED[*]
Clock Port      : CLOCK_50
Rise            : 10.470
Fall            : 10.183
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[0]
Clock Port      : CLOCK_50
Rise            : 8.036
Fall            : 8.004
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[1]
Clock Port      : CLOCK_50
Rise            : 7.982
Fall            : 7.929
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[2]
Clock Port      : CLOCK_50
Rise            : 8.151
Fall            : 8.115
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[3]
Clock Port      : CLOCK_50
Rise            : 7.654
Fall            : 7.638
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[4]
Clock Port      : CLOCK_50
Rise            : 7.866
Fall            : 7.844
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[5]
Clock Port      : CLOCK_50
Rise            : 10.470
Fall            : 10.183
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[6]
Clock Port      : CLOCK_50
Rise            : 8.654
Fall            : 8.642
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[7]
Clock Port      : CLOCK_50
Rise            : 9.306
Fall            : 9.035
Clock Edge      : Rise
Clock Reference : CLOCK_50
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                  ;
+--------------------------------------------------------------------------------+
Data Port       : LED[*]
Clock Port      : CLOCK_50
Rise            : 6.669
Fall            : 6.608
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[0]
Clock Port      : CLOCK_50
Rise            : 7.397
Fall            : 7.346
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[1]
Clock Port      : CLOCK_50
Rise            : 7.524
Fall            : 7.491
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[2]
Clock Port      : CLOCK_50
Rise            : 7.479
Fall            : 7.390
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[3]
Clock Port      : CLOCK_50
Rise            : 6.669
Fall            : 6.608
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[4]
Clock Port      : CLOCK_50
Rise            : 7.067
Fall            : 7.031
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[5]
Clock Port      : CLOCK_50
Rise            : 9.908
Fall            : 9.604
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[6]
Clock Port      : CLOCK_50
Rise            : 7.824
Fall            : 7.751
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[7]
Clock Port      : CLOCK_50
Rise            : 8.799
Fall            : 8.511
Clock Edge      : Rise
Clock Reference : CLOCK_50
+--------------------------------------------------------------------------------+



----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                              ;
+--------------------------------------------------------------------------------+
Fmax            : 395.73 MHz
Restricted Fmax : 250.0 MHz
Clock Name      : CLOCK_50
Note            : limit due to minimum period restriction (max I/O toggle rate)
+--------------------------------------------------------------------------------+

This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                             ;
+--------------------------------------------------------------------------------+
Clock         : CLOCK_50
Slack         : -1.527
End Point TNS : -72.611
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                              ;
+--------------------------------------------------------------------------------+
Clock         : CLOCK_50
Slack         : 0.255
End Point TNS : 0.000
+--------------------------------------------------------------------------------+



-----------------------------------------
; Slow 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.


----------------------------------------
; Slow 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.


+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                               ;
+--------------------------------------------------------------------------------+
Clock         : CLOCK_50
Slack         : -3.000
End Point TNS : -110.824
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'CLOCK_50'                                         ;
+--------------------------------------------------------------------------------+
Slack        : -1.527
From Node    : counter[14]
To Node      : address[13]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.466

Slack        : -1.527
From Node    : counter[14]
To Node      : address[12]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.466

Slack        : -1.527
From Node    : counter[14]
To Node      : address[11]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.466

Slack        : -1.527
From Node    : counter[14]
To Node      : address[10]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.466

Slack        : -1.527
From Node    : counter[14]
To Node      : address[9]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.466

Slack        : -1.527
From Node    : counter[14]
To Node      : address[8]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.466

Slack        : -1.527
From Node    : counter[14]
To Node      : address[7]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.466

Slack        : -1.527
From Node    : counter[14]
To Node      : address[6]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.466

Slack        : -1.527
From Node    : counter[14]
To Node      : address[5]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.466

Slack        : -1.527
From Node    : counter[14]
To Node      : address[4]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.466

Slack        : -1.527
From Node    : counter[14]
To Node      : address[3]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.466

Slack        : -1.527
From Node    : counter[14]
To Node      : address[2]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.466

Slack        : -1.527
From Node    : counter[14]
To Node      : address[1]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.466

Slack        : -1.520
From Node    : counter[13]
To Node      : address[13]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.459

Slack        : -1.520
From Node    : counter[13]
To Node      : address[12]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.459

Slack        : -1.520
From Node    : counter[13]
To Node      : address[11]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.459

Slack        : -1.520
From Node    : counter[13]
To Node      : address[10]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.459

Slack        : -1.520
From Node    : counter[13]
To Node      : address[9]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.459

Slack        : -1.520
From Node    : counter[13]
To Node      : address[8]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.459

Slack        : -1.520
From Node    : counter[13]
To Node      : address[7]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.459

Slack        : -1.520
From Node    : counter[13]
To Node      : address[6]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.459

Slack        : -1.520
From Node    : counter[13]
To Node      : address[5]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.459

Slack        : -1.520
From Node    : counter[13]
To Node      : address[4]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.459

Slack        : -1.520
From Node    : counter[13]
To Node      : address[3]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.459

Slack        : -1.520
From Node    : counter[13]
To Node      : address[2]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.459

Slack        : -1.520
From Node    : counter[13]
To Node      : address[1]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.459

Slack        : -1.484
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.353

Slack        : -1.484
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.353

Slack        : -1.484
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.353

Slack        : -1.484
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.353

Slack        : -1.484
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.353

Slack        : -1.484
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.353

Slack        : -1.484
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.353

Slack        : -1.484
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.353

Slack        : -1.484
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.353

Slack        : -1.484
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.353

Slack        : -1.484
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.353

Slack        : -1.484
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.353

Slack        : -1.484
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.353

Slack        : -1.484
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.353

Slack        : -1.484
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.353

Slack        : -1.484
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.069
Data Delay   : 2.353

Slack        : -1.448
From Node    : counter[6]
To Node      : address[13]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.387

Slack        : -1.448
From Node    : counter[6]
To Node      : address[12]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.387

Slack        : -1.448
From Node    : counter[6]
To Node      : address[11]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.387

Slack        : -1.448
From Node    : counter[6]
To Node      : address[10]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.387

Slack        : -1.448
From Node    : counter[6]
To Node      : address[9]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.387

Slack        : -1.448
From Node    : counter[6]
To Node      : address[8]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.387

Slack        : -1.448
From Node    : counter[6]
To Node      : address[7]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.387

Slack        : -1.448
From Node    : counter[6]
To Node      : address[6]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.387

Slack        : -1.448
From Node    : counter[6]
To Node      : address[5]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.387

Slack        : -1.448
From Node    : counter[6]
To Node      : address[4]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.387

Slack        : -1.448
From Node    : counter[6]
To Node      : address[3]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.387

Slack        : -1.448
From Node    : counter[6]
To Node      : address[2]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.387

Slack        : -1.448
From Node    : counter[6]
To Node      : address[1]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.387

Slack        : -1.442
From Node    : counter[7]
To Node      : address[13]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.381

Slack        : -1.442
From Node    : counter[7]
To Node      : address[12]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.381

Slack        : -1.442
From Node    : counter[7]
To Node      : address[11]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.381

Slack        : -1.442
From Node    : counter[7]
To Node      : address[10]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.381

Slack        : -1.442
From Node    : counter[7]
To Node      : address[9]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.381

Slack        : -1.442
From Node    : counter[7]
To Node      : address[8]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.381

Slack        : -1.442
From Node    : counter[7]
To Node      : address[7]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.381

Slack        : -1.442
From Node    : counter[7]
To Node      : address[6]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.381

Slack        : -1.442
From Node    : counter[7]
To Node      : address[5]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.381

Slack        : -1.442
From Node    : counter[7]
To Node      : address[4]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.381

Slack        : -1.442
From Node    : counter[7]
To Node      : address[3]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.381

Slack        : -1.442
From Node    : counter[7]
To Node      : address[2]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.381

Slack        : -1.442
From Node    : counter[7]
To Node      : address[1]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.381

Slack        : -1.431
From Node    : counter[1]
To Node      : address[13]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.370

Slack        : -1.431
From Node    : counter[1]
To Node      : address[12]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.370

Slack        : -1.431
From Node    : counter[1]
To Node      : address[11]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.370

Slack        : -1.431
From Node    : counter[1]
To Node      : address[10]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.370

Slack        : -1.431
From Node    : counter[1]
To Node      : address[9]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.370

Slack        : -1.431
From Node    : counter[1]
To Node      : address[8]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.370

Slack        : -1.431
From Node    : counter[1]
To Node      : address[7]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.370

Slack        : -1.431
From Node    : counter[1]
To Node      : address[6]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.370

Slack        : -1.431
From Node    : counter[1]
To Node      : address[5]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.370

Slack        : -1.431
From Node    : counter[1]
To Node      : address[4]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.370

Slack        : -1.431
From Node    : counter[1]
To Node      : address[3]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.370

Slack        : -1.431
From Node    : counter[1]
To Node      : address[2]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.370

Slack        : -1.431
From Node    : counter[1]
To Node      : address[1]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.370

Slack        : -1.425
From Node    : counter[0]
To Node      : address[13]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.364

Slack        : -1.425
From Node    : counter[0]
To Node      : address[12]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.364

Slack        : -1.425
From Node    : counter[0]
To Node      : address[11]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.364

Slack        : -1.425
From Node    : counter[0]
To Node      : address[10]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.364

Slack        : -1.425
From Node    : counter[0]
To Node      : address[9]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.364

Slack        : -1.425
From Node    : counter[0]
To Node      : address[8]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.364

Slack        : -1.425
From Node    : counter[0]
To Node      : address[7]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.364

Slack        : -1.425
From Node    : counter[0]
To Node      : address[6]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.364

Slack        : -1.425
From Node    : counter[0]
To Node      : address[5]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.364

Slack        : -1.425
From Node    : counter[0]
To Node      : address[4]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.364

Slack        : -1.425
From Node    : counter[0]
To Node      : address[3]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.364

Slack        : -1.425
From Node    : counter[0]
To Node      : address[2]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.364

Slack        : -1.425
From Node    : counter[0]
To Node      : address[1]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.364

Slack        : -1.423
From Node    : counter[5]
To Node      : address[13]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.362

Slack        : -1.423
From Node    : counter[5]
To Node      : address[12]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.362

Slack        : -1.423
From Node    : counter[5]
To Node      : address[11]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.362

Slack        : -1.423
From Node    : counter[5]
To Node      : address[10]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.362

Slack        : -1.423
From Node    : counter[5]
To Node      : address[9]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.362

Slack        : -1.423
From Node    : counter[5]
To Node      : address[8]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.056
Data Delay   : 2.362
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'CLOCK_50'                                          ;
+--------------------------------------------------------------------------------+
Slack        : 0.255
From Node    : address[1]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.337
Data Delay   : 0.761

Slack        : 0.255
From Node    : address[1]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.337
Data Delay   : 0.761

Slack        : 0.261
From Node    : address[4]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.337
Data Delay   : 0.767

Slack        : 0.300
From Node    : address[0]
To Node      : address[0]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.067
Data Delay   : 0.511

Slack        : 0.312
From Node    : address[2]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.337
Data Delay   : 0.818

Slack        : 0.319
From Node    : counter[0]
To Node      : counter[0]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.056
Data Delay   : 0.519

Slack        : 0.329
From Node    : address[5]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.337
Data Delay   : 0.835

Slack        : 0.334
From Node    : address[7]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.337
Data Delay   : 0.840

Slack        : 0.335
From Node    : address[11]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.337
Data Delay   : 0.841

Slack        : 0.335
From Node    : counter[21]
To Node      : counter[21]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.068
Data Delay   : 0.547

Slack        : 0.341
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.055
Data Delay   : 0.540

Slack        : 0.344
From Node    : address[12]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.337
Data Delay   : 0.850

Slack        : 0.346
From Node    : address[8]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.337
Data Delay   : 0.852

Slack        : 0.353
From Node    : address[6]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.337
Data Delay   : 0.859

Slack        : 0.354
From Node    : address[3]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.337
Data Delay   : 0.860

Slack        : 0.357
From Node    : address[9]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.337
Data Delay   : 0.863

Slack        : 0.365
From Node    : address[13]
To Node      : address[13]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.055
Data Delay   : 0.564

Slack        : 0.425
From Node    : counter[19]
To Node      : counter[20]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.384
Data Delay   : 0.953

Slack        : 0.432
From Node    : counter[19]
To Node      : counter[21]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.384
Data Delay   : 0.960

Slack        : 0.498
From Node    : counter[10]
To Node      : counter[10]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.056
Data Delay   : 0.698

Slack        : 0.499
From Node    : address[4]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.337
Data Delay   : 1.005

Slack        : 0.499
From Node    : counter[14]
To Node      : counter[14]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.056
Data Delay   : 0.699

Slack        : 0.499
From Node    : counter[8]
To Node      : counter[8]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.056
Data Delay   : 0.699

Slack        : 0.499
From Node    : counter[6]
To Node      : counter[6]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.056
Data Delay   : 0.699

Slack        : 0.500
From Node    : counter[16]
To Node      : counter[16]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.056
Data Delay   : 0.700

Slack        : 0.500
From Node    : counter[12]
To Node      : counter[12]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.056
Data Delay   : 0.700

Slack        : 0.502
From Node    : counter[17]
To Node      : counter[17]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.056
Data Delay   : 0.702

Slack        : 0.502
From Node    : counter[13]
To Node      : counter[13]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.056
Data Delay   : 0.702

Slack        : 0.502
From Node    : counter[7]
To Node      : counter[7]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.056
Data Delay   : 0.702

Slack        : 0.502
From Node    : counter[4]
To Node      : counter[4]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.056
Data Delay   : 0.702

Slack        : 0.502
From Node    : counter[2]
To Node      : counter[2]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.056
Data Delay   : 0.702

Slack        : 0.502
From Node    : counter[20]
To Node      : counter[20]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.068
Data Delay   : 0.714

Slack        : 0.503
From Node    : counter[18]
To Node      : counter[18]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.056
Data Delay   : 0.703

Slack        : 0.503
From Node    : counter[9]
To Node      : counter[9]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.056
Data Delay   : 0.703

Slack        : 0.504
From Node    : counter[19]
To Node      : counter[19]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.056
Data Delay   : 0.704

Slack        : 0.504
From Node    : counter[15]
To Node      : counter[15]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.056
Data Delay   : 0.704

Slack        : 0.504
From Node    : counter[3]
To Node      : counter[3]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.056
Data Delay   : 0.704

Slack        : 0.509
From Node    : counter[18]
To Node      : counter[20]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.384
Data Delay   : 1.037

Slack        : 0.511
From Node    : address[4]
To Node      : address[4]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.055
Data Delay   : 0.710

Slack        : 0.512
From Node    : address[12]
To Node      : address[12]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.055
Data Delay   : 0.711

Slack        : 0.512
From Node    : address[6]
To Node      : address[6]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.055
Data Delay   : 0.711

Slack        : 0.512
From Node    : address[2]
To Node      : address[2]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.055
Data Delay   : 0.711

Slack        : 0.513
From Node    : address[7]
To Node      : address[7]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.055
Data Delay   : 0.712

Slack        : 0.513
From Node    : counter[0]
To Node      : counter[1]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.056
Data Delay   : 0.713

Slack        : 0.514
From Node    : address[7]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.343
Data Delay   : 1.026

Slack        : 0.515
From Node    : address[10]
To Node      : address[10]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.055
Data Delay   : 0.714

Slack        : 0.515
From Node    : address[8]
To Node      : address[8]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.055
Data Delay   : 0.714

Slack        : 0.515
From Node    : counter[5]
To Node      : counter[5]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.056
Data Delay   : 0.715

Slack        : 0.515
From Node    : counter[1]
To Node      : counter[1]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.056
Data Delay   : 0.715

Slack        : 0.516
From Node    : address[5]
To Node      : address[5]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.055
Data Delay   : 0.715

Slack        : 0.516
From Node    : counter[18]
To Node      : counter[21]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.384
Data Delay   : 1.044

Slack        : 0.517
From Node    : address[11]
To Node      : address[11]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.055
Data Delay   : 0.716

Slack        : 0.517
From Node    : address[9]
To Node      : address[9]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.055
Data Delay   : 0.716

Slack        : 0.518
From Node    : address[4]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.351
Data Delay   : 1.038

Slack        : 0.519
From Node    : counter[17]
To Node      : counter[20]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.384
Data Delay   : 1.047

Slack        : 0.522
From Node    : address[4]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.337
Data Delay   : 1.028

Slack        : 0.524
From Node    : address[1]
To Node      : address[1]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.055
Data Delay   : 0.723

Slack        : 0.525
From Node    : address[11]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.343
Data Delay   : 1.037

Slack        : 0.526
From Node    : counter[17]
To Node      : counter[21]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.384
Data Delay   : 1.054

Slack        : 0.527
From Node    : address[13]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.055
Data Delay   : 0.726

Slack        : 0.527
From Node    : address[1]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.351
Data Delay   : 1.047

Slack        : 0.532
From Node    : address[3]
To Node      : address[3]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.055
Data Delay   : 0.731

Slack        : 0.537
From Node    : address[4]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.351
Data Delay   : 1.057

Slack        : 0.541
From Node    : address[1]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.337
Data Delay   : 1.047

Slack        : 0.542
From Node    : address[12]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.343
Data Delay   : 1.054

Slack        : 0.544
From Node    : address[4]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.343
Data Delay   : 1.056

Slack        : 0.544
From Node    : address[10]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.343
Data Delay   : 1.056

Slack        : 0.554
From Node    : address[3]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.343
Data Delay   : 1.066

Slack        : 0.558
From Node    : address[9]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.343
Data Delay   : 1.070

Slack        : 0.559
From Node    : address[6]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.343
Data Delay   : 1.071

Slack        : 0.567
From Node    : address[5]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.337
Data Delay   : 1.073

Slack        : 0.570
From Node    : address[10]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.351
Data Delay   : 1.090

Slack        : 0.581
From Node    : address[2]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.351
Data Delay   : 1.101

Slack        : 0.592
From Node    : address[2]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.351
Data Delay   : 1.112

Slack        : 0.596
From Node    : address[8]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.351
Data Delay   : 1.116

Slack        : 0.597
From Node    : address[8]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.351
Data Delay   : 1.117

Slack        : 0.598
From Node    : address[10]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.337
Data Delay   : 1.104

Slack        : 0.601
From Node    : counter[16]
To Node      : counter[20]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.384
Data Delay   : 1.129

Slack        : 0.602
From Node    : address[2]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.351
Data Delay   : 1.122

Slack        : 0.602
From Node    : address[9]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.351
Data Delay   : 1.122

Slack        : 0.603
From Node    : address[10]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.337
Data Delay   : 1.109

Slack        : 0.607
From Node    : address[5]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.337
Data Delay   : 1.113

Slack        : 0.607
From Node    : address[9]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.337
Data Delay   : 1.113

Slack        : 0.608
From Node    : address[5]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.351
Data Delay   : 1.128

Slack        : 0.608
From Node    : counter[16]
To Node      : counter[21]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.384
Data Delay   : 1.136

Slack        : 0.615
From Node    : address[3]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.337
Data Delay   : 1.121

Slack        : 0.616
From Node    : address[3]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.351
Data Delay   : 1.136

Slack        : 0.617
From Node    : counter[15]
To Node      : counter[20]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.384
Data Delay   : 1.145

Slack        : 0.624
From Node    : counter[15]
To Node      : counter[21]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.384
Data Delay   : 1.152

Slack        : 0.628
From Node    : address[3]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.351
Data Delay   : 1.148

Slack        : 0.633
From Node    : address[2]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.337
Data Delay   : 1.139

Slack        : 0.635
From Node    : address[9]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.337
Data Delay   : 1.141

Slack        : 0.638
From Node    : address[9]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.351
Data Delay   : 1.158

Slack        : 0.696
From Node    : counter[14]
To Node      : counter[20]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.384
Data Delay   : 1.224

Slack        : 0.703
From Node    : counter[14]
To Node      : counter[21]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.384
Data Delay   : 1.231

Slack        : 0.711
From Node    : counter[13]
To Node      : counter[20]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.384
Data Delay   : 1.239

Slack        : 0.718
From Node    : counter[13]
To Node      : counter[21]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.384
Data Delay   : 1.246

Slack        : 0.743
From Node    : counter[6]
To Node      : counter[7]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.056
Data Delay   : 0.943

Slack        : 0.743
From Node    : counter[8]
To Node      : counter[9]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.056
Data Delay   : 0.943

Slack        : 0.743
From Node    : counter[14]
To Node      : counter[15]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.056
Data Delay   : 0.943
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'                           ;
+--------------------------------------------------------------------------------+
Slack          : -3.000
Actual Width   : 1.000
Required Width : 4.000
Type           : Port Rate
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : CLOCK_50

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9

Slack          : -2.174
Actual Width   : 1.000
Required Width : 3.174
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[0]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[10]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[11]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[12]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[13]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[1]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[2]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[3]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[4]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[5]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[6]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[7]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[8]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[9]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[0]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[10]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[11]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[12]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[13]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[14]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[15]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[16]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[17]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[18]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[19]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[1]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[20]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[21]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[2]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[3]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[4]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[5]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[6]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[7]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[8]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[9]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0]

Slack          : -0.011
Actual Width   : 0.219
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0

Slack          : -0.011
Actual Width   : 0.219
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0

Slack          : -0.011
Actual Width   : 0.219
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0

Slack          : -0.011
Actual Width   : 0.219
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0

Slack          : -0.010
Actual Width   : 0.220
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0

Slack          : -0.010
Actual Width   : 0.220
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0

Slack          : -0.010
Actual Width   : 0.220
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0

Slack          : -0.010
Actual Width   : 0.220
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0

Slack          : -0.010
Actual Width   : 0.220
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0

Slack          : -0.010
Actual Width   : 0.220
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0

Slack          : -0.010
Actual Width   : 0.220
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0

Slack          : -0.010
Actual Width   : 0.220
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0

Slack          : -0.009
Actual Width   : 0.221
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0

Slack          : -0.009
Actual Width   : 0.221
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0

Slack          : -0.009
Actual Width   : 0.221
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0

Slack          : -0.009
Actual Width   : 0.221
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0

Slack          : -0.007
Actual Width   : 0.223
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13

Slack          : -0.007
Actual Width   : 0.223
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5

Slack          : -0.007
Actual Width   : 0.223
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7

Slack          : -0.007
Actual Width   : 0.223
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9

Slack          : -0.006
Actual Width   : 0.224
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0

Slack          : -0.006
Actual Width   : 0.224
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10

Slack          : -0.006
Actual Width   : 0.224
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12

Slack          : -0.006
Actual Width   : 0.224
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14

Slack          : -0.006
Actual Width   : 0.224
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15

Slack          : -0.006
Actual Width   : 0.224
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4

Slack          : -0.006
Actual Width   : 0.224
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6

Slack          : -0.006
Actual Width   : 0.224
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8

Slack          : -0.005
Actual Width   : 0.225
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Clock to Output Times                                                          ;
+--------------------------------------------------------------------------------+
Data Port       : LED[*]
Clock Port      : CLOCK_50
Rise            : 9.439
Fall            : 8.980
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[0]
Clock Port      : CLOCK_50
Rise            : 7.273
Fall            : 7.194
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[1]
Clock Port      : CLOCK_50
Rise            : 7.209
Fall            : 7.095
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[2]
Clock Port      : CLOCK_50
Rise            : 7.387
Fall            : 7.257
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[3]
Clock Port      : CLOCK_50
Rise            : 6.922
Fall            : 6.837
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[4]
Clock Port      : CLOCK_50
Rise            : 7.090
Fall            : 6.963
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[5]
Clock Port      : CLOCK_50
Rise            : 9.439
Fall            : 8.980
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[6]
Clock Port      : CLOCK_50
Rise            : 7.889
Fall            : 7.717
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[7]
Clock Port      : CLOCK_50
Rise            : 8.347
Fall            : 7.950
Clock Edge      : Rise
Clock Reference : CLOCK_50
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                  ;
+--------------------------------------------------------------------------------+
Data Port       : LED[*]
Clock Port      : CLOCK_50
Rise            : 6.027
Fall            : 5.921
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[0]
Clock Port      : CLOCK_50
Rise            : 6.683
Fall            : 6.586
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[1]
Clock Port      : CLOCK_50
Rise            : 6.797
Fall            : 6.677
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[2]
Clock Port      : CLOCK_50
Rise            : 6.758
Fall            : 6.608
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[3]
Clock Port      : CLOCK_50
Rise            : 6.027
Fall            : 5.921
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[4]
Clock Port      : CLOCK_50
Rise            : 6.376
Fall            : 6.259
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[5]
Clock Port      : CLOCK_50
Rise            : 8.947
Fall            : 8.480
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[6]
Clock Port      : CLOCK_50
Rise            : 7.114
Fall            : 6.908
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[7]
Clock Port      : CLOCK_50
Rise            : 7.910
Fall            : 7.506
Clock Edge      : Rise
Clock Reference : CLOCK_50
+--------------------------------------------------------------------------------+



---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                             ;
+--------------------------------------------------------------------------------+
Clock         : CLOCK_50
Slack         : -0.529
End Point TNS : -18.538
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                              ;
+--------------------------------------------------------------------------------+
Clock         : CLOCK_50
Slack         : 0.123
End Point TNS : 0.000
+--------------------------------------------------------------------------------+



-----------------------------------------
; Fast 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.


----------------------------------------
; Fast 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.


+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                               ;
+--------------------------------------------------------------------------------+
Clock         : CLOCK_50
Slack         : -3.000
End Point TNS : -93.684
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'CLOCK_50'                                         ;
+--------------------------------------------------------------------------------+
Slack        : -0.529
From Node    : counter[14]
To Node      : address[13]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.479

Slack        : -0.529
From Node    : counter[14]
To Node      : address[12]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.479

Slack        : -0.529
From Node    : counter[14]
To Node      : address[11]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.479

Slack        : -0.529
From Node    : counter[14]
To Node      : address[10]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.479

Slack        : -0.529
From Node    : counter[14]
To Node      : address[9]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.479

Slack        : -0.529
From Node    : counter[14]
To Node      : address[8]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.479

Slack        : -0.529
From Node    : counter[14]
To Node      : address[7]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.479

Slack        : -0.529
From Node    : counter[14]
To Node      : address[6]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.479

Slack        : -0.529
From Node    : counter[14]
To Node      : address[5]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.479

Slack        : -0.529
From Node    : counter[14]
To Node      : address[4]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.479

Slack        : -0.529
From Node    : counter[14]
To Node      : address[3]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.479

Slack        : -0.529
From Node    : counter[14]
To Node      : address[2]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.479

Slack        : -0.529
From Node    : counter[14]
To Node      : address[1]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.479

Slack        : -0.529
From Node    : counter[13]
To Node      : address[13]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.479

Slack        : -0.529
From Node    : counter[13]
To Node      : address[12]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.479

Slack        : -0.529
From Node    : counter[13]
To Node      : address[11]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.479

Slack        : -0.529
From Node    : counter[13]
To Node      : address[10]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.479

Slack        : -0.529
From Node    : counter[13]
To Node      : address[9]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.479

Slack        : -0.529
From Node    : counter[13]
To Node      : address[8]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.479

Slack        : -0.529
From Node    : counter[13]
To Node      : address[7]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.479

Slack        : -0.529
From Node    : counter[13]
To Node      : address[6]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.479

Slack        : -0.529
From Node    : counter[13]
To Node      : address[5]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.479

Slack        : -0.529
From Node    : counter[13]
To Node      : address[4]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.479

Slack        : -0.529
From Node    : counter[13]
To Node      : address[3]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.479

Slack        : -0.529
From Node    : counter[13]
To Node      : address[2]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.479

Slack        : -0.529
From Node    : counter[13]
To Node      : address[1]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.479

Slack        : -0.489
From Node    : counter[6]
To Node      : address[13]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.439

Slack        : -0.489
From Node    : counter[6]
To Node      : address[12]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.439

Slack        : -0.489
From Node    : counter[6]
To Node      : address[11]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.439

Slack        : -0.489
From Node    : counter[6]
To Node      : address[10]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.439

Slack        : -0.489
From Node    : counter[6]
To Node      : address[9]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.439

Slack        : -0.489
From Node    : counter[6]
To Node      : address[8]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.439

Slack        : -0.489
From Node    : counter[6]
To Node      : address[7]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.439

Slack        : -0.489
From Node    : counter[6]
To Node      : address[6]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.439

Slack        : -0.489
From Node    : counter[6]
To Node      : address[5]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.439

Slack        : -0.489
From Node    : counter[6]
To Node      : address[4]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.439

Slack        : -0.489
From Node    : counter[6]
To Node      : address[3]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.439

Slack        : -0.489
From Node    : counter[6]
To Node      : address[2]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.439

Slack        : -0.489
From Node    : counter[6]
To Node      : address[1]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.439

Slack        : -0.489
From Node    : counter[7]
To Node      : address[13]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.439

Slack        : -0.489
From Node    : counter[7]
To Node      : address[12]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.439

Slack        : -0.489
From Node    : counter[7]
To Node      : address[11]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.439

Slack        : -0.489
From Node    : counter[7]
To Node      : address[10]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.439

Slack        : -0.489
From Node    : counter[7]
To Node      : address[9]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.439

Slack        : -0.489
From Node    : counter[7]
To Node      : address[8]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.439

Slack        : -0.489
From Node    : counter[7]
To Node      : address[7]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.439

Slack        : -0.489
From Node    : counter[7]
To Node      : address[6]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.439

Slack        : -0.489
From Node    : counter[7]
To Node      : address[5]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.439

Slack        : -0.489
From Node    : counter[7]
To Node      : address[4]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.439

Slack        : -0.489
From Node    : counter[7]
To Node      : address[3]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.439

Slack        : -0.489
From Node    : counter[7]
To Node      : address[2]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.439

Slack        : -0.489
From Node    : counter[7]
To Node      : address[1]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.439

Slack        : -0.486
From Node    : counter[1]
To Node      : address[13]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.436

Slack        : -0.486
From Node    : counter[1]
To Node      : address[12]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.436

Slack        : -0.486
From Node    : counter[1]
To Node      : address[11]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.436

Slack        : -0.486
From Node    : counter[1]
To Node      : address[10]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.436

Slack        : -0.486
From Node    : counter[1]
To Node      : address[9]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.436

Slack        : -0.486
From Node    : counter[1]
To Node      : address[8]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.436

Slack        : -0.486
From Node    : counter[1]
To Node      : address[7]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.436

Slack        : -0.486
From Node    : counter[1]
To Node      : address[6]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.436

Slack        : -0.486
From Node    : counter[1]
To Node      : address[5]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.436

Slack        : -0.486
From Node    : counter[1]
To Node      : address[4]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.436

Slack        : -0.486
From Node    : counter[1]
To Node      : address[3]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.436

Slack        : -0.486
From Node    : counter[1]
To Node      : address[2]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.436

Slack        : -0.486
From Node    : counter[1]
To Node      : address[1]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.436

Slack        : -0.486
From Node    : counter[0]
To Node      : address[13]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.436

Slack        : -0.486
From Node    : counter[0]
To Node      : address[12]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.436

Slack        : -0.486
From Node    : counter[0]
To Node      : address[11]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.436

Slack        : -0.486
From Node    : counter[0]
To Node      : address[10]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.436

Slack        : -0.486
From Node    : counter[0]
To Node      : address[9]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.436

Slack        : -0.486
From Node    : counter[0]
To Node      : address[8]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.436

Slack        : -0.486
From Node    : counter[0]
To Node      : address[7]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.436

Slack        : -0.486
From Node    : counter[0]
To Node      : address[6]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.436

Slack        : -0.486
From Node    : counter[0]
To Node      : address[5]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.436

Slack        : -0.486
From Node    : counter[0]
To Node      : address[4]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.436

Slack        : -0.486
From Node    : counter[0]
To Node      : address[3]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.436

Slack        : -0.486
From Node    : counter[0]
To Node      : address[2]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.436

Slack        : -0.486
From Node    : counter[0]
To Node      : address[1]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.436

Slack        : -0.479
From Node    : counter[5]
To Node      : address[13]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.429

Slack        : -0.479
From Node    : counter[5]
To Node      : address[12]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.429

Slack        : -0.479
From Node    : counter[5]
To Node      : address[11]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.429

Slack        : -0.479
From Node    : counter[5]
To Node      : address[10]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.429

Slack        : -0.479
From Node    : counter[5]
To Node      : address[9]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.429

Slack        : -0.479
From Node    : counter[5]
To Node      : address[8]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.429

Slack        : -0.479
From Node    : counter[5]
To Node      : address[7]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.429

Slack        : -0.479
From Node    : counter[5]
To Node      : address[6]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.429

Slack        : -0.479
From Node    : counter[5]
To Node      : address[5]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.429

Slack        : -0.479
From Node    : counter[5]
To Node      : address[4]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.429

Slack        : -0.479
From Node    : counter[5]
To Node      : address[3]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.429

Slack        : -0.479
From Node    : counter[5]
To Node      : address[2]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.429

Slack        : -0.479
From Node    : counter[5]
To Node      : address[1]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.429

Slack        : -0.446
From Node    : address[13]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : 0.122
Data Delay   : 1.577

Slack        : -0.443
From Node    : counter[11]
To Node      : address[13]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.393

Slack        : -0.443
From Node    : counter[11]
To Node      : address[12]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.393

Slack        : -0.443
From Node    : counter[11]
To Node      : address[11]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.393

Slack        : -0.443
From Node    : counter[11]
To Node      : address[10]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.393

Slack        : -0.443
From Node    : counter[11]
To Node      : address[9]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.393

Slack        : -0.443
From Node    : counter[11]
To Node      : address[8]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.393

Slack        : -0.443
From Node    : counter[11]
To Node      : address[7]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.393

Slack        : -0.443
From Node    : counter[11]
To Node      : address[6]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 1.000
Clock Skew   : -0.037
Data Delay   : 1.393
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'CLOCK_50'                                          ;
+--------------------------------------------------------------------------------+
Slack        : 0.123
From Node    : address[1]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.219
Data Delay   : 0.446

Slack        : 0.124
From Node    : address[1]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.218
Data Delay   : 0.446

Slack        : 0.128
From Node    : address[4]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.219
Data Delay   : 0.451

Slack        : 0.159
From Node    : address[2]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.219
Data Delay   : 0.482

Slack        : 0.173
From Node    : address[5]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.219
Data Delay   : 0.496

Slack        : 0.177
From Node    : address[7]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.219
Data Delay   : 0.500

Slack        : 0.177
From Node    : address[11]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.219
Data Delay   : 0.500

Slack        : 0.179
From Node    : address[0]
To Node      : address[0]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.044
Data Delay   : 0.307

Slack        : 0.180
From Node    : address[8]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.219
Data Delay   : 0.503

Slack        : 0.182
From Node    : address[12]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.219
Data Delay   : 0.505

Slack        : 0.184
From Node    : address[3]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.219
Data Delay   : 0.507

Slack        : 0.185
From Node    : address[6]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.219
Data Delay   : 0.508

Slack        : 0.188
From Node    : address[9]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.219
Data Delay   : 0.511

Slack        : 0.193
From Node    : counter[0]
To Node      : counter[0]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.037
Data Delay   : 0.314

Slack        : 0.196
From Node    : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.036
Data Delay   : 0.316

Slack        : 0.197
From Node    : counter[21]
To Node      : counter[21]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.044
Data Delay   : 0.325

Slack        : 0.217
From Node    : address[13]
To Node      : address[13]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.036
Data Delay   : 0.337

Slack        : 0.261
From Node    : counter[19]
To Node      : counter[20]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.234
Data Delay   : 0.579

Slack        : 0.264
From Node    : counter[19]
To Node      : counter[21]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.234
Data Delay   : 0.582

Slack        : 0.276
From Node    : address[7]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.223
Data Delay   : 0.603

Slack        : 0.277
From Node    : address[4]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.218
Data Delay   : 0.599

Slack        : 0.281
From Node    : address[11]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.223
Data Delay   : 0.608

Slack        : 0.288
From Node    : address[4]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.219
Data Delay   : 0.611

Slack        : 0.293
From Node    : address[10]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.223
Data Delay   : 0.620

Slack        : 0.294
From Node    : address[12]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.223
Data Delay   : 0.621

Slack        : 0.295
From Node    : counter[10]
To Node      : counter[10]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.037
Data Delay   : 0.416

Slack        : 0.296
From Node    : address[1]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.219
Data Delay   : 0.619

Slack        : 0.296
From Node    : counter[12]
To Node      : counter[12]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.037
Data Delay   : 0.417

Slack        : 0.296
From Node    : counter[8]
To Node      : counter[8]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.037
Data Delay   : 0.417

Slack        : 0.297
From Node    : address[13]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.036
Data Delay   : 0.417

Slack        : 0.297
From Node    : counter[16]
To Node      : counter[16]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.037
Data Delay   : 0.418

Slack        : 0.297
From Node    : counter[14]
To Node      : counter[14]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.037
Data Delay   : 0.418

Slack        : 0.297
From Node    : counter[9]
To Node      : counter[9]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.037
Data Delay   : 0.418

Slack        : 0.297
From Node    : counter[6]
To Node      : counter[6]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.037
Data Delay   : 0.418

Slack        : 0.297
From Node    : counter[4]
To Node      : counter[4]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.037
Data Delay   : 0.418

Slack        : 0.298
From Node    : counter[13]
To Node      : counter[13]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.037
Data Delay   : 0.419

Slack        : 0.298
From Node    : counter[3]
To Node      : counter[3]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.037
Data Delay   : 0.419

Slack        : 0.298
From Node    : counter[2]
To Node      : counter[2]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.037
Data Delay   : 0.419

Slack        : 0.299
From Node    : address[4]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.230
Data Delay   : 0.633

Slack        : 0.299
From Node    : counter[18]
To Node      : counter[18]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.037
Data Delay   : 0.420

Slack        : 0.299
From Node    : counter[17]
To Node      : counter[17]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.037
Data Delay   : 0.420

Slack        : 0.299
From Node    : counter[15]
To Node      : counter[15]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.037
Data Delay   : 0.420

Slack        : 0.299
From Node    : counter[7]
To Node      : counter[7]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.037
Data Delay   : 0.420

Slack        : 0.299
From Node    : counter[20]
To Node      : counter[20]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.044
Data Delay   : 0.427

Slack        : 0.300
From Node    : address[4]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.223
Data Delay   : 0.627

Slack        : 0.300
From Node    : counter[19]
To Node      : counter[19]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.037
Data Delay   : 0.421

Slack        : 0.301
From Node    : address[6]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.223
Data Delay   : 0.628

Slack        : 0.303
From Node    : address[9]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.223
Data Delay   : 0.630

Slack        : 0.304
From Node    : counter[1]
To Node      : counter[1]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.037
Data Delay   : 0.425

Slack        : 0.305
From Node    : address[4]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.230
Data Delay   : 0.639

Slack        : 0.305
From Node    : address[12]
To Node      : address[12]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.036
Data Delay   : 0.425

Slack        : 0.305
From Node    : address[6]
To Node      : address[6]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.036
Data Delay   : 0.425

Slack        : 0.305
From Node    : address[4]
To Node      : address[4]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.036
Data Delay   : 0.425

Slack        : 0.305
From Node    : address[2]
To Node      : address[2]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.036
Data Delay   : 0.425

Slack        : 0.305
From Node    : counter[0]
To Node      : counter[1]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.037
Data Delay   : 0.426

Slack        : 0.306
From Node    : address[1]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.229
Data Delay   : 0.639

Slack        : 0.306
From Node    : address[8]
To Node      : address[8]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.036
Data Delay   : 0.426

Slack        : 0.306
From Node    : address[7]
To Node      : address[7]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.036
Data Delay   : 0.426

Slack        : 0.306
From Node    : counter[5]
To Node      : counter[5]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.037
Data Delay   : 0.427

Slack        : 0.307
From Node    : address[3]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.223
Data Delay   : 0.634

Slack        : 0.307
From Node    : address[10]
To Node      : address[10]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.036
Data Delay   : 0.427

Slack        : 0.307
From Node    : address[9]
To Node      : address[9]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.036
Data Delay   : 0.427

Slack        : 0.307
From Node    : address[5]
To Node      : address[5]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.036
Data Delay   : 0.427

Slack        : 0.308
From Node    : address[11]
To Node      : address[11]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.036
Data Delay   : 0.428

Slack        : 0.311
From Node    : address[1]
To Node      : address[1]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.036
Data Delay   : 0.431

Slack        : 0.314
From Node    : counter[18]
To Node      : counter[20]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.234
Data Delay   : 0.632

Slack        : 0.317
From Node    : counter[18]
To Node      : counter[21]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.234
Data Delay   : 0.635

Slack        : 0.318
From Node    : address[3]
To Node      : address[3]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.036
Data Delay   : 0.438

Slack        : 0.319
From Node    : address[5]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.219
Data Delay   : 0.642

Slack        : 0.326
From Node    : counter[17]
To Node      : counter[20]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.234
Data Delay   : 0.644

Slack        : 0.327
From Node    : address[10]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.230
Data Delay   : 0.661

Slack        : 0.329
From Node    : counter[17]
To Node      : counter[21]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.234
Data Delay   : 0.647

Slack        : 0.334
From Node    : address[10]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.219
Data Delay   : 0.657

Slack        : 0.338
From Node    : address[10]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.218
Data Delay   : 0.660

Slack        : 0.340
From Node    : address[9]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.218
Data Delay   : 0.662

Slack        : 0.341
From Node    : address[3]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.219
Data Delay   : 0.664

Slack        : 0.342
From Node    : address[5]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.218
Data Delay   : 0.664

Slack        : 0.342
From Node    : address[2]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.229
Data Delay   : 0.675

Slack        : 0.344
From Node    : address[8]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.230
Data Delay   : 0.678

Slack        : 0.346
From Node    : address[2]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.230
Data Delay   : 0.680

Slack        : 0.346
From Node    : address[5]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.230
Data Delay   : 0.680

Slack        : 0.346
From Node    : address[8]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.230
Data Delay   : 0.680

Slack        : 0.348
From Node    : address[9]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.230
Data Delay   : 0.682

Slack        : 0.348
From Node    : address[2]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.230
Data Delay   : 0.682

Slack        : 0.353
From Node    : address[2]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.219
Data Delay   : 0.676

Slack        : 0.354
From Node    : address[3]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.230
Data Delay   : 0.688

Slack        : 0.355
From Node    : address[3]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.230
Data Delay   : 0.689

Slack        : 0.355
From Node    : address[9]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.219
Data Delay   : 0.678

Slack        : 0.371
From Node    : address[9]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.230
Data Delay   : 0.705

Slack        : 0.378
From Node    : counter[16]
To Node      : counter[20]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.234
Data Delay   : 0.696

Slack        : 0.381
From Node    : counter[16]
To Node      : counter[21]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.234
Data Delay   : 0.699

Slack        : 0.392
From Node    : counter[15]
To Node      : counter[20]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.234
Data Delay   : 0.710

Slack        : 0.395
From Node    : counter[15]
To Node      : counter[21]
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.234
Data Delay   : 0.713

Slack        : 0.414
From Node    : address[10]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.219
Data Delay   : 0.737

Slack        : 0.417
From Node    : address[11]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.218
Data Delay   : 0.739

Slack        : 0.417
From Node    : address[11]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.223
Data Delay   : 0.744

Slack        : 0.428
From Node    : address[9]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.223
Data Delay   : 0.755

Slack        : 0.434
From Node    : address[12]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.223
Data Delay   : 0.761

Slack        : 0.435
From Node    : address[5]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.230
Data Delay   : 0.769

Slack        : 0.437
From Node    : address[7]
To Node      : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Launch Clock : CLOCK_50
Latch Clock  : CLOCK_50
Relationship : 0.000
Clock Skew   : 0.218
Data Delay   : 0.759
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'                           ;
+--------------------------------------------------------------------------------+
Slack          : -3.000
Actual Width   : 1.000
Required Width : 4.000
Type           : Port Rate
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : CLOCK_50

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[0]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[10]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[11]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[12]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[13]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[1]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[2]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[3]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[4]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[5]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[6]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[7]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[8]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : address[9]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[0]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[10]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[11]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[12]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[13]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[14]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[15]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[16]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[17]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[18]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[19]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[1]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[20]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[21]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[2]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[3]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[4]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[5]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[6]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[7]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[8]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : counter[9]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0]

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9

Slack          : -1.000
Actual Width   : 1.000
Required Width : 2.000
Type           : Min Period
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0

Slack          : -0.291
Actual Width   : -0.061
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0

Slack          : -0.291
Actual Width   : -0.061
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0

Slack          : -0.291
Actual Width   : -0.061
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0

Slack          : -0.291
Actual Width   : -0.061
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0

Slack          : -0.291
Actual Width   : -0.061
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0

Slack          : -0.291
Actual Width   : -0.061
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0

Slack          : -0.291
Actual Width   : -0.061
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0

Slack          : -0.291
Actual Width   : -0.061
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0

Slack          : -0.291
Actual Width   : -0.061
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0

Slack          : -0.291
Actual Width   : -0.061
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0

Slack          : -0.291
Actual Width   : -0.061
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0

Slack          : -0.291
Actual Width   : -0.061
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0

Slack          : -0.291
Actual Width   : -0.061
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0

Slack          : -0.291
Actual Width   : -0.061
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0

Slack          : -0.290
Actual Width   : -0.060
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0

Slack          : -0.290
Actual Width   : -0.060
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1

Slack          : -0.290
Actual Width   : -0.060
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10

Slack          : -0.290
Actual Width   : -0.060
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11

Slack          : -0.290
Actual Width   : -0.060
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12

Slack          : -0.290
Actual Width   : -0.060
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13

Slack          : -0.290
Actual Width   : -0.060
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14

Slack          : -0.290
Actual Width   : -0.060
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15

Slack          : -0.290
Actual Width   : -0.060
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2

Slack          : -0.290
Actual Width   : -0.060
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3

Slack          : -0.290
Actual Width   : -0.060
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4

Slack          : -0.290
Actual Width   : -0.060
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0

Slack          : -0.290
Actual Width   : -0.060
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6

Slack          : -0.290
Actual Width   : -0.060
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7

Slack          : -0.290
Actual Width   : -0.060
Required Width : 0.230
Type           : Low Pulse Width
Clock          : CLOCK_50
Clock Edge     : Rise
Target         : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Clock to Output Times                                                          ;
+--------------------------------------------------------------------------------+
Data Port       : LED[*]
Clock Port      : CLOCK_50
Rise            : 6.420
Fall            : 6.381
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[0]
Clock Port      : CLOCK_50
Rise            : 4.683
Fall            : 4.845
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[1]
Clock Port      : CLOCK_50
Rise            : 4.677
Fall            : 4.744
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[2]
Clock Port      : CLOCK_50
Rise            : 4.731
Fall            : 4.868
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[3]
Clock Port      : CLOCK_50
Rise            : 4.431
Fall            : 4.553
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[4]
Clock Port      : CLOCK_50
Rise            : 4.571
Fall            : 4.688
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[5]
Clock Port      : CLOCK_50
Rise            : 6.420
Fall            : 6.381
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[6]
Clock Port      : CLOCK_50
Rise            : 5.002
Fall            : 5.185
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[7]
Clock Port      : CLOCK_50
Rise            : 5.766
Fall            : 5.661
Clock Edge      : Rise
Clock Reference : CLOCK_50
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                  ;
+--------------------------------------------------------------------------------+
Data Port       : LED[*]
Clock Port      : CLOCK_50
Rise            : 3.865
Fall            : 3.891
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[0]
Clock Port      : CLOCK_50
Rise            : 4.313
Fall            : 4.443
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[1]
Clock Port      : CLOCK_50
Rise            : 4.345
Fall            : 4.444
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[2]
Clock Port      : CLOCK_50
Rise            : 4.324
Fall            : 4.427
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[3]
Clock Port      : CLOCK_50
Rise            : 3.865
Fall            : 3.891
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[4]
Clock Port      : CLOCK_50
Rise            : 4.100
Fall            : 4.147
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[5]
Clock Port      : CLOCK_50
Rise            : 6.088
Fall            : 5.971
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[6]
Clock Port      : CLOCK_50
Rise            : 4.510
Fall            : 4.644
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[7]
Clock Port      : CLOCK_50
Rise            : 5.471
Fall            : 5.290
Clock Edge      : Rise
Clock Reference : CLOCK_50
+--------------------------------------------------------------------------------+



---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+--------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                            ;
+--------------------------------------------------------------------------------+
Clock               : Worst-case Slack
Setup               : -1.788
Hold                : 0.123
Recovery            : N/A
Removal             : N/A
Minimum Pulse Width : -3.000

Clock               :  CLOCK_50
Setup               : -1.788
Hold                : 0.123
Recovery            : N/A
Removal             : N/A
Minimum Pulse Width : -3.000

Clock               : Design-wide TNS
Setup               : -88.557
Hold                : 0.0
Recovery            : 0.0
Removal             : 0.0
Minimum Pulse Width : -110.836

Clock               :  CLOCK_50
Setup               : -88.557
Hold                : 0.000
Recovery            : N/A
Removal             : N/A
Minimum Pulse Width : -110.836
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Clock to Output Times                                                          ;
+--------------------------------------------------------------------------------+
Data Port       : LED[*]
Clock Port      : CLOCK_50
Rise            : 10.470
Fall            : 10.183
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[0]
Clock Port      : CLOCK_50
Rise            : 8.036
Fall            : 8.004
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[1]
Clock Port      : CLOCK_50
Rise            : 7.982
Fall            : 7.929
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[2]
Clock Port      : CLOCK_50
Rise            : 8.151
Fall            : 8.115
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[3]
Clock Port      : CLOCK_50
Rise            : 7.654
Fall            : 7.638
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[4]
Clock Port      : CLOCK_50
Rise            : 7.866
Fall            : 7.844
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[5]
Clock Port      : CLOCK_50
Rise            : 10.470
Fall            : 10.183
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[6]
Clock Port      : CLOCK_50
Rise            : 8.654
Fall            : 8.642
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[7]
Clock Port      : CLOCK_50
Rise            : 9.306
Fall            : 9.035
Clock Edge      : Rise
Clock Reference : CLOCK_50
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                  ;
+--------------------------------------------------------------------------------+
Data Port       : LED[*]
Clock Port      : CLOCK_50
Rise            : 3.865
Fall            : 3.891
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[0]
Clock Port      : CLOCK_50
Rise            : 4.313
Fall            : 4.443
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[1]
Clock Port      : CLOCK_50
Rise            : 4.345
Fall            : 4.444
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[2]
Clock Port      : CLOCK_50
Rise            : 4.324
Fall            : 4.427
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[3]
Clock Port      : CLOCK_50
Rise            : 3.865
Fall            : 3.891
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[4]
Clock Port      : CLOCK_50
Rise            : 4.100
Fall            : 4.147
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[5]
Clock Port      : CLOCK_50
Rise            : 6.088
Fall            : 5.971
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[6]
Clock Port      : CLOCK_50
Rise            : 4.510
Fall            : 4.644
Clock Edge      : Rise
Clock Reference : CLOCK_50

Data Port       :  LED[7]
Clock Port      : CLOCK_50
Rise            : 5.471
Fall            : 5.290
Clock Edge      : Rise
Clock Reference : CLOCK_50
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                  ;
+--------------------------------------------------------------------------------+
Pin                     : LED[0]
I/O Standard            : 3.3-V LVTTL
Near Tline Length       : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R           : short
Near Differential R     : -
Near Pull-up R          : open
Near Pull-down R        : open
Near C                  : open
Far Tline Length        : 0 in
Far Tline L per Length  : 0 H/in
Far Tline C per Length  : 0 F/in
Far Series R            : short
Far Pull-up R           : open
Far Pull-down R         : open
Far C                   : open
Termination Voltage     : 0 V
Far Differential R      : -
EBD File Name           : n/a
EBD Signal Name         : n/a
EBD Far-end             : n/a

Pin                     : LED[1]
I/O Standard            : 3.3-V LVTTL
Near Tline Length       : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R           : short
Near Differential R     : -
Near Pull-up R          : open
Near Pull-down R        : open
Near C                  : open
Far Tline Length        : 0 in
Far Tline L per Length  : 0 H/in
Far Tline C per Length  : 0 F/in
Far Series R            : short
Far Pull-up R           : open
Far Pull-down R         : open
Far C                   : open
Termination Voltage     : 0 V
Far Differential R      : -
EBD File Name           : n/a
EBD Signal Name         : n/a
EBD Far-end             : n/a

Pin                     : LED[2]
I/O Standard            : 3.3-V LVTTL
Near Tline Length       : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R           : short
Near Differential R     : -
Near Pull-up R          : open
Near Pull-down R        : open
Near C                  : open
Far Tline Length        : 0 in
Far Tline L per Length  : 0 H/in
Far Tline C per Length  : 0 F/in
Far Series R            : short
Far Pull-up R           : open
Far Pull-down R         : open
Far C                   : open
Termination Voltage     : 0 V
Far Differential R      : -
EBD File Name           : n/a
EBD Signal Name         : n/a
EBD Far-end             : n/a

Pin                     : LED[3]
I/O Standard            : 3.3-V LVTTL
Near Tline Length       : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R           : short
Near Differential R     : -
Near Pull-up R          : open
Near Pull-down R        : open
Near C                  : open
Far Tline Length        : 0 in
Far Tline L per Length  : 0 H/in
Far Tline C per Length  : 0 F/in
Far Series R            : short
Far Pull-up R           : open
Far Pull-down R         : open
Far C                   : open
Termination Voltage     : 0 V
Far Differential R      : -
EBD File Name           : n/a
EBD Signal Name         : n/a
EBD Far-end             : n/a

Pin                     : LED[4]
I/O Standard            : 3.3-V LVTTL
Near Tline Length       : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R           : short
Near Differential R     : -
Near Pull-up R          : open
Near Pull-down R        : open
Near C                  : open
Far Tline Length        : 0 in
Far Tline L per Length  : 0 H/in
Far Tline C per Length  : 0 F/in
Far Series R            : short
Far Pull-up R           : open
Far Pull-down R         : open
Far C                   : open
Termination Voltage     : 0 V
Far Differential R      : -
EBD File Name           : n/a
EBD Signal Name         : n/a
EBD Far-end             : n/a

Pin                     : LED[5]
I/O Standard            : 3.3-V LVTTL
Near Tline Length       : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R           : short
Near Differential R     : -
Near Pull-up R          : open
Near Pull-down R        : open
Near C                  : open
Far Tline Length        : 0 in
Far Tline L per Length  : 0 H/in
Far Tline C per Length  : 0 F/in
Far Series R            : short
Far Pull-up R           : open
Far Pull-down R         : open
Far C                   : open
Termination Voltage     : 0 V
Far Differential R      : -
EBD File Name           : n/a
EBD Signal Name         : n/a
EBD Far-end             : n/a

Pin                     : LED[6]
I/O Standard            : 3.3-V LVTTL
Near Tline Length       : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R           : short
Near Differential R     : -
Near Pull-up R          : open
Near Pull-down R        : open
Near C                  : open
Far Tline Length        : 0 in
Far Tline L per Length  : 0 H/in
Far Tline C per Length  : 0 F/in
Far Series R            : short
Far Pull-up R           : open
Far Pull-down R         : open
Far C                   : open
Termination Voltage     : 0 V
Far Differential R      : -
EBD File Name           : n/a
EBD Signal Name         : n/a
EBD Far-end             : n/a

Pin                     : LED[7]
I/O Standard            : 3.3-V LVTTL
Near Tline Length       : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R           : short
Near Differential R     : -
Near Pull-up R          : open
Near Pull-down R        : open
Near C                  : open
Far Tline Length        : 0 in
Far Tline L per Length  : 0 H/in
Far Tline C per Length  : 0 F/in
Far Series R            : short
Far Pull-up R           : open
Far Pull-down R         : open
Far C                   : open
Termination Voltage     : 0 V
Far Differential R      : -
EBD File Name           : n/a
EBD Signal Name         : n/a
EBD Far-end             : n/a

Pin                     : ~ALTERA_DCLK~
I/O Standard            : 3.3-V LVTTL
Near Tline Length       : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R           : short
Near Differential R     : -
Near Pull-up R          : open
Near Pull-down R        : open
Near C                  : open
Far Tline Length        : 0 in
Far Tline L per Length  : 0 H/in
Far Tline C per Length  : 0 F/in
Far Series R            : short
Far Pull-up R           : open
Far Pull-down R         : open
Far C                   : open
Termination Voltage     : 0 V
Far Differential R      : -
EBD File Name           : n/a
EBD Signal Name         : n/a
EBD Far-end             : n/a

Pin                     : ~ALTERA_nCEO~
I/O Standard            : 2.5 V
Near Tline Length       : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R           : short
Near Differential R     : -
Near Pull-up R          : open
Near Pull-down R        : open
Near C                  : open
Far Tline Length        : 0 in
Far Tline L per Length  : 0 H/in
Far Tline C per Length  : 0 F/in
Far Series R            : short
Far Pull-up R           : open
Far Pull-down R         : open
Far C                   : open
Termination Voltage     : 0 V
Far Differential R      : -
EBD File Name           : n/a
EBD Signal Name         : n/a
EBD Far-end             : n/a
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Input Transition Times                                                         ;
+--------------------------------------------------------------------------------+
Pin             : CLOCK_50
I/O Standard    : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps

Pin             : ~ALTERA_ASDO_DATA1~
I/O Standard    : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps

Pin             : ~ALTERA_FLASH_nCE_nCSO~
I/O Standard    : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps

Pin             : ~ALTERA_DATA0~
I/O Standard    : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 0c Model)                                ;
+--------------------------------------------------------------------------------+
Pin                                  : LED[0]
I/O Standard                         : 3.3-V LVTTL
Board Delay on Rise                  : 0 s
Board Delay on Fall                  : 0 s
Steady State Voh at FPGA Pin         : 3.08 V
Steady State Vol at FPGA Pin         : 2.24e-08 V
Voh Max at FPGA Pin                  : 3.14 V
Vol Min at FPGA Pin                  : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin          : 5.06e-10 s
90-10 Fall Time at FPGA Pin          : 4.37e-10 s
Monotonic Rise at FPGA Pin           : No
Monotonic Fall at FPGA Pin           : No
Steady State Voh at Far-end          : 3.08 V
Steady State Vol at Far-end          : 2.24e-08 V
Voh Max at Far-end                   : 3.14 V
Vol Min at Far-end                   : -0.115 V
Ringback Voltage on Rise at Far-end  : 0.31 V
Ringback Voltage on Fall at Far-end  : 0.241 V
10-90 Rise Time at Far-end           : 5.06e-10 s
90-10 Fall Time at Far-end           : 4.37e-10 s
Monotonic Rise at Far-end            : No
Monotonic Fall at Far-end            : No

Pin                                  : LED[1]
I/O Standard                         : 3.3-V LVTTL
Board Delay on Rise                  : 0 s
Board Delay on Fall                  : 0 s
Steady State Voh at FPGA Pin         : 3.08 V
Steady State Vol at FPGA Pin         : 2.24e-08 V
Voh Max at FPGA Pin                  : 3.14 V
Vol Min at FPGA Pin                  : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin          : 5.06e-10 s
90-10 Fall Time at FPGA Pin          : 4.37e-10 s
Monotonic Rise at FPGA Pin           : No
Monotonic Fall at FPGA Pin           : No
Steady State Voh at Far-end          : 3.08 V
Steady State Vol at Far-end          : 2.24e-08 V
Voh Max at Far-end                   : 3.14 V
Vol Min at Far-end                   : -0.115 V
Ringback Voltage on Rise at Far-end  : 0.31 V
Ringback Voltage on Fall at Far-end  : 0.241 V
10-90 Rise Time at Far-end           : 5.06e-10 s
90-10 Fall Time at Far-end           : 4.37e-10 s
Monotonic Rise at Far-end            : No
Monotonic Fall at Far-end            : No

Pin                                  : LED[2]
I/O Standard                         : 3.3-V LVTTL
Board Delay on Rise                  : 0 s
Board Delay on Fall                  : 0 s
Steady State Voh at FPGA Pin         : 3.08 V
Steady State Vol at FPGA Pin         : 2.24e-08 V
Voh Max at FPGA Pin                  : 3.14 V
Vol Min at FPGA Pin                  : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin          : 5.06e-10 s
90-10 Fall Time at FPGA Pin          : 4.37e-10 s
Monotonic Rise at FPGA Pin           : No
Monotonic Fall at FPGA Pin           : No
Steady State Voh at Far-end          : 3.08 V
Steady State Vol at Far-end          : 2.24e-08 V
Voh Max at Far-end                   : 3.14 V
Vol Min at Far-end                   : -0.115 V
Ringback Voltage on Rise at Far-end  : 0.31 V
Ringback Voltage on Fall at Far-end  : 0.241 V
10-90 Rise Time at Far-end           : 5.06e-10 s
90-10 Fall Time at Far-end           : 4.37e-10 s
Monotonic Rise at Far-end            : No
Monotonic Fall at Far-end            : No

Pin                                  : LED[3]
I/O Standard                         : 3.3-V LVTTL
Board Delay on Rise                  : 0 s
Board Delay on Fall                  : 0 s
Steady State Voh at FPGA Pin         : 3.08 V
Steady State Vol at FPGA Pin         : 2.24e-08 V
Voh Max at FPGA Pin                  : 3.14 V
Vol Min at FPGA Pin                  : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin          : 5.06e-10 s
90-10 Fall Time at FPGA Pin          : 4.37e-10 s
Monotonic Rise at FPGA Pin           : No
Monotonic Fall at FPGA Pin           : No
Steady State Voh at Far-end          : 3.08 V
Steady State Vol at Far-end          : 2.24e-08 V
Voh Max at Far-end                   : 3.14 V
Vol Min at Far-end                   : -0.115 V
Ringback Voltage on Rise at Far-end  : 0.31 V
Ringback Voltage on Fall at Far-end  : 0.241 V
10-90 Rise Time at Far-end           : 5.06e-10 s
90-10 Fall Time at Far-end           : 4.37e-10 s
Monotonic Rise at Far-end            : No
Monotonic Fall at Far-end            : No

Pin                                  : LED[4]
I/O Standard                         : 3.3-V LVTTL
Board Delay on Rise                  : 0 s
Board Delay on Fall                  : 0 s
Steady State Voh at FPGA Pin         : 3.08 V
Steady State Vol at FPGA Pin         : 1.54e-08 V
Voh Max at FPGA Pin                  : 3.14 V
Vol Min at FPGA Pin                  : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin          : 7.35e-10 s
90-10 Fall Time at FPGA Pin          : 6.36e-10 s
Monotonic Rise at FPGA Pin           : No
Monotonic Fall at FPGA Pin           : No
Steady State Voh at Far-end          : 3.08 V
Steady State Vol at Far-end          : 1.54e-08 V
Voh Max at Far-end                   : 3.14 V
Vol Min at Far-end                   : -0.074 V
Ringback Voltage on Rise at Far-end  : 0.343 V
Ringback Voltage on Fall at Far-end  : 0.194 V
10-90 Rise Time at Far-end           : 7.35e-10 s
90-10 Fall Time at Far-end           : 6.36e-10 s
Monotonic Rise at Far-end            : No
Monotonic Fall at Far-end            : No

Pin                                  : LED[5]
I/O Standard                         : 3.3-V LVTTL
Board Delay on Rise                  : 0 s
Board Delay on Fall                  : 0 s
Steady State Voh at FPGA Pin         : 3.08 V
Steady State Vol at FPGA Pin         : 1.54e-08 V
Voh Max at FPGA Pin                  : 3.09 V
Vol Min at FPGA Pin                  : -0.0119 V
Ringback Voltage on Rise at FPGA Pin : 0.277 V
Ringback Voltage on Fall at FPGA Pin : 0.297 V
10-90 Rise Time at FPGA Pin          : 4.54e-09 s
90-10 Fall Time at FPGA Pin          : 3.32e-09 s
Monotonic Rise at FPGA Pin           : No
Monotonic Fall at FPGA Pin           : No
Steady State Voh at Far-end          : 3.08 V
Steady State Vol at Far-end          : 1.54e-08 V
Voh Max at Far-end                   : 3.09 V
Vol Min at Far-end                   : -0.0119 V
Ringback Voltage on Rise at Far-end  : 0.277 V
Ringback Voltage on Fall at Far-end  : 0.297 V
10-90 Rise Time at Far-end           : 4.54e-09 s
90-10 Fall Time at Far-end           : 3.32e-09 s
Monotonic Rise at Far-end            : No
Monotonic Fall at Far-end            : No

Pin                                  : LED[6]
I/O Standard                         : 3.3-V LVTTL
Board Delay on Rise                  : 0 s
Board Delay on Fall                  : 0 s
Steady State Voh at FPGA Pin         : 3.08 V
Steady State Vol at FPGA Pin         : 1.54e-08 V
Voh Max at FPGA Pin                  : 3.16 V
Vol Min at FPGA Pin                  : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin          : 4.82e-10 s
90-10 Fall Time at FPGA Pin          : 4.27e-10 s
Monotonic Rise at FPGA Pin           : Yes
Monotonic Fall at FPGA Pin           : No
Steady State Voh at Far-end          : 3.08 V
Steady State Vol at Far-end          : 1.54e-08 V
Voh Max at Far-end                   : 3.16 V
Vol Min at Far-end                   : -0.11 V
Ringback Voltage on Rise at Far-end  : 0.302 V
Ringback Voltage on Fall at Far-end  : 0.22 V
10-90 Rise Time at Far-end           : 4.82e-10 s
90-10 Fall Time at Far-end           : 4.27e-10 s
Monotonic Rise at Far-end            : Yes
Monotonic Fall at Far-end            : No

Pin                                  : LED[7]
I/O Standard                         : 3.3-V LVTTL
Board Delay on Rise                  : 0 s
Board Delay on Fall                  : 0 s
Steady State Voh at FPGA Pin         : 3.08 V
Steady State Vol at FPGA Pin         : 1.54e-08 V
Voh Max at FPGA Pin                  : 3.09 V
Vol Min at FPGA Pin                  : -0.0119 V
Ringback Voltage on Rise at FPGA Pin : 0.277 V
Ringback Voltage on Fall at FPGA Pin : 0.297 V
10-90 Rise Time at FPGA Pin          : 4.54e-09 s
90-10 Fall Time at FPGA Pin          : 3.32e-09 s
Monotonic Rise at FPGA Pin           : No
Monotonic Fall at FPGA Pin           : No
Steady State Voh at Far-end          : 3.08 V
Steady State Vol at Far-end          : 1.54e-08 V
Voh Max at Far-end                   : 3.09 V
Vol Min at Far-end                   : -0.0119 V
Ringback Voltage on Rise at Far-end  : 0.277 V
Ringback Voltage on Fall at Far-end  : 0.297 V
10-90 Rise Time at Far-end           : 4.54e-09 s
90-10 Fall Time at Far-end           : 3.32e-09 s
Monotonic Rise at Far-end            : No
Monotonic Fall at Far-end            : No

Pin                                  : ~ALTERA_DCLK~
I/O Standard                         : 3.3-V LVTTL
Board Delay on Rise                  : 0 s
Board Delay on Fall                  : 0 s
Steady State Voh at FPGA Pin         : 3.08 V
Steady State Vol at FPGA Pin         : 8.05e-09 V
Voh Max at FPGA Pin                  : 3.21 V
Vol Min at FPGA Pin                  : -0.181 V
Ringback Voltage on Rise at FPGA Pin : 0.16 V
Ringback Voltage on Fall at FPGA Pin : 0.253 V
10-90 Rise Time at FPGA Pin          : 2.77e-10 s
90-10 Fall Time at FPGA Pin          : 2.32e-10 s
Monotonic Rise at FPGA Pin           : No
Monotonic Fall at FPGA Pin           : Yes
Steady State Voh at Far-end          : 3.08 V
Steady State Vol at Far-end          : 8.05e-09 V
Voh Max at Far-end                   : 3.21 V
Vol Min at Far-end                   : -0.181 V
Ringback Voltage on Rise at Far-end  : 0.16 V
Ringback Voltage on Fall at Far-end  : 0.253 V
10-90 Rise Time at Far-end           : 2.77e-10 s
90-10 Fall Time at Far-end           : 2.32e-10 s
Monotonic Rise at Far-end            : No
Monotonic Fall at Far-end            : Yes

Pin                                  : ~ALTERA_nCEO~
I/O Standard                         : 2.5 V
Board Delay on Rise                  : 0 s
Board Delay on Fall                  : 0 s
Steady State Voh at FPGA Pin         : 2.32 V
Steady State Vol at FPGA Pin         : 5.61e-09 V
Voh Max at FPGA Pin                  : 2.38 V
Vol Min at FPGA Pin                  : -0.00274 V
Ringback Voltage on Rise at FPGA Pin : 0.141 V
Ringback Voltage on Fall at FPGA Pin : 0.006 V
10-90 Rise Time at FPGA Pin          : 4.7e-10 s
90-10 Fall Time at FPGA Pin          : 6.02e-10 s
Monotonic Rise at FPGA Pin           : Yes
Monotonic Fall at FPGA Pin           : Yes
Steady State Voh at Far-end          : 2.32 V
Steady State Vol at Far-end          : 5.61e-09 V
Voh Max at Far-end                   : 2.38 V
Vol Min at Far-end                   : -0.00274 V
Ringback Voltage on Rise at Far-end  : 0.141 V
Ringback Voltage on Fall at Far-end  : 0.006 V
10-90 Rise Time at Far-end           : 4.7e-10 s
90-10 Fall Time at Far-end           : 6.02e-10 s
Monotonic Rise at Far-end            : Yes
Monotonic Fall at Far-end            : Yes
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 85c Model)                               ;
+--------------------------------------------------------------------------------+
Pin                                  : LED[0]
I/O Standard                         : 3.3-V LVTTL
Board Delay on Rise                  : 0 s
Board Delay on Fall                  : 0 s
Steady State Voh at FPGA Pin         : 3.08 V
Steady State Vol at FPGA Pin         : 2.99e-06 V
Voh Max at FPGA Pin                  : 3.11 V
Vol Min at FPGA Pin                  : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin          : 6.66e-10 s
90-10 Fall Time at FPGA Pin          : 6.19e-10 s
Monotonic Rise at FPGA Pin           : Yes
Monotonic Fall at FPGA Pin           : No
Steady State Voh at Far-end          : 3.08 V
Steady State Vol at Far-end          : 2.99e-06 V
Voh Max at Far-end                   : 3.11 V
Vol Min at Far-end                   : -0.0717 V
Ringback Voltage on Rise at Far-end  : 0.209 V
Ringback Voltage on Fall at Far-end  : 0.168 V
10-90 Rise Time at Far-end           : 6.66e-10 s
90-10 Fall Time at Far-end           : 6.19e-10 s
Monotonic Rise at Far-end            : Yes
Monotonic Fall at Far-end            : No

Pin                                  : LED[1]
I/O Standard                         : 3.3-V LVTTL
Board Delay on Rise                  : 0 s
Board Delay on Fall                  : 0 s
Steady State Voh at FPGA Pin         : 3.08 V
Steady State Vol at FPGA Pin         : 2.99e-06 V
Voh Max at FPGA Pin                  : 3.11 V
Vol Min at FPGA Pin                  : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin          : 6.66e-10 s
90-10 Fall Time at FPGA Pin          : 6.19e-10 s
Monotonic Rise at FPGA Pin           : Yes
Monotonic Fall at FPGA Pin           : No
Steady State Voh at Far-end          : 3.08 V
Steady State Vol at Far-end          : 2.99e-06 V
Voh Max at Far-end                   : 3.11 V
Vol Min at Far-end                   : -0.0717 V
Ringback Voltage on Rise at Far-end  : 0.209 V
Ringback Voltage on Fall at Far-end  : 0.168 V
10-90 Rise Time at Far-end           : 6.66e-10 s
90-10 Fall Time at Far-end           : 6.19e-10 s
Monotonic Rise at Far-end            : Yes
Monotonic Fall at Far-end            : No

Pin                                  : LED[2]
I/O Standard                         : 3.3-V LVTTL
Board Delay on Rise                  : 0 s
Board Delay on Fall                  : 0 s
Steady State Voh at FPGA Pin         : 3.08 V
Steady State Vol at FPGA Pin         : 2.99e-06 V
Voh Max at FPGA Pin                  : 3.11 V
Vol Min at FPGA Pin                  : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin          : 6.66e-10 s
90-10 Fall Time at FPGA Pin          : 6.19e-10 s
Monotonic Rise at FPGA Pin           : Yes
Monotonic Fall at FPGA Pin           : No
Steady State Voh at Far-end          : 3.08 V
Steady State Vol at Far-end          : 2.99e-06 V
Voh Max at Far-end                   : 3.11 V
Vol Min at Far-end                   : -0.0717 V
Ringback Voltage on Rise at Far-end  : 0.209 V
Ringback Voltage on Fall at Far-end  : 0.168 V
10-90 Rise Time at Far-end           : 6.66e-10 s
90-10 Fall Time at Far-end           : 6.19e-10 s
Monotonic Rise at Far-end            : Yes
Monotonic Fall at Far-end            : No

Pin                                  : LED[3]
I/O Standard                         : 3.3-V LVTTL
Board Delay on Rise                  : 0 s
Board Delay on Fall                  : 0 s
Steady State Voh at FPGA Pin         : 3.08 V
Steady State Vol at FPGA Pin         : 2.99e-06 V
Voh Max at FPGA Pin                  : 3.11 V
Vol Min at FPGA Pin                  : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin          : 6.66e-10 s
90-10 Fall Time at FPGA Pin          : 6.19e-10 s
Monotonic Rise at FPGA Pin           : Yes
Monotonic Fall at FPGA Pin           : No
Steady State Voh at Far-end          : 3.08 V
Steady State Vol at Far-end          : 2.99e-06 V
Voh Max at Far-end                   : 3.11 V
Vol Min at Far-end                   : -0.0717 V
Ringback Voltage on Rise at Far-end  : 0.209 V
Ringback Voltage on Fall at Far-end  : 0.168 V
10-90 Rise Time at Far-end           : 6.66e-10 s
90-10 Fall Time at Far-end           : 6.19e-10 s
Monotonic Rise at Far-end            : Yes
Monotonic Fall at Far-end            : No

Pin                                  : LED[4]
I/O Standard                         : 3.3-V LVTTL
Board Delay on Rise                  : 0 s
Board Delay on Fall                  : 0 s
Steady State Voh at FPGA Pin         : 3.08 V
Steady State Vol at FPGA Pin         : 2e-06 V
Voh Max at FPGA Pin                  : 3.12 V
Vol Min at FPGA Pin                  : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin          : 9.17e-10 s
90-10 Fall Time at FPGA Pin          : 8.31e-10 s
Monotonic Rise at FPGA Pin           : Yes
Monotonic Fall at FPGA Pin           : No
Steady State Voh at Far-end          : 3.08 V
Steady State Vol at Far-end          : 2e-06 V
Voh Max at Far-end                   : 3.12 V
Vol Min at Far-end                   : -0.0547 V
Ringback Voltage on Rise at Far-end  : 0.276 V
Ringback Voltage on Fall at Far-end  : 0.181 V
10-90 Rise Time at Far-end           : 9.17e-10 s
90-10 Fall Time at Far-end           : 8.31e-10 s
Monotonic Rise at Far-end            : Yes
Monotonic Fall at Far-end            : No

Pin                                  : LED[5]
I/O Standard                         : 3.3-V LVTTL
Board Delay on Rise                  : 0 s
Board Delay on Fall                  : 0 s
Steady State Voh at FPGA Pin         : 3.08 V
Steady State Vol at FPGA Pin         : 2e-06 V
Voh Max at FPGA Pin                  : 3.08 V
Vol Min at FPGA Pin                  : -0.00666 V
Ringback Voltage on Rise at FPGA Pin : 0.298 V
Ringback Voltage on Fall at FPGA Pin : 0.277 V
10-90 Rise Time at FPGA Pin          : 5.29e-09 s
90-10 Fall Time at FPGA Pin          : 4.2e-09 s
Monotonic Rise at FPGA Pin           : Yes
Monotonic Fall at FPGA Pin           : No
Steady State Voh at Far-end          : 3.08 V
Steady State Vol at Far-end          : 2e-06 V
Voh Max at Far-end                   : 3.08 V
Vol Min at Far-end                   : -0.00666 V
Ringback Voltage on Rise at Far-end  : 0.298 V
Ringback Voltage on Fall at Far-end  : 0.277 V
10-90 Rise Time at Far-end           : 5.29e-09 s
90-10 Fall Time at Far-end           : 4.2e-09 s
Monotonic Rise at Far-end            : Yes
Monotonic Fall at Far-end            : No

Pin                                  : LED[6]
I/O Standard                         : 3.3-V LVTTL
Board Delay on Rise                  : 0 s
Board Delay on Fall                  : 0 s
Steady State Voh at FPGA Pin         : 3.08 V
Steady State Vol at FPGA Pin         : 2e-06 V
Voh Max at FPGA Pin                  : 3.13 V
Vol Min at FPGA Pin                  : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin          : 6.54e-10 s
90-10 Fall Time at FPGA Pin          : 5e-10 s
Monotonic Rise at FPGA Pin           : No
Monotonic Fall at FPGA Pin           : No
Steady State Voh at Far-end          : 3.08 V
Steady State Vol at Far-end          : 2e-06 V
Voh Max at Far-end                   : 3.13 V
Vol Min at Far-end                   : -0.0781 V
Ringback Voltage on Rise at Far-end  : 0.202 V
Ringback Voltage on Fall at Far-end  : 0.359 V
10-90 Rise Time at Far-end           : 6.54e-10 s
90-10 Fall Time at Far-end           : 5e-10 s
Monotonic Rise at Far-end            : No
Monotonic Fall at Far-end            : No

Pin                                  : LED[7]
I/O Standard                         : 3.3-V LVTTL
Board Delay on Rise                  : 0 s
Board Delay on Fall                  : 0 s
Steady State Voh at FPGA Pin         : 3.08 V
Steady State Vol at FPGA Pin         : 2e-06 V
Voh Max at FPGA Pin                  : 3.08 V
Vol Min at FPGA Pin                  : -0.00666 V
Ringback Voltage on Rise at FPGA Pin : 0.298 V
Ringback Voltage on Fall at FPGA Pin : 0.277 V
10-90 Rise Time at FPGA Pin          : 5.29e-09 s
90-10 Fall Time at FPGA Pin          : 4.2e-09 s
Monotonic Rise at FPGA Pin           : Yes
Monotonic Fall at FPGA Pin           : No
Steady State Voh at Far-end          : 3.08 V
Steady State Vol at Far-end          : 2e-06 V
Voh Max at Far-end                   : 3.08 V
Vol Min at Far-end                   : -0.00666 V
Ringback Voltage on Rise at Far-end  : 0.298 V
Ringback Voltage on Fall at Far-end  : 0.277 V
10-90 Rise Time at Far-end           : 5.29e-09 s
90-10 Fall Time at Far-end           : 4.2e-09 s
Monotonic Rise at Far-end            : Yes
Monotonic Fall at Far-end            : No

Pin                                  : ~ALTERA_DCLK~
I/O Standard                         : 3.3-V LVTTL
Board Delay on Rise                  : 0 s
Board Delay on Fall                  : 0 s
Steady State Voh at FPGA Pin         : 3.08 V
Steady State Vol at FPGA Pin         : 1.02e-06 V
Voh Max at FPGA Pin                  : 3.14 V
Vol Min at FPGA Pin                  : -0.124 V
Ringback Voltage on Rise at FPGA Pin : 0.134 V
Ringback Voltage on Fall at FPGA Pin : 0.323 V
10-90 Rise Time at FPGA Pin          : 3.02e-10 s
90-10 Fall Time at FPGA Pin          : 2.85e-10 s
Monotonic Rise at FPGA Pin           : Yes
Monotonic Fall at FPGA Pin           : No
Steady State Voh at Far-end          : 3.08 V
Steady State Vol at Far-end          : 1.02e-06 V
Voh Max at Far-end                   : 3.14 V
Vol Min at Far-end                   : -0.124 V
Ringback Voltage on Rise at Far-end  : 0.134 V
Ringback Voltage on Fall at Far-end  : 0.323 V
10-90 Rise Time at Far-end           : 3.02e-10 s
90-10 Fall Time at Far-end           : 2.85e-10 s
Monotonic Rise at Far-end            : Yes
Monotonic Fall at Far-end            : No

Pin                                  : ~ALTERA_nCEO~
I/O Standard                         : 2.5 V
Board Delay on Rise                  : 0 s
Board Delay on Fall                  : 0 s
Steady State Voh at FPGA Pin         : 2.32 V
Steady State Vol at FPGA Pin         : 9.45e-07 V
Voh Max at FPGA Pin                  : 2.35 V
Vol Min at FPGA Pin                  : -0.00643 V
Ringback Voltage on Rise at FPGA Pin : 0.081 V
Ringback Voltage on Fall at FPGA Pin : 0.031 V
10-90 Rise Time at FPGA Pin          : 5.31e-10 s
90-10 Fall Time at FPGA Pin          : 7.59e-10 s
Monotonic Rise at FPGA Pin           : Yes
Monotonic Fall at FPGA Pin           : Yes
Steady State Voh at Far-end          : 2.32 V
Steady State Vol at Far-end          : 9.45e-07 V
Voh Max at Far-end                   : 2.35 V
Vol Min at Far-end                   : -0.00643 V
Ringback Voltage on Rise at Far-end  : 0.081 V
Ringback Voltage on Fall at Far-end  : 0.031 V
10-90 Rise Time at Far-end           : 5.31e-10 s
90-10 Fall Time at Far-end           : 7.59e-10 s
Monotonic Rise at Far-end            : Yes
Monotonic Fall at Far-end            : Yes
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1200mv 0c Model)                                ;
+--------------------------------------------------------------------------------+
Pin                                  : LED[0]
I/O Standard                         : 3.3-V LVTTL
Board Delay on Rise                  : 0 s
Board Delay on Fall                  : 0 s
Steady State Voh at FPGA Pin         : 3.46 V
Steady State Vol at FPGA Pin         : 1.85e-07 V
Voh Max at FPGA Pin                  : 3.57 V
Vol Min at FPGA Pin                  : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin          : 4.61e-10 s
90-10 Fall Time at FPGA Pin          : 4.2e-10 s
Monotonic Rise at FPGA Pin           : No
Monotonic Fall at FPGA Pin           : No
Steady State Voh at Far-end          : 3.46 V
Steady State Vol at Far-end          : 1.85e-07 V
Voh Max at Far-end                   : 3.57 V
Vol Min at Far-end                   : -0.141 V
Ringback Voltage on Rise at Far-end  : 0.301 V
Ringback Voltage on Fall at Far-end  : 0.239 V
10-90 Rise Time at Far-end           : 4.61e-10 s
90-10 Fall Time at Far-end           : 4.2e-10 s
Monotonic Rise at Far-end            : No
Monotonic Fall at Far-end            : No

Pin                                  : LED[1]
I/O Standard                         : 3.3-V LVTTL
Board Delay on Rise                  : 0 s
Board Delay on Fall                  : 0 s
Steady State Voh at FPGA Pin         : 3.46 V
Steady State Vol at FPGA Pin         : 1.85e-07 V
Voh Max at FPGA Pin                  : 3.57 V
Vol Min at FPGA Pin                  : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin          : 4.61e-10 s
90-10 Fall Time at FPGA Pin          : 4.2e-10 s
Monotonic Rise at FPGA Pin           : No
Monotonic Fall at FPGA Pin           : No
Steady State Voh at Far-end          : 3.46 V
Steady State Vol at Far-end          : 1.85e-07 V
Voh Max at Far-end                   : 3.57 V
Vol Min at Far-end                   : -0.141 V
Ringback Voltage on Rise at Far-end  : 0.301 V
Ringback Voltage on Fall at Far-end  : 0.239 V
10-90 Rise Time at Far-end           : 4.61e-10 s
90-10 Fall Time at Far-end           : 4.2e-10 s
Monotonic Rise at Far-end            : No
Monotonic Fall at Far-end            : No

Pin                                  : LED[2]
I/O Standard                         : 3.3-V LVTTL
Board Delay on Rise                  : 0 s
Board Delay on Fall                  : 0 s
Steady State Voh at FPGA Pin         : 3.46 V
Steady State Vol at FPGA Pin         : 1.85e-07 V
Voh Max at FPGA Pin                  : 3.57 V
Vol Min at FPGA Pin                  : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin          : 4.61e-10 s
90-10 Fall Time at FPGA Pin          : 4.2e-10 s
Monotonic Rise at FPGA Pin           : No
Monotonic Fall at FPGA Pin           : No
Steady State Voh at Far-end          : 3.46 V
Steady State Vol at Far-end          : 1.85e-07 V
Voh Max at Far-end                   : 3.57 V
Vol Min at Far-end                   : -0.141 V
Ringback Voltage on Rise at Far-end  : 0.301 V
Ringback Voltage on Fall at Far-end  : 0.239 V
10-90 Rise Time at Far-end           : 4.61e-10 s
90-10 Fall Time at Far-end           : 4.2e-10 s
Monotonic Rise at Far-end            : No
Monotonic Fall at Far-end            : No

Pin                                  : LED[3]
I/O Standard                         : 3.3-V LVTTL
Board Delay on Rise                  : 0 s
Board Delay on Fall                  : 0 s
Steady State Voh at FPGA Pin         : 3.46 V
Steady State Vol at FPGA Pin         : 1.85e-07 V
Voh Max at FPGA Pin                  : 3.57 V
Vol Min at FPGA Pin                  : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin          : 4.61e-10 s
90-10 Fall Time at FPGA Pin          : 4.2e-10 s
Monotonic Rise at FPGA Pin           : No
Monotonic Fall at FPGA Pin           : No
Steady State Voh at Far-end          : 3.46 V
Steady State Vol at Far-end          : 1.85e-07 V
Voh Max at Far-end                   : 3.57 V
Vol Min at Far-end                   : -0.141 V
Ringback Voltage on Rise at Far-end  : 0.301 V
Ringback Voltage on Fall at Far-end  : 0.239 V
10-90 Rise Time at Far-end           : 4.61e-10 s
90-10 Fall Time at Far-end           : 4.2e-10 s
Monotonic Rise at Far-end            : No
Monotonic Fall at Far-end            : No

Pin                                  : LED[4]
I/O Standard                         : 3.3-V LVTTL
Board Delay on Rise                  : 0 s
Board Delay on Fall                  : 0 s
Steady State Voh at FPGA Pin         : 3.46 V
Steady State Vol at FPGA Pin         : 1.25e-07 V
Voh Max at FPGA Pin                  : 3.57 V
Vol Min at FPGA Pin                  : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin          : 6.79e-10 s
90-10 Fall Time at FPGA Pin          : 6.15e-10 s
Monotonic Rise at FPGA Pin           : No
Monotonic Fall at FPGA Pin           : No
Steady State Voh at Far-end          : 3.46 V
Steady State Vol at Far-end          : 1.25e-07 V
Voh Max at Far-end                   : 3.57 V
Vol Min at Far-end                   : -0.0855 V
Ringback Voltage on Rise at Far-end  : 0.315 V
Ringback Voltage on Fall at Far-end  : 0.175 V
10-90 Rise Time at Far-end           : 6.79e-10 s
90-10 Fall Time at Far-end           : 6.15e-10 s
Monotonic Rise at Far-end            : No
Monotonic Fall at Far-end            : No

Pin                                  : LED[5]
I/O Standard                         : 3.3-V LVTTL
Board Delay on Rise                  : 0 s
Board Delay on Fall                  : 0 s
Steady State Voh at FPGA Pin         : 3.46 V
Steady State Vol at FPGA Pin         : 1.25e-07 V
Voh Max at FPGA Pin                  : 3.48 V
Vol Min at FPGA Pin                  : -0.0162 V
Ringback Voltage on Rise at FPGA Pin : 0.354 V
Ringback Voltage on Fall at FPGA Pin : 0.317 V
10-90 Rise Time at FPGA Pin          : 3.88e-09 s
90-10 Fall Time at FPGA Pin          : 3.06e-09 s
Monotonic Rise at FPGA Pin           : No
Monotonic Fall at FPGA Pin           : No
Steady State Voh at Far-end          : 3.46 V
Steady State Vol at Far-end          : 1.25e-07 V
Voh Max at Far-end                   : 3.48 V
Vol Min at Far-end                   : -0.0162 V
Ringback Voltage on Rise at Far-end  : 0.354 V
Ringback Voltage on Fall at Far-end  : 0.317 V
10-90 Rise Time at Far-end           : 3.88e-09 s
90-10 Fall Time at Far-end           : 3.06e-09 s
Monotonic Rise at Far-end            : No
Monotonic Fall at Far-end            : No

Pin                                  : LED[6]
I/O Standard                         : 3.3-V LVTTL
Board Delay on Rise                  : 0 s
Board Delay on Fall                  : 0 s
Steady State Voh at FPGA Pin         : 3.46 V
Steady State Vol at FPGA Pin         : 1.25e-07 V
Voh Max at FPGA Pin                  : 3.6 V
Vol Min at FPGA Pin                  : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin          : 4.55e-10 s
90-10 Fall Time at FPGA Pin          : 4.11e-10 s
Monotonic Rise at FPGA Pin           : No
Monotonic Fall at FPGA Pin           : No
Steady State Voh at Far-end          : 3.46 V
Steady State Vol at Far-end          : 1.25e-07 V
Voh Max at Far-end                   : 3.6 V
Vol Min at Far-end                   : -0.127 V
Ringback Voltage on Rise at Far-end  : 0.302 V
Ringback Voltage on Fall at Far-end  : 0.21 V
10-90 Rise Time at Far-end           : 4.55e-10 s
90-10 Fall Time at Far-end           : 4.11e-10 s
Monotonic Rise at Far-end            : No
Monotonic Fall at Far-end            : No

Pin                                  : LED[7]
I/O Standard                         : 3.3-V LVTTL
Board Delay on Rise                  : 0 s
Board Delay on Fall                  : 0 s
Steady State Voh at FPGA Pin         : 3.46 V
Steady State Vol at FPGA Pin         : 1.25e-07 V
Voh Max at FPGA Pin                  : 3.48 V
Vol Min at FPGA Pin                  : -0.0162 V
Ringback Voltage on Rise at FPGA Pin : 0.354 V
Ringback Voltage on Fall at FPGA Pin : 0.317 V
10-90 Rise Time at FPGA Pin          : 3.88e-09 s
90-10 Fall Time at FPGA Pin          : 3.06e-09 s
Monotonic Rise at FPGA Pin           : No
Monotonic Fall at FPGA Pin           : No
Steady State Voh at Far-end          : 3.46 V
Steady State Vol at Far-end          : 1.25e-07 V
Voh Max at Far-end                   : 3.48 V
Vol Min at Far-end                   : -0.0162 V
Ringback Voltage on Rise at Far-end  : 0.354 V
Ringback Voltage on Fall at Far-end  : 0.317 V
10-90 Rise Time at Far-end           : 3.88e-09 s
90-10 Fall Time at Far-end           : 3.06e-09 s
Monotonic Rise at Far-end            : No
Monotonic Fall at Far-end            : No

Pin                                  : ~ALTERA_DCLK~
I/O Standard                         : 3.3-V LVTTL
Board Delay on Rise                  : 0 s
Board Delay on Fall                  : 0 s
Steady State Voh at FPGA Pin         : 3.46 V
Steady State Vol at FPGA Pin         : 6.54e-08 V
Voh Max at FPGA Pin                  : 3.66 V
Vol Min at FPGA Pin                  : -0.258 V
Ringback Voltage on Rise at FPGA Pin : 0.41 V
Ringback Voltage on Fall at FPGA Pin : 0.318 V
10-90 Rise Time at FPGA Pin          : 1.57e-10 s
90-10 Fall Time at FPGA Pin          : 2.15e-10 s
Monotonic Rise at FPGA Pin           : No
Monotonic Fall at FPGA Pin           : Yes
Steady State Voh at Far-end          : 3.46 V
Steady State Vol at Far-end          : 6.54e-08 V
Voh Max at Far-end                   : 3.66 V
Vol Min at Far-end                   : -0.258 V
Ringback Voltage on Rise at Far-end  : 0.41 V
Ringback Voltage on Fall at Far-end  : 0.318 V
10-90 Rise Time at Far-end           : 1.57e-10 s
90-10 Fall Time at Far-end           : 2.15e-10 s
Monotonic Rise at Far-end            : No
Monotonic Fall at Far-end            : Yes

Pin                                  : ~ALTERA_nCEO~
I/O Standard                         : 2.5 V
Board Delay on Rise                  : 0 s
Board Delay on Fall                  : 0 s
Steady State Voh at FPGA Pin         : 2.62 V
Steady State Vol at FPGA Pin         : 3.54e-08 V
Voh Max at FPGA Pin                  : 2.7 V
Vol Min at FPGA Pin                  : -0.00943 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.035 V
10-90 Rise Time at FPGA Pin          : 3.19e-10 s
90-10 Fall Time at FPGA Pin          : 4.99e-10 s
Monotonic Rise at FPGA Pin           : No
Monotonic Fall at FPGA Pin           : Yes
Steady State Voh at Far-end          : 2.62 V
Steady State Vol at Far-end          : 3.54e-08 V
Voh Max at Far-end                   : 2.7 V
Vol Min at Far-end                   : -0.00943 V
Ringback Voltage on Rise at Far-end  : 0.276 V
Ringback Voltage on Fall at Far-end  : 0.035 V
10-90 Rise Time at Far-end           : 3.19e-10 s
90-10 Fall Time at Far-end           : 4.99e-10 s
Monotonic Rise at Far-end            : No
Monotonic Fall at Far-end            : Yes
+--------------------------------------------------------------------------------+



+--------------------------------------------------------------------------------+
; Setup Transfers                                                                ;
+--------------------------------------------------------------------------------+
From Clock : CLOCK_50
To Clock   : CLOCK_50
RR Paths   : 908
FR Paths   : 0
RF Paths   : 0
FF Paths   : 0
+--------------------------------------------------------------------------------+

Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+--------------------------------------------------------------------------------+
; Hold Transfers                                                                 ;
+--------------------------------------------------------------------------------+
From Clock : CLOCK_50
To Clock   : CLOCK_50
RR Paths   : 908
FR Paths   : 0
RF Paths   : 0
FF Paths   : 0
+--------------------------------------------------------------------------------+

Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design


+--------------------------------------------------------------------------------+
; Unconstrained Paths                                                            ;
+--------------------------------------------------------------------------------+
Property : Illegal Clocks
Setup    : 0
Hold     : 0

Property : Unconstrained Clocks
Setup    : 0
Hold     : 0

Property : Unconstrained Input Ports
Setup    : 0
Hold     : 0

Property : Unconstrained Input Port Paths
Setup    : 0
Hold     : 0

Property : Unconstrained Output Ports
Setup    : 8
Hold     : 8

Property : Unconstrained Output Port Paths
Setup    : 24
Hold     : 24
+--------------------------------------------------------------------------------+



+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
    Info: Processing started: Wed Mar 30 13:12:24 2022
Info: Command: quartus_sta spectrum -c spectrum
Info: qsta_default_script.tcl version: #1
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (21077): Core supply voltage is 1.2V
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Critical Warning (332012): Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332105): Deriving Clocks
    Info (332105): create_clock -period 1.000 -name CLOCK_50 CLOCK_50
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -1.788
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -1.788             -88.557 CLOCK_50 
Info (332146): Worst-case hold slack is 0.260
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.260               0.000 CLOCK_50 
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -3.000
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -3.000            -110.836 CLOCK_50 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -1.527
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -1.527             -72.611 CLOCK_50 
Info (332146): Worst-case hold slack is 0.255
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.255               0.000 CLOCK_50 
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -3.000
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -3.000            -110.824 CLOCK_50 
Info: Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -0.529
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.529             -18.538 CLOCK_50 
Info (332146): Worst-case hold slack is 0.123
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.123               0.000 CLOCK_50 
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -3.000
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -3.000             -93.684 CLOCK_50 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
    Info: Peak virtual memory: 407 megabytes
    Info: Processing ended: Wed Mar 30 13:12:26 2022
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:02