437 lines
14 KiB
Verilog
437 lines
14 KiB
Verilog
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/*
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This SDRAM controller is for the Mojo's SDRAM shield which uses
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a 48LC32M8A2-7E SDRAM chip. This module was designed under the
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assumption that the click rate is 100MHz. Timing values would
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need to be re-evaluated under different clock rates.
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This controller features two baisc improvements over the most
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basic of controllers. It does burst reads and writes of 4 bytes,
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and it only closes a row when it has to.
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*/
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module sdram (
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input clk,
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input rst,
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// these signals go directly to the IO pins
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output sdram_clk,
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output sdram_cle,
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output sdram_cs,
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output sdram_cas,
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output sdram_ras,
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output sdram_we,
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output sdram_dqm,
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output [1:0] sdram_ba,
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output [12:0] sdram_a,
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inout [7:0] sdram_dq,
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// User interface
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input [22:0] addr, // address to read/write
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input rw, // 1 = write, 0 = read
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input [31:0] data_in, // data from a read
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output [31:0] data_out, // data for a write
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output busy, // controller is busy when high
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input in_valid, // pulse high to initiate a read/write
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output out_valid // pulses high when data from read is valid
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);
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// Commands for the SDRAM
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localparam CMD_UNSELECTED = 4'b1000;
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localparam CMD_NOP = 4'b0111;
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localparam CMD_ACTIVE = 4'b0011;
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localparam CMD_READ = 4'b0101;
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localparam CMD_WRITE = 4'b0100;
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localparam CMD_TERMINATE = 4'b0110;
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localparam CMD_PRECHARGE = 4'b0010;
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localparam CMD_REFRESH = 4'b0001;
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localparam CMD_LOAD_MODE_REG = 4'b0000;
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localparam STATE_SIZE = 4;
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localparam INIT = 0,
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WAIT = 1,
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PRECHARGE_INIT = 2,
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REFRESH_INIT_1 = 3,
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REFRESH_INIT_2 = 4,
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LOAD_MODE_REG = 5,
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IDLE = 6,
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REFRESH = 7,
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ACTIVATE = 8,
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READ = 9,
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READ_RES = 10,
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WRITE = 11,
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PRECHARGE = 12;
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wire sdram_clk_ddr;
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// This is used to drive the SDRAM clock
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ODDR2 #(
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.DDR_ALIGNMENT("NONE"),
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.INIT(1'b0),
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.SRTYPE("SYNC")
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) ODDR2_inst (
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.Q(sdram_clk_ddr), // 1-bit DDR output data
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.C0(clk), // 1-bit clock input
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.C1(~clk), // 1-bit clock input
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.CE(1'b1), // 1-bit clock enable input
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.D0(1'b0), // 1-bit data input (associated with C0)
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.D1(1'b1), // 1-bit data input (associated with C1)
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.R(1'b0), // 1-bit reset input
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.S(1'b0) // 1-bit set input
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);
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IODELAY2 #(
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.IDELAY_VALUE(0),
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.IDELAY_MODE("NORMAL"),
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.ODELAY_VALUE(100), // value of 100 seems to work at 100MHz
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.IDELAY_TYPE("FIXED"),
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.DELAY_SRC("ODATAIN"),
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.DATA_RATE("SDR")
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) IODELAY_inst (
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.IDATAIN(1'b0),
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.T(1'b0),
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.ODATAIN(sdram_clk_ddr),
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.CAL(1'b0),
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.IOCLK0(1'b0),
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.IOCLK1(1'b0),
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.CLK(1'b0),
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.INC(1'b0),
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.CE(1'b0),
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.RST(1'b0),
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.BUSY(),
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.DATAOUT(),
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.DATAOUT2(),
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.TOUT(),
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.DOUT(sdram_clk)
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);
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// registers for SDRAM signals
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reg cle_d, dqm_d;
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reg [3:0] cmd_d;
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reg [1:0] ba_d;
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reg [12:0] a_d;
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reg [7:0] dq_d;
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reg [7:0] dqi_d;
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// We want the output/input registers to be embedded in the
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// IO buffers so we set IOB to "TRUE". This is to ensure all
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// the signals are sent and received at the same time.
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(* IOB = "TRUE" *)
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reg cle_q, dqm_q;
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(* IOB = "TRUE" *)
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reg [3:0] cmd_q;
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(* IOB = "TRUE" *)
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reg [1:0] ba_q;
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(* IOB = "TRUE" *)
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reg [12:0] a_q;
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(* IOB = "TRUE" *)
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reg [7:0] dq_q;
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(* IOB = "TRUE" *)
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reg [7:0] dqi_q;
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reg dq_en_d, dq_en_q;
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// Output assignments
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assign sdram_cle = cle_q;
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assign sdram_cs = cmd_q[3];
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assign sdram_ras = cmd_q[2];
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assign sdram_cas = cmd_q[1];
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assign sdram_we = cmd_q[0];
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assign sdram_dqm = dqm_q;
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assign sdram_ba = ba_q;
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assign sdram_a = a_q;
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assign sdram_dq = dq_en_q ? dq_q : 8'hZZ; // only drive when dq_en_q is 1
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reg [STATE_SIZE-1:0] state_d, state_q = INIT;
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reg [STATE_SIZE-1:0] next_state_d, next_state_q;
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reg [22:0] addr_d, addr_q;
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reg [31:0] data_d, data_q;
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reg out_valid_d, out_valid_q;
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assign data_out = data_q;
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assign busy = !ready_q;
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assign out_valid = out_valid_q;
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reg [15:0] delay_ctr_d, delay_ctr_q;
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reg [1:0] byte_ctr_d, byte_ctr_q;
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reg [9:0] refresh_ctr_d, refresh_ctr_q;
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reg refresh_flag_d, refresh_flag_q;
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reg ready_d, ready_q;
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reg saved_rw_d, saved_rw_q;
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reg [22:0] saved_addr_d, saved_addr_q;
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reg [31:0] saved_data_d, saved_data_q;
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reg rw_op_d, rw_op_q;
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reg [3:0] row_open_d, row_open_q;
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reg [12:0] row_addr_d[3:0], row_addr_q[3:0];
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reg [2:0] precharge_bank_d, precharge_bank_q;
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integer i;
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always @* begin
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// Default values
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dq_d = dq_q;
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dqi_d = sdram_dq;
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dq_en_d = 1'b0; // normally keep the bus in high-Z
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cle_d = cle_q;
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cmd_d = CMD_NOP; // default to NOP
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dqm_d = 1'b0;
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ba_d = 2'd0;
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a_d = 25'd0;
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state_d = state_q;
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next_state_d = next_state_q;
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delay_ctr_d = delay_ctr_q;
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addr_d = addr_q;
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data_d = data_q;
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out_valid_d = 1'b0;
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precharge_bank_d = precharge_bank_q;
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rw_op_d = rw_op_q;
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byte_ctr_d = 2'd0;
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row_open_d = row_open_q;
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// row_addr is a 2d array and must be coppied this way
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for (i = 0; i < 4; i = i + 1)
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row_addr_d[i] = row_addr_q[i];
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// The data in the SDRAM must be refreshed periodically.
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// This conter ensures that the data remains intact.
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refresh_flag_d = refresh_flag_q;
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refresh_ctr_d = refresh_ctr_q + 1'b1;
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if (refresh_ctr_q > 10'd750) begin
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refresh_ctr_d = 10'd0;
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refresh_flag_d = 1'b1;
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end
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saved_rw_d = saved_rw_q;
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saved_data_d = saved_data_q;
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saved_addr_d = saved_addr_q;
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ready_d = ready_q;
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// This is a queue of 1 for read/write operations.
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// When the queue is empty we aren't busy and can
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// accept another request.
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if (ready_q && in_valid) begin
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saved_rw_d = rw;
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saved_data_d = data_in;
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saved_addr_d = addr;
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ready_d = 1'b0;
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end
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case (state_q)
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///// INITALIZATION /////
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INIT: begin
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ready_d = 1'b0;
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row_open_d = 4'b0;
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out_valid_d = 1'b0;
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a_d = 13'b0;
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ba_d = 2'b0;
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cle_d = 1'b1;
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state_d = WAIT;
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delay_ctr_d = 16'd10100; // wait for 101us
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next_state_d = PRECHARGE_INIT;
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dq_en_d = 1'b0;
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end
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WAIT: begin
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delay_ctr_d = delay_ctr_q - 1'b1;
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if (delay_ctr_q == 13'd0) begin
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state_d = next_state_q;
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if (next_state_q == WRITE) begin
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dq_en_d = 1'b1; // enable the bus early
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dq_d = data_q[7:0];
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end
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end
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end
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PRECHARGE_INIT: begin
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cmd_d = CMD_PRECHARGE;
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a_d[10] = 1'b1; // all banks
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ba_d = 2'd0;
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state_d = WAIT;
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next_state_d = REFRESH_INIT_1;
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delay_ctr_d = 13'd0;
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end
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REFRESH_INIT_1: begin
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cmd_d = CMD_REFRESH;
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state_d = WAIT;
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delay_ctr_d = 13'd7;
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next_state_d = REFRESH_INIT_2;
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end
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REFRESH_INIT_2: begin
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cmd_d = CMD_REFRESH;
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state_d = WAIT;
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delay_ctr_d = 13'd7;
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next_state_d = LOAD_MODE_REG;
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end
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LOAD_MODE_REG: begin
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cmd_d = CMD_LOAD_MODE_REG;
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ba_d = 2'b0;
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// Reserved, Burst Access, Standard Op, CAS = 2, Sequential, Burst = 4
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a_d = {3'b000, 1'b0, 2'b00, 3'b010, 1'b0, 3'b010}; //010
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state_d = WAIT;
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delay_ctr_d = 13'd1;
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next_state_d = IDLE;
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refresh_flag_d = 1'b0;
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refresh_ctr_d = 10'b1;
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ready_d = 1'b1;
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end
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///// IDLE STATE /////
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IDLE: begin
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if (refresh_flag_q) begin // we need to do a refresh
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state_d = PRECHARGE;
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next_state_d = REFRESH;
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precharge_bank_d = 3'b100; // all banks
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refresh_flag_d = 1'b0; // clear the refresh flag
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end else if (!ready_q) begin // operation waiting
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ready_d = 1'b1; // clear the queue
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rw_op_d = saved_rw_q; // save the values we'll need later
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addr_d = saved_addr_q;
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if (saved_rw_q) // Write
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data_d = saved_data_q;
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// if the row is open we don't have to activate it
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if (row_open_q[saved_addr_q[9:8]]) begin
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if (row_addr_q[saved_addr_q[9:8]] == saved_addr_q[22:10]) begin
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// Row is already open
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if (saved_rw_q)
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state_d = WRITE;
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else
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state_d = READ;
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end else begin
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// A different row in the bank is open
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state_d = PRECHARGE; // precharge open row
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precharge_bank_d = {1'b0, saved_addr_q[9:8]};
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next_state_d = ACTIVATE; // open current row
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end
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end else begin
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// no rows open
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state_d = ACTIVATE; // open the row
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end
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end
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end
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///// REFRESH /////
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REFRESH: begin
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cmd_d = CMD_REFRESH;
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state_d = WAIT;
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delay_ctr_d = 13'd6; // gotta wait 7 clocks (66ns)
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next_state_d = IDLE;
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end
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///// ACTIVATE /////
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ACTIVATE: begin
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cmd_d = CMD_ACTIVE;
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a_d = addr_q[22:10];
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ba_d = addr_q[9:8];
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delay_ctr_d = 13'd0;
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state_d = WAIT;
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if (rw_op_q)
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next_state_d = WRITE;
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else
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next_state_d = READ;
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row_open_d[addr_q[9:8]] = 1'b1; // row is now open
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row_addr_d[addr_q[9:8]] = addr_q[22:10];
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end
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///// READ /////
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READ: begin
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cmd_d = CMD_READ;
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a_d = {2'b0, 1'b0, addr_q[7:0], 2'b0};
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ba_d = addr_q[9:8];
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state_d = WAIT;
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delay_ctr_d = 13'd2; // wait for the data to show up
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next_state_d = READ_RES;
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end
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READ_RES: begin
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byte_ctr_d = byte_ctr_q + 1'b1; // we need to read in 4 bytes
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data_d = {dqi_q, data_q[31:8]}; // shift the data in
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if (byte_ctr_q == 2'd3) begin
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out_valid_d = 1'b1;
|
||
|
|
state_d = IDLE;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
///// WRITE /////
|
||
|
|
WRITE: begin
|
||
|
|
byte_ctr_d = byte_ctr_q + 1'b1; // send out 4 bytes
|
||
|
|
|
||
|
|
if (byte_ctr_q == 2'd0) // first byte send write command
|
||
|
|
cmd_d = CMD_WRITE;
|
||
|
|
|
||
|
|
dq_d = data_q[7:0];
|
||
|
|
data_d = {8'h00, data_q[31:8]}; // shift the data out
|
||
|
|
dq_en_d = 1'b1; // enable out bus
|
||
|
|
a_d = {2'b0, 1'b0, addr_q[7:0], 2'b00};
|
||
|
|
ba_d = addr_q[9:8];
|
||
|
|
|
||
|
|
if (byte_ctr_q == 2'd3) begin
|
||
|
|
state_d = IDLE;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
///// PRECHARGE /////
|
||
|
|
PRECHARGE: begin
|
||
|
|
cmd_d = CMD_PRECHARGE;
|
||
|
|
a_d[10] = precharge_bank_q[2]; // all banks
|
||
|
|
ba_d = precharge_bank_q[1:0];
|
||
|
|
state_d = WAIT;
|
||
|
|
delay_ctr_d = 13'd0;
|
||
|
|
|
||
|
|
if (precharge_bank_q[2]) begin
|
||
|
|
row_open_d = 4'b0000; // closed all rows
|
||
|
|
end else begin
|
||
|
|
row_open_d[precharge_bank_q[1:0]] = 1'b0; // closed one row
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
default: state_d = INIT;
|
||
|
|
endcase
|
||
|
|
|
||
|
|
end
|
||
|
|
|
||
|
|
always @(posedge clk) begin
|
||
|
|
if(rst) begin
|
||
|
|
cle_q <= 1'b0;
|
||
|
|
dq_en_q <= 1'b0;
|
||
|
|
state_q <= INIT;
|
||
|
|
ready_q <= 1'b0;
|
||
|
|
end else begin
|
||
|
|
cle_q <= cle_d;
|
||
|
|
dq_en_q <= dq_en_d;
|
||
|
|
state_q <= state_d;
|
||
|
|
ready_q <= ready_d;
|
||
|
|
end
|
||
|
|
|
||
|
|
saved_rw_q <= saved_rw_d;
|
||
|
|
saved_data_q <= saved_data_d;
|
||
|
|
saved_addr_q <= saved_addr_d;
|
||
|
|
|
||
|
|
cmd_q <= cmd_d;
|
||
|
|
dqm_q <= dqm_d;
|
||
|
|
ba_q <= ba_d;
|
||
|
|
a_q <= a_d;
|
||
|
|
dq_q <= dq_d;
|
||
|
|
dqi_q <= dqi_d;
|
||
|
|
|
||
|
|
next_state_q <= next_state_d;
|
||
|
|
refresh_flag_q <= refresh_flag_d;
|
||
|
|
refresh_ctr_q <= refresh_ctr_d;
|
||
|
|
data_q <= data_d;
|
||
|
|
addr_q <= addr_d;
|
||
|
|
out_valid_q <= out_valid_d;
|
||
|
|
row_open_q <= row_open_d;
|
||
|
|
for (i = 0; i < 4; i = i + 1)
|
||
|
|
row_addr_q[i] <= row_addr_d[i];
|
||
|
|
precharge_bank_q <= precharge_bank_d;
|
||
|
|
rw_op_q <= rw_op_d;
|
||
|
|
byte_ctr_q <= byte_ctr_d;
|
||
|
|
delay_ctr_q <= delay_ctr_d;
|
||
|
|
end
|
||
|
|
endmodule
|