108 lines
7.3 KiB
Plaintext
108 lines
7.3 KiB
Plaintext
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EDA Netlist Writer report for spectrum
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Sat Apr 2 16:36:04 2022
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Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. EDA Netlist Writer Summary
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3. Simulation Settings
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4. Simulation Generated Files
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5. EDA Netlist Writer Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 1991-2013 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors. Please refer to the
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applicable agreement for further details.
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+-------------------------------------------------------------------+
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; EDA Netlist Writer Summary ;
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+---------------------------+---------------------------------------+
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; EDA Netlist Writer Status ; Successful - Sat Apr 2 16:36:04 2022 ;
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; Revision Name ; spectrum ;
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; Top-level Entity Name ; spectrum ;
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; Family ; Cyclone IV E ;
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; Simulation Files Creation ; Successful ;
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+---------------------------+---------------------------------------+
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+-------------------------------------------------------------------------------------------------------------------------------+
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; Simulation Settings ;
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+---------------------------------------------------------------------------------------------------+---------------------------+
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; Option ; Setting ;
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+---------------------------------------------------------------------------------------------------+---------------------------+
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; Tool Name ; ModelSim-Altera (Verilog) ;
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; Generate netlist for functional simulation only ; Off ;
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; Time scale ; 1 ps ;
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; Truncate long hierarchy paths ; Off ;
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; Map illegal HDL characters ; Off ;
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; Flatten buses into individual nodes ; Off ;
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; Maintain hierarchy ; Off ;
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; Bring out device-wide set/reset signals as ports ; Off ;
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; Enable glitch filtering ; Off ;
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; Do not write top level VHDL entity ; Off ;
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; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
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; Architecture name in VHDL output netlist ; structure ;
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; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
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; Generate third-party EDA tool command script for gate-level simulation ; Off ;
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+---------------------------------------------------------------------------------------------------+---------------------------+
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+--------------------------------------------------------------------------------------+
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; Simulation Generated Files ;
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+--------------------------------------------------------------------------------------+
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; Generated Files ;
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+--------------------------------------------------------------------------------------+
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; /home/benny/work/fpga/spectrum/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo ;
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; /home/benny/work/fpga/spectrum/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo ;
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; /home/benny/work/fpga/spectrum/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo ;
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; /home/benny/work/fpga/spectrum/simulation/modelsim/spectrum.vo ;
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; /home/benny/work/fpga/spectrum/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo ;
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; /home/benny/work/fpga/spectrum/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo ;
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; /home/benny/work/fpga/spectrum/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo ;
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; /home/benny/work/fpga/spectrum/simulation/modelsim/spectrum_v.sdo ;
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+--------------------------------------------------------------------------------------+
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+-----------------------------+
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; EDA Netlist Writer Messages ;
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+-----------------------------+
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Info: *******************************************************************
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Info: Running Quartus II 32-bit EDA Netlist Writer
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Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
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Info: Processing started: Sat Apr 2 16:36:01 2022
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Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum
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Info (204019): Generated file spectrum_6_1200mv_85c_slow.vo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file spectrum_6_1200mv_0c_slow.vo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file spectrum_min_1200mv_0c_fast.vo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file spectrum.vo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file spectrum_v.sdo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool
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Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings
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Info: Peak virtual memory: 384 megabytes
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Info: Processing ended: Sat Apr 2 16:36:04 2022
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Info: Elapsed time: 00:00:03
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Info: Total CPU time (on all processors): 00:00:03
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