5096 lines
258 KiB
Systemverilog
5096 lines
258 KiB
Systemverilog
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// Automatically generated by genfuse.py
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force dut.resets_.clrpc=0;
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force dut.reg_file_.reg_gp_we=0;
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force dut.reg_control_.ctl_reg_sys_we=0;
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force dut.z80_top_ifc_n.fpga_reset=1;
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#2 // Start test loop
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force dut.ir_.ctl_ir_we=1;
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force dut.ir_.db=0;
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#2 release dut.ir_.ctl_ir_we;
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release dut.ir_.db;
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$fdisplay(f,"Testing opcode 00 NOP");
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// Preset af
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force dut.reg_file_.b2v_latch_af_lo.we=1;
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force dut.reg_file_.b2v_latch_af_hi.we=1;
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force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
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force dut.reg_file_.b2v_latch_af_hi.db=8'h00;
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#2 release dut.reg_file_.b2v_latch_af_lo.we;
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release dut.reg_file_.b2v_latch_af_hi.we;
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release dut.reg_file_.b2v_latch_af_lo.db;
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release dut.reg_file_.b2v_latch_af_hi.db;
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// Preset bc
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force dut.reg_file_.b2v_latch_bc_lo.we=1;
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force dut.reg_file_.b2v_latch_bc_hi.we=1;
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force dut.reg_file_.b2v_latch_bc_lo.db=8'h00;
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force dut.reg_file_.b2v_latch_bc_hi.db=8'h00;
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#2 release dut.reg_file_.b2v_latch_bc_lo.we;
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release dut.reg_file_.b2v_latch_bc_hi.we;
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release dut.reg_file_.b2v_latch_bc_lo.db;
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release dut.reg_file_.b2v_latch_bc_hi.db;
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// Preset de
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force dut.reg_file_.b2v_latch_de_lo.we=1;
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force dut.reg_file_.b2v_latch_de_hi.we=1;
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force dut.reg_file_.b2v_latch_de_lo.db=8'h00;
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force dut.reg_file_.b2v_latch_de_hi.db=8'h00;
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#2 release dut.reg_file_.b2v_latch_de_lo.we;
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release dut.reg_file_.b2v_latch_de_hi.we;
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release dut.reg_file_.b2v_latch_de_lo.db;
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release dut.reg_file_.b2v_latch_de_hi.db;
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// Preset hl
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force dut.reg_file_.b2v_latch_hl_lo.we=1;
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force dut.reg_file_.b2v_latch_hl_hi.we=1;
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force dut.reg_file_.b2v_latch_hl_lo.db=8'h00;
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force dut.reg_file_.b2v_latch_hl_hi.db=8'h00;
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#2 release dut.reg_file_.b2v_latch_hl_lo.we;
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release dut.reg_file_.b2v_latch_hl_hi.we;
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release dut.reg_file_.b2v_latch_hl_lo.db;
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release dut.reg_file_.b2v_latch_hl_hi.db;
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// Preset af2
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force dut.reg_file_.b2v_latch_af2_lo.we=1;
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force dut.reg_file_.b2v_latch_af2_hi.we=1;
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force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
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force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
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#2 release dut.reg_file_.b2v_latch_af2_lo.we;
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release dut.reg_file_.b2v_latch_af2_hi.we;
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release dut.reg_file_.b2v_latch_af2_lo.db;
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release dut.reg_file_.b2v_latch_af2_hi.db;
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// Preset bc2
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force dut.reg_file_.b2v_latch_bc2_lo.we=1;
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force dut.reg_file_.b2v_latch_bc2_hi.we=1;
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force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
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force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
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#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
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release dut.reg_file_.b2v_latch_bc2_hi.we;
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release dut.reg_file_.b2v_latch_bc2_lo.db;
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release dut.reg_file_.b2v_latch_bc2_hi.db;
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// Preset de2
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force dut.reg_file_.b2v_latch_de2_lo.we=1;
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force dut.reg_file_.b2v_latch_de2_hi.we=1;
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force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
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force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
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#2 release dut.reg_file_.b2v_latch_de2_lo.we;
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release dut.reg_file_.b2v_latch_de2_hi.we;
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release dut.reg_file_.b2v_latch_de2_lo.db;
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release dut.reg_file_.b2v_latch_de2_hi.db;
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// Preset hl2
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force dut.reg_file_.b2v_latch_hl2_lo.we=1;
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force dut.reg_file_.b2v_latch_hl2_hi.we=1;
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force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
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force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
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#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
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release dut.reg_file_.b2v_latch_hl2_hi.we;
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release dut.reg_file_.b2v_latch_hl2_lo.db;
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release dut.reg_file_.b2v_latch_hl2_hi.db;
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// Preset ix
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force dut.reg_file_.b2v_latch_ix_lo.we=1;
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force dut.reg_file_.b2v_latch_ix_hi.we=1;
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force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
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force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
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#2 release dut.reg_file_.b2v_latch_ix_lo.we;
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release dut.reg_file_.b2v_latch_ix_hi.we;
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release dut.reg_file_.b2v_latch_ix_lo.db;
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release dut.reg_file_.b2v_latch_ix_hi.db;
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// Preset iy
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force dut.reg_file_.b2v_latch_iy_lo.we=1;
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force dut.reg_file_.b2v_latch_iy_hi.we=1;
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force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
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force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
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#2 release dut.reg_file_.b2v_latch_iy_lo.we;
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release dut.reg_file_.b2v_latch_iy_hi.we;
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release dut.reg_file_.b2v_latch_iy_lo.db;
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release dut.reg_file_.b2v_latch_iy_hi.db;
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// Preset sp
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force dut.reg_file_.b2v_latch_sp_lo.we=1;
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force dut.reg_file_.b2v_latch_sp_hi.we=1;
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force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
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force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
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#2 release dut.reg_file_.b2v_latch_sp_lo.we;
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release dut.reg_file_.b2v_latch_sp_hi.we;
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release dut.reg_file_.b2v_latch_sp_lo.db;
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release dut.reg_file_.b2v_latch_sp_hi.db;
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// Preset wz
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force dut.reg_file_.b2v_latch_wz_lo.we=1;
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force dut.reg_file_.b2v_latch_wz_hi.we=1;
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force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
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force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
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#2 release dut.reg_file_.b2v_latch_wz_lo.we;
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release dut.reg_file_.b2v_latch_wz_hi.we;
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release dut.reg_file_.b2v_latch_wz_lo.db;
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release dut.reg_file_.b2v_latch_wz_hi.db;
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// Preset pc
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force dut.reg_file_.b2v_latch_pc_lo.we=1;
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force dut.reg_file_.b2v_latch_pc_hi.we=1;
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force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
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force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
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#2 release dut.reg_file_.b2v_latch_pc_lo.we;
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release dut.reg_file_.b2v_latch_pc_hi.we;
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release dut.reg_file_.b2v_latch_pc_lo.db;
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release dut.reg_file_.b2v_latch_pc_hi.db;
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// Preset ir
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force dut.reg_file_.b2v_latch_ir_lo.we=1;
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force dut.reg_file_.b2v_latch_ir_hi.we=1;
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force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
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force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
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#2 release dut.reg_file_.b2v_latch_ir_lo.we;
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release dut.reg_file_.b2v_latch_ir_hi.we;
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release dut.reg_file_.b2v_latch_ir_lo.db;
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release dut.reg_file_.b2v_latch_ir_hi.db;
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// Preset memory
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ram.Mem[0] = 8'h00;
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force dut.z80_top_ifc_n.fpga_reset=0;
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force dut.address_latch_.Q=16'h0000;
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release dut.reg_control_.ctl_reg_sys_we;
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release dut.reg_file_.reg_gp_we;
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#2 // Execute: M1/T1 start
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#1 release dut.address_latch_.Q;
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#1
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#6 // Wait for opcode end
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force dut.reg_control_.ctl_reg_sys_we=0;
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#2 pc=z.A;
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#2
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#1 force dut.reg_file_.reg_gp_we=0;
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force dut.z80_top_ifc_n.fpga_reset=1;
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if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,"* Reg af f=%h !=00",dut.reg_file_.b2v_latch_af_lo.latch);
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if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h00) $fdisplay(f,"* Reg af a=%h !=00",dut.reg_file_.b2v_latch_af_hi.latch);
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if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h00) $fdisplay(f,"* Reg bc c=%h !=00",dut.reg_file_.b2v_latch_bc_lo.latch);
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if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h00) $fdisplay(f,"* Reg bc b=%h !=00",dut.reg_file_.b2v_latch_bc_hi.latch);
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if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h00) $fdisplay(f,"* Reg de e=%h !=00",dut.reg_file_.b2v_latch_de_lo.latch);
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if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h00) $fdisplay(f,"* Reg de d=%h !=00",dut.reg_file_.b2v_latch_de_hi.latch);
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if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h00) $fdisplay(f,"* Reg hl l=%h !=00",dut.reg_file_.b2v_latch_hl_lo.latch);
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if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h00) $fdisplay(f,"* Reg hl h=%h !=00",dut.reg_file_.b2v_latch_hl_hi.latch);
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if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
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if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
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if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
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if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
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if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
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if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
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if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
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if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
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if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
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if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
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if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
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if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
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if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
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if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
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if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
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if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
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if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
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#1 // End opcode
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force dut.ir_.ctl_ir_we=1;
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force dut.ir_.db=0;
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#2 release dut.ir_.ctl_ir_we;
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release dut.ir_.db;
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$fdisplay(f,"Testing opcode ed67 RRD");
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// Preset af
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force dut.reg_file_.b2v_latch_af_lo.we=1;
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force dut.reg_file_.b2v_latch_af_hi.we=1;
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force dut.reg_file_.b2v_latch_af_lo.db=8'h24;
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force dut.reg_file_.b2v_latch_af_hi.db=8'h36;
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#2 release dut.reg_file_.b2v_latch_af_lo.we;
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release dut.reg_file_.b2v_latch_af_hi.we;
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release dut.reg_file_.b2v_latch_af_lo.db;
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release dut.reg_file_.b2v_latch_af_hi.db;
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// Preset bc
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force dut.reg_file_.b2v_latch_bc_lo.we=1;
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force dut.reg_file_.b2v_latch_bc_hi.we=1;
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force dut.reg_file_.b2v_latch_bc_lo.db=8'h6a;
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force dut.reg_file_.b2v_latch_bc_hi.db=8'hb1;
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#2 release dut.reg_file_.b2v_latch_bc_lo.we;
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release dut.reg_file_.b2v_latch_bc_hi.we;
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release dut.reg_file_.b2v_latch_bc_lo.db;
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release dut.reg_file_.b2v_latch_bc_hi.db;
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// Preset de
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force dut.reg_file_.b2v_latch_de_lo.we=1;
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force dut.reg_file_.b2v_latch_de_hi.we=1;
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force dut.reg_file_.b2v_latch_de_lo.db=8'hdb;
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force dut.reg_file_.b2v_latch_de_hi.db=8'ha4;
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#2 release dut.reg_file_.b2v_latch_de_lo.we;
|
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release dut.reg_file_.b2v_latch_de_hi.we;
|
||
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release dut.reg_file_.b2v_latch_de_lo.db;
|
||
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release dut.reg_file_.b2v_latch_de_hi.db;
|
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// Preset hl
|
||
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force dut.reg_file_.b2v_latch_hl_lo.we=1;
|
||
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force dut.reg_file_.b2v_latch_hl_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.db=8'hde;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.db=8'hb9;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.db;
|
||
|
|
// Preset af2
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.db;
|
||
|
|
// Preset bc2
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.db;
|
||
|
|
// Preset de2
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.db;
|
||
|
|
// Preset hl2
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.db;
|
||
|
|
// Preset ix
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.db;
|
||
|
|
// Preset iy
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.db;
|
||
|
|
// Preset sp
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.db;
|
||
|
|
// Preset wz
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.db;
|
||
|
|
// Preset pc
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.db;
|
||
|
|
// Preset ir
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.db;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[0] = 8'hed;
|
||
|
|
ram.Mem[1] = 8'h67;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[47582] = 8'h93;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=0;
|
||
|
|
force dut.address_latch_.Q=16'h0000;
|
||
|
|
release dut.reg_control_.ctl_reg_sys_we;
|
||
|
|
release dut.reg_file_.reg_gp_we;
|
||
|
|
#2 // Execute: M1/T1 start
|
||
|
|
#1 release dut.address_latch_.Q;
|
||
|
|
#1
|
||
|
|
#34 // Wait for opcode end
|
||
|
|
force dut.reg_control_.ctl_reg_sys_we=0;
|
||
|
|
#2 pc=z.A;
|
||
|
|
#2
|
||
|
|
#1 force dut.reg_file_.reg_gp_we=0;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=1;
|
||
|
|
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h24) $fdisplay(f,"* Reg af f=%h !=24",dut.reg_file_.b2v_latch_af_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h33) $fdisplay(f,"* Reg af a=%h !=33",dut.reg_file_.b2v_latch_af_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h6a) $fdisplay(f,"* Reg bc c=%h !=6a",dut.reg_file_.b2v_latch_bc_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'hb1) $fdisplay(f,"* Reg bc b=%h !=b1",dut.reg_file_.b2v_latch_bc_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hdb) $fdisplay(f,"* Reg de e=%h !=db",dut.reg_file_.b2v_latch_de_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'ha4) $fdisplay(f,"* Reg de d=%h !=a4",dut.reg_file_.b2v_latch_de_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'hde) $fdisplay(f,"* Reg hl l=%h !=de",dut.reg_file_.b2v_latch_hl_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hb9) $fdisplay(f,"* Reg hl h=%h !=b9",dut.reg_file_.b2v_latch_hl_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
|
||
|
|
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
|
||
|
|
if (ram.Mem[47582]!==8'h69) $fdisplay(f,"* Mem[b9de]=%h !=69",ram.Mem[47582]);
|
||
|
|
#1 // End opcode
|
||
|
|
|
||
|
|
force dut.ir_.ctl_ir_we=1;
|
||
|
|
force dut.ir_.db=0;
|
||
|
|
#2 release dut.ir_.ctl_ir_we;
|
||
|
|
release dut.ir_.db;
|
||
|
|
$fdisplay(f,"Testing opcode ed6f RLD");
|
||
|
|
// Preset af
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.db=8'h8b;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.db=8'h65;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.db;
|
||
|
|
// Preset bc
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.db=8'h7a;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.db=8'h7a;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.db;
|
||
|
|
// Preset de
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.db=8'hf0;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.db=8'hec;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.db;
|
||
|
|
// Preset hl
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.db=8'h3c;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.db=8'h40;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.db;
|
||
|
|
// Preset af2
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.db;
|
||
|
|
// Preset bc2
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.db;
|
||
|
|
// Preset de2
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.db;
|
||
|
|
// Preset hl2
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.db;
|
||
|
|
// Preset ix
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.db;
|
||
|
|
// Preset iy
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.db;
|
||
|
|
// Preset sp
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.db;
|
||
|
|
// Preset wz
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.db;
|
||
|
|
// Preset pc
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.db;
|
||
|
|
// Preset ir
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.db;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[0] = 8'hed;
|
||
|
|
ram.Mem[1] = 8'h6f;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[16444] = 8'hc4;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=0;
|
||
|
|
force dut.address_latch_.Q=16'h0000;
|
||
|
|
release dut.reg_control_.ctl_reg_sys_we;
|
||
|
|
release dut.reg_file_.reg_gp_we;
|
||
|
|
#2 // Execute: M1/T1 start
|
||
|
|
#1 release dut.address_latch_.Q;
|
||
|
|
#1
|
||
|
|
#34 // Wait for opcode end
|
||
|
|
force dut.reg_control_.ctl_reg_sys_we=0;
|
||
|
|
#2 pc=z.A;
|
||
|
|
#2
|
||
|
|
#1 force dut.reg_file_.reg_gp_we=0;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=1;
|
||
|
|
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h2d) $fdisplay(f,"* Reg af f=%h !=2d",dut.reg_file_.b2v_latch_af_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h6c) $fdisplay(f,"* Reg af a=%h !=6c",dut.reg_file_.b2v_latch_af_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h7a) $fdisplay(f,"* Reg bc c=%h !=7a",dut.reg_file_.b2v_latch_bc_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h7a) $fdisplay(f,"* Reg bc b=%h !=7a",dut.reg_file_.b2v_latch_bc_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hf0) $fdisplay(f,"* Reg de e=%h !=f0",dut.reg_file_.b2v_latch_de_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'hec) $fdisplay(f,"* Reg de d=%h !=ec",dut.reg_file_.b2v_latch_de_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h3c) $fdisplay(f,"* Reg hl l=%h !=3c",dut.reg_file_.b2v_latch_hl_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h40) $fdisplay(f,"* Reg hl h=%h !=40",dut.reg_file_.b2v_latch_hl_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
|
||
|
|
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
|
||
|
|
if (ram.Mem[16444]!==8'h45) $fdisplay(f,"* Mem[403c]=%h !=45",ram.Mem[16444]);
|
||
|
|
#1 // End opcode
|
||
|
|
|
||
|
|
force dut.ir_.ctl_ir_we=1;
|
||
|
|
force dut.ir_.db=0;
|
||
|
|
#2 release dut.ir_.ctl_ir_we;
|
||
|
|
release dut.ir_.db;
|
||
|
|
$fdisplay(f,"Testing opcode 81 ADD A,C");
|
||
|
|
// Preset af
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.db;
|
||
|
|
// Preset bc
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.db;
|
||
|
|
// Preset de
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.db=8'h20;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.db;
|
||
|
|
// Preset hl
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.db;
|
||
|
|
// Preset af2
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.db;
|
||
|
|
// Preset bc2
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.db;
|
||
|
|
// Preset de2
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.db;
|
||
|
|
// Preset hl2
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.db;
|
||
|
|
// Preset ix
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.db;
|
||
|
|
// Preset iy
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.db;
|
||
|
|
// Preset sp
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.db;
|
||
|
|
// Preset wz
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.db;
|
||
|
|
// Preset pc
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.db;
|
||
|
|
// Preset ir
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.db;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[0] = 8'h81;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[56486] = 8'h49;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=0;
|
||
|
|
force dut.address_latch_.Q=16'h0000;
|
||
|
|
release dut.reg_control_.ctl_reg_sys_we;
|
||
|
|
release dut.reg_file_.reg_gp_we;
|
||
|
|
#2 // Execute: M1/T1 start
|
||
|
|
#1 release dut.address_latch_.Q;
|
||
|
|
#1
|
||
|
|
#6 // Wait for opcode end
|
||
|
|
force dut.reg_control_.ctl_reg_sys_we=0;
|
||
|
|
#2 pc=z.A;
|
||
|
|
#2
|
||
|
|
#1 force dut.reg_file_.reg_gp_we=0;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=1;
|
||
|
|
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h31) $fdisplay(f,"* Reg af f=%h !=31",dut.reg_file_.b2v_latch_af_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h30) $fdisplay(f,"* Reg af a=%h !=30",dut.reg_file_.b2v_latch_af_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
|
||
|
|
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
|
||
|
|
#1 // End opcode
|
||
|
|
|
||
|
|
force dut.ir_.ctl_ir_we=1;
|
||
|
|
force dut.ir_.db=0;
|
||
|
|
#2 release dut.ir_.ctl_ir_we;
|
||
|
|
release dut.ir_.db;
|
||
|
|
$fdisplay(f,"Testing opcode cb41 BIT 0,C");
|
||
|
|
// Preset af
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.db=8'h9e;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.db;
|
||
|
|
// Preset bc
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.db=8'h43;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.db=8'h1b;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.db;
|
||
|
|
// Preset de
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.db=8'h4e;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.db=8'h95;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.db;
|
||
|
|
// Preset hl
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.db=8'he9;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.db=8'h7b;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.db;
|
||
|
|
// Preset af2
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.db;
|
||
|
|
// Preset bc2
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.db;
|
||
|
|
// Preset de2
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.db;
|
||
|
|
// Preset hl2
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.db;
|
||
|
|
// Preset ix
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.db;
|
||
|
|
// Preset iy
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.db;
|
||
|
|
// Preset sp
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.db;
|
||
|
|
// Preset wz
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.db;
|
||
|
|
// Preset pc
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.db;
|
||
|
|
// Preset ir
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.db;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[0] = 8'hcb;
|
||
|
|
ram.Mem[1] = 8'h41;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[31721] = 8'hf7;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=0;
|
||
|
|
force dut.address_latch_.Q=16'h0000;
|
||
|
|
release dut.reg_control_.ctl_reg_sys_we;
|
||
|
|
release dut.reg_file_.reg_gp_we;
|
||
|
|
#2 // Execute: M1/T1 start
|
||
|
|
#1 release dut.address_latch_.Q;
|
||
|
|
#1
|
||
|
|
#14 // Wait for opcode end
|
||
|
|
force dut.reg_control_.ctl_reg_sys_we=0;
|
||
|
|
#2 pc=z.A;
|
||
|
|
#2
|
||
|
|
#1 force dut.reg_file_.reg_gp_we=0;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=1;
|
||
|
|
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h10) $fdisplay(f,"* Reg af f=%h !=10",dut.reg_file_.b2v_latch_af_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h9e) $fdisplay(f,"* Reg af a=%h !=9e",dut.reg_file_.b2v_latch_af_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h43) $fdisplay(f,"* Reg bc c=%h !=43",dut.reg_file_.b2v_latch_bc_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h1b) $fdisplay(f,"* Reg bc b=%h !=1b",dut.reg_file_.b2v_latch_bc_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h4e) $fdisplay(f,"* Reg de e=%h !=4e",dut.reg_file_.b2v_latch_de_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h95) $fdisplay(f,"* Reg de d=%h !=95",dut.reg_file_.b2v_latch_de_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'he9) $fdisplay(f,"* Reg hl l=%h !=e9",dut.reg_file_.b2v_latch_hl_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h7b) $fdisplay(f,"* Reg hl h=%h !=7b",dut.reg_file_.b2v_latch_hl_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
|
||
|
|
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
|
||
|
|
#1 // End opcode
|
||
|
|
|
||
|
|
force dut.ir_.ctl_ir_we=1;
|
||
|
|
force dut.ir_.db=0;
|
||
|
|
#2 release dut.ir_.ctl_ir_we;
|
||
|
|
release dut.ir_.db;
|
||
|
|
$fdisplay(f,"Testing opcode cb93 RES 2,E");
|
||
|
|
// Preset af
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.db=8'hc2;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.db;
|
||
|
|
// Preset bc
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.db=8'h05;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.db=8'h4e;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.db;
|
||
|
|
// Preset de
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.db=8'hf8;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.db=8'hb3;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.db;
|
||
|
|
// Preset hl
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.db=8'h34;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.db=8'h22;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.db;
|
||
|
|
// Preset af2
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.db;
|
||
|
|
// Preset bc2
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.db;
|
||
|
|
// Preset de2
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.db;
|
||
|
|
// Preset hl2
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.db;
|
||
|
|
// Preset ix
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.db;
|
||
|
|
// Preset iy
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.db;
|
||
|
|
// Preset sp
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.db;
|
||
|
|
// Preset wz
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.db;
|
||
|
|
// Preset pc
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.db;
|
||
|
|
// Preset ir
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.db;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[0] = 8'hcb;
|
||
|
|
ram.Mem[1] = 8'h93;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[8756] = 8'ha0;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=0;
|
||
|
|
force dut.address_latch_.Q=16'h0000;
|
||
|
|
release dut.reg_control_.ctl_reg_sys_we;
|
||
|
|
release dut.reg_file_.reg_gp_we;
|
||
|
|
#2 // Execute: M1/T1 start
|
||
|
|
#1 release dut.address_latch_.Q;
|
||
|
|
#1
|
||
|
|
#14 // Wait for opcode end
|
||
|
|
force dut.reg_control_.ctl_reg_sys_we=0;
|
||
|
|
#2 pc=z.A;
|
||
|
|
#2
|
||
|
|
#1 force dut.reg_file_.reg_gp_we=0;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=1;
|
||
|
|
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,"* Reg af f=%h !=00",dut.reg_file_.b2v_latch_af_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hc2) $fdisplay(f,"* Reg af a=%h !=c2",dut.reg_file_.b2v_latch_af_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h05) $fdisplay(f,"* Reg bc c=%h !=05",dut.reg_file_.b2v_latch_bc_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h4e) $fdisplay(f,"* Reg bc b=%h !=4e",dut.reg_file_.b2v_latch_bc_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hf8) $fdisplay(f,"* Reg de e=%h !=f8",dut.reg_file_.b2v_latch_de_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'hb3) $fdisplay(f,"* Reg de d=%h !=b3",dut.reg_file_.b2v_latch_de_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h34) $fdisplay(f,"* Reg hl l=%h !=34",dut.reg_file_.b2v_latch_hl_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h22) $fdisplay(f,"* Reg hl h=%h !=22",dut.reg_file_.b2v_latch_hl_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
|
||
|
|
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
|
||
|
|
#1 // End opcode
|
||
|
|
|
||
|
|
force dut.ir_.ctl_ir_we=1;
|
||
|
|
force dut.ir_.db=0;
|
||
|
|
#2 release dut.ir_.ctl_ir_we;
|
||
|
|
release dut.ir_.db;
|
||
|
|
$fdisplay(f,"Testing opcode cbe5 SET 4,L");
|
||
|
|
// Preset af
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.db=8'hca;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.db;
|
||
|
|
// Preset bc
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.db=8'h0d;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.db=8'hdf;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.db;
|
||
|
|
// Preset de
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.db=8'h88;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.db=8'hd5;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.db;
|
||
|
|
// Preset hl
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.db=8'h8f;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.db=8'hb4;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.db;
|
||
|
|
// Preset af2
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.db;
|
||
|
|
// Preset bc2
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.db;
|
||
|
|
// Preset de2
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.db;
|
||
|
|
// Preset hl2
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.db;
|
||
|
|
// Preset ix
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.db;
|
||
|
|
// Preset iy
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.db;
|
||
|
|
// Preset sp
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.db;
|
||
|
|
// Preset wz
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.db;
|
||
|
|
// Preset pc
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.db;
|
||
|
|
// Preset ir
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.db;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[0] = 8'hcb;
|
||
|
|
ram.Mem[1] = 8'he5;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[46223] = 8'hcf;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=0;
|
||
|
|
force dut.address_latch_.Q=16'h0000;
|
||
|
|
release dut.reg_control_.ctl_reg_sys_we;
|
||
|
|
release dut.reg_file_.reg_gp_we;
|
||
|
|
#2 // Execute: M1/T1 start
|
||
|
|
#1 release dut.address_latch_.Q;
|
||
|
|
#1
|
||
|
|
#14 // Wait for opcode end
|
||
|
|
force dut.reg_control_.ctl_reg_sys_we=0;
|
||
|
|
#2 pc=z.A;
|
||
|
|
#2
|
||
|
|
#1 force dut.reg_file_.reg_gp_we=0;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=1;
|
||
|
|
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,"* Reg af f=%h !=00",dut.reg_file_.b2v_latch_af_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hca) $fdisplay(f,"* Reg af a=%h !=ca",dut.reg_file_.b2v_latch_af_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h0d) $fdisplay(f,"* Reg bc c=%h !=0d",dut.reg_file_.b2v_latch_bc_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'hdf) $fdisplay(f,"* Reg bc b=%h !=df",dut.reg_file_.b2v_latch_bc_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h88) $fdisplay(f,"* Reg de e=%h !=88",dut.reg_file_.b2v_latch_de_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'hd5) $fdisplay(f,"* Reg de d=%h !=d5",dut.reg_file_.b2v_latch_de_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h9f) $fdisplay(f,"* Reg hl l=%h !=9f",dut.reg_file_.b2v_latch_hl_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hb4) $fdisplay(f,"* Reg hl h=%h !=b4",dut.reg_file_.b2v_latch_hl_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
|
||
|
|
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
|
||
|
|
#1 // End opcode
|
||
|
|
|
||
|
|
force dut.ir_.ctl_ir_we=1;
|
||
|
|
force dut.ir_.db=0;
|
||
|
|
#2 release dut.ir_.ctl_ir_we;
|
||
|
|
release dut.ir_.db;
|
||
|
|
$fdisplay(f,"Testing opcode 8c ADC A,H");
|
||
|
|
// Preset af
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.db;
|
||
|
|
// Preset bc
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.db;
|
||
|
|
// Preset de
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.db=8'h20;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.db;
|
||
|
|
// Preset hl
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.db;
|
||
|
|
// Preset af2
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.db;
|
||
|
|
// Preset bc2
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.db;
|
||
|
|
// Preset de2
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.db;
|
||
|
|
// Preset hl2
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.db;
|
||
|
|
// Preset ix
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.db;
|
||
|
|
// Preset iy
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.db;
|
||
|
|
// Preset sp
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.db;
|
||
|
|
// Preset wz
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.db;
|
||
|
|
// Preset pc
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.db;
|
||
|
|
// Preset ir
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.db;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[0] = 8'h8c;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[56486] = 8'h49;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=0;
|
||
|
|
force dut.address_latch_.Q=16'h0000;
|
||
|
|
release dut.reg_control_.ctl_reg_sys_we;
|
||
|
|
release dut.reg_file_.reg_gp_we;
|
||
|
|
#2 // Execute: M1/T1 start
|
||
|
|
#1 release dut.address_latch_.Q;
|
||
|
|
#1
|
||
|
|
#6 // Wait for opcode end
|
||
|
|
force dut.reg_control_.ctl_reg_sys_we=0;
|
||
|
|
#2 pc=z.A;
|
||
|
|
#2
|
||
|
|
#1 force dut.reg_file_.reg_gp_we=0;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=1;
|
||
|
|
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h91) $fdisplay(f,"* Reg af f=%h !=91",dut.reg_file_.b2v_latch_af_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hd1) $fdisplay(f,"* Reg af a=%h !=d1",dut.reg_file_.b2v_latch_af_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
|
||
|
|
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
|
||
|
|
#1 // End opcode
|
||
|
|
|
||
|
|
force dut.ir_.ctl_ir_we=1;
|
||
|
|
force dut.ir_.db=0;
|
||
|
|
#2 release dut.ir_.ctl_ir_we;
|
||
|
|
release dut.ir_.db;
|
||
|
|
$fdisplay(f,"Testing opcode 92 SUB D");
|
||
|
|
// Preset af
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.db;
|
||
|
|
// Preset bc
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.db;
|
||
|
|
// Preset de
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.db=8'h20;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.db;
|
||
|
|
// Preset hl
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.db;
|
||
|
|
// Preset af2
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.db;
|
||
|
|
// Preset bc2
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.db;
|
||
|
|
// Preset de2
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.db;
|
||
|
|
// Preset hl2
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.db;
|
||
|
|
// Preset ix
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.db;
|
||
|
|
// Preset iy
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.db;
|
||
|
|
// Preset sp
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.db;
|
||
|
|
// Preset wz
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.db;
|
||
|
|
// Preset pc
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.db;
|
||
|
|
// Preset ir
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.db;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[0] = 8'h92;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[56486] = 8'h49;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=0;
|
||
|
|
force dut.address_latch_.Q=16'h0000;
|
||
|
|
release dut.reg_control_.ctl_reg_sys_we;
|
||
|
|
release dut.reg_file_.reg_gp_we;
|
||
|
|
#2 // Execute: M1/T1 start
|
||
|
|
#1 release dut.address_latch_.Q;
|
||
|
|
#1
|
||
|
|
#6 // Wait for opcode end
|
||
|
|
force dut.reg_control_.ctl_reg_sys_we=0;
|
||
|
|
#2 pc=z.A;
|
||
|
|
#2
|
||
|
|
#1 force dut.reg_file_.reg_gp_we=0;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=1;
|
||
|
|
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h82) $fdisplay(f,"* Reg af f=%h !=82",dut.reg_file_.b2v_latch_af_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hd5) $fdisplay(f,"* Reg af a=%h !=d5",dut.reg_file_.b2v_latch_af_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
|
||
|
|
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
|
||
|
|
#1 // End opcode
|
||
|
|
|
||
|
|
force dut.ir_.ctl_ir_we=1;
|
||
|
|
force dut.ir_.db=0;
|
||
|
|
#2 release dut.ir_.ctl_ir_we;
|
||
|
|
release dut.ir_.db;
|
||
|
|
$fdisplay(f,"Testing opcode 9d SBC A,L");
|
||
|
|
// Preset af
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.db;
|
||
|
|
// Preset bc
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.db;
|
||
|
|
// Preset de
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.db=8'h20;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.db;
|
||
|
|
// Preset hl
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.db;
|
||
|
|
// Preset af2
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.db;
|
||
|
|
// Preset bc2
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.db;
|
||
|
|
// Preset de2
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.db;
|
||
|
|
// Preset hl2
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.db;
|
||
|
|
// Preset ix
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.db;
|
||
|
|
// Preset iy
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.db;
|
||
|
|
// Preset sp
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.db;
|
||
|
|
// Preset wz
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.db;
|
||
|
|
// Preset pc
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.db;
|
||
|
|
// Preset ir
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.db;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[0] = 8'h9d;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[56486] = 8'h49;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=0;
|
||
|
|
force dut.address_latch_.Q=16'h0000;
|
||
|
|
release dut.reg_control_.ctl_reg_sys_we;
|
||
|
|
release dut.reg_file_.reg_gp_we;
|
||
|
|
#2 // Execute: M1/T1 start
|
||
|
|
#1 release dut.address_latch_.Q;
|
||
|
|
#1
|
||
|
|
#6 // Wait for opcode end
|
||
|
|
force dut.reg_control_.ctl_reg_sys_we=0;
|
||
|
|
#2 pc=z.A;
|
||
|
|
#2
|
||
|
|
#1 force dut.reg_file_.reg_gp_we=0;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=1;
|
||
|
|
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h1a) $fdisplay(f,"* Reg af f=%h !=1a",dut.reg_file_.b2v_latch_af_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h4f) $fdisplay(f,"* Reg af a=%h !=4f",dut.reg_file_.b2v_latch_af_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
|
||
|
|
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
|
||
|
|
#1 // End opcode
|
||
|
|
|
||
|
|
force dut.ir_.ctl_ir_we=1;
|
||
|
|
force dut.ir_.db=0;
|
||
|
|
#2 release dut.ir_.ctl_ir_we;
|
||
|
|
release dut.ir_.db;
|
||
|
|
$fdisplay(f,"Testing opcode a3 AND E");
|
||
|
|
// Preset af
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.db;
|
||
|
|
// Preset bc
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.db;
|
||
|
|
// Preset de
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.db=8'h20;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.db;
|
||
|
|
// Preset hl
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.db;
|
||
|
|
// Preset af2
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.db;
|
||
|
|
// Preset bc2
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.db;
|
||
|
|
// Preset de2
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.db;
|
||
|
|
// Preset hl2
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.db;
|
||
|
|
// Preset ix
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.db;
|
||
|
|
// Preset iy
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.db;
|
||
|
|
// Preset sp
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.db;
|
||
|
|
// Preset wz
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.db;
|
||
|
|
// Preset pc
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.db;
|
||
|
|
// Preset ir
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.db;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[0] = 8'ha3;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[56486] = 8'h49;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=0;
|
||
|
|
force dut.address_latch_.Q=16'h0000;
|
||
|
|
release dut.reg_control_.ctl_reg_sys_we;
|
||
|
|
release dut.reg_file_.reg_gp_we;
|
||
|
|
#2 // Execute: M1/T1 start
|
||
|
|
#1 release dut.address_latch_.Q;
|
||
|
|
#1
|
||
|
|
#6 // Wait for opcode end
|
||
|
|
force dut.reg_control_.ctl_reg_sys_we=0;
|
||
|
|
#2 pc=z.A;
|
||
|
|
#2
|
||
|
|
#1 force dut.reg_file_.reg_gp_we=0;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=1;
|
||
|
|
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h14) $fdisplay(f,"* Reg af f=%h !=14",dut.reg_file_.b2v_latch_af_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h05) $fdisplay(f,"* Reg af a=%h !=05",dut.reg_file_.b2v_latch_af_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
|
||
|
|
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
|
||
|
|
#1 // End opcode
|
||
|
|
|
||
|
|
force dut.ir_.ctl_ir_we=1;
|
||
|
|
force dut.ir_.db=0;
|
||
|
|
#2 release dut.ir_.ctl_ir_we;
|
||
|
|
release dut.ir_.db;
|
||
|
|
$fdisplay(f,"Testing opcode ae XOR (HL)");
|
||
|
|
// Preset af
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.db;
|
||
|
|
// Preset bc
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.db;
|
||
|
|
// Preset de
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.db=8'h20;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.db;
|
||
|
|
// Preset hl
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.db;
|
||
|
|
// Preset af2
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.db;
|
||
|
|
// Preset bc2
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.db;
|
||
|
|
// Preset de2
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.db;
|
||
|
|
// Preset hl2
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.db;
|
||
|
|
// Preset ix
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.db;
|
||
|
|
// Preset iy
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.db;
|
||
|
|
// Preset sp
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.db;
|
||
|
|
// Preset wz
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.db;
|
||
|
|
// Preset pc
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.db;
|
||
|
|
// Preset ir
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.db;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[0] = 8'hae;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[56486] = 8'h49;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=0;
|
||
|
|
force dut.address_latch_.Q=16'h0000;
|
||
|
|
release dut.reg_control_.ctl_reg_sys_we;
|
||
|
|
release dut.reg_file_.reg_gp_we;
|
||
|
|
#2 // Execute: M1/T1 start
|
||
|
|
#1 release dut.address_latch_.Q;
|
||
|
|
#1
|
||
|
|
#12 // Wait for opcode end
|
||
|
|
force dut.reg_control_.ctl_reg_sys_we=0;
|
||
|
|
#2 pc=z.A;
|
||
|
|
#2
|
||
|
|
#1 force dut.reg_file_.reg_gp_we=0;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=1;
|
||
|
|
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'ha8) $fdisplay(f,"* Reg af f=%h !=a8",dut.reg_file_.b2v_latch_af_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hbc) $fdisplay(f,"* Reg af a=%h !=bc",dut.reg_file_.b2v_latch_af_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
|
||
|
|
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
|
||
|
|
#1 // End opcode
|
||
|
|
|
||
|
|
force dut.ir_.ctl_ir_we=1;
|
||
|
|
force dut.ir_.db=0;
|
||
|
|
#2 release dut.ir_.ctl_ir_we;
|
||
|
|
release dut.ir_.db;
|
||
|
|
$fdisplay(f,"Testing opcode b4 OR H");
|
||
|
|
// Preset af
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.db;
|
||
|
|
// Preset bc
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.db;
|
||
|
|
// Preset de
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.db=8'h20;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.db;
|
||
|
|
// Preset hl
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.db;
|
||
|
|
// Preset af2
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.db;
|
||
|
|
// Preset bc2
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.db;
|
||
|
|
// Preset de2
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.db;
|
||
|
|
// Preset hl2
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.db;
|
||
|
|
// Preset ix
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.db;
|
||
|
|
// Preset iy
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.db;
|
||
|
|
// Preset sp
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.db;
|
||
|
|
// Preset wz
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.db;
|
||
|
|
// Preset pc
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.db;
|
||
|
|
// Preset ir
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.db;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[0] = 8'hb4;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[56486] = 8'h49;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=0;
|
||
|
|
force dut.address_latch_.Q=16'h0000;
|
||
|
|
release dut.reg_control_.ctl_reg_sys_we;
|
||
|
|
release dut.reg_file_.reg_gp_we;
|
||
|
|
#2 // Execute: M1/T1 start
|
||
|
|
#1 release dut.address_latch_.Q;
|
||
|
|
#1
|
||
|
|
#6 // Wait for opcode end
|
||
|
|
force dut.reg_control_.ctl_reg_sys_we=0;
|
||
|
|
#2 pc=z.A;
|
||
|
|
#2
|
||
|
|
#1 force dut.reg_file_.reg_gp_we=0;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=1;
|
||
|
|
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'ha8) $fdisplay(f,"* Reg af f=%h !=a8",dut.reg_file_.b2v_latch_af_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hfd) $fdisplay(f,"* Reg af a=%h !=fd",dut.reg_file_.b2v_latch_af_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
|
||
|
|
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
|
||
|
|
#1 // End opcode
|
||
|
|
|
||
|
|
force dut.ir_.ctl_ir_we=1;
|
||
|
|
force dut.ir_.db=0;
|
||
|
|
#2 release dut.ir_.ctl_ir_we;
|
||
|
|
release dut.ir_.db;
|
||
|
|
$fdisplay(f,"Testing opcode bf CP A");
|
||
|
|
// Preset af
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.db;
|
||
|
|
// Preset bc
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.db;
|
||
|
|
// Preset de
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.db=8'h20;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.db;
|
||
|
|
// Preset hl
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.db;
|
||
|
|
// Preset af2
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.db;
|
||
|
|
// Preset bc2
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.db;
|
||
|
|
// Preset de2
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.db;
|
||
|
|
// Preset hl2
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.db;
|
||
|
|
// Preset ix
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.db;
|
||
|
|
// Preset iy
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.db;
|
||
|
|
// Preset sp
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.db;
|
||
|
|
// Preset wz
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.db;
|
||
|
|
// Preset pc
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.db;
|
||
|
|
// Preset ir
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.db;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[0] = 8'hbf;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[56486] = 8'h49;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=0;
|
||
|
|
force dut.address_latch_.Q=16'h0000;
|
||
|
|
release dut.reg_control_.ctl_reg_sys_we;
|
||
|
|
release dut.reg_file_.reg_gp_we;
|
||
|
|
#2 // Execute: M1/T1 start
|
||
|
|
#1 release dut.address_latch_.Q;
|
||
|
|
#1
|
||
|
|
#6 // Wait for opcode end
|
||
|
|
force dut.reg_control_.ctl_reg_sys_we=0;
|
||
|
|
#2 pc=z.A;
|
||
|
|
#2
|
||
|
|
#1 force dut.reg_file_.reg_gp_we=0;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=1;
|
||
|
|
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h62) $fdisplay(f,"* Reg af f=%h !=62",dut.reg_file_.b2v_latch_af_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hf5) $fdisplay(f,"* Reg af a=%h !=f5",dut.reg_file_.b2v_latch_af_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
|
||
|
|
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
|
||
|
|
#1 // End opcode
|
||
|
|
|
||
|
|
force dut.ir_.ctl_ir_we=1;
|
||
|
|
force dut.ir_.db=0;
|
||
|
|
#2 release dut.ir_.ctl_ir_we;
|
||
|
|
release dut.ir_.db;
|
||
|
|
$fdisplay(f,"Testing opcode 43 LD B,E");
|
||
|
|
// Preset af
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.db=8'h02;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.db;
|
||
|
|
// Preset bc
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.db=8'h98;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.db=8'hcf;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.db;
|
||
|
|
// Preset de
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.db=8'hd8;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.db=8'h90;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.db;
|
||
|
|
// Preset hl
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.db=8'h69;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.db=8'ha1;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.db;
|
||
|
|
// Preset af2
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.db;
|
||
|
|
// Preset bc2
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.db;
|
||
|
|
// Preset de2
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.db;
|
||
|
|
// Preset hl2
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.db;
|
||
|
|
// Preset ix
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.db;
|
||
|
|
// Preset iy
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.db;
|
||
|
|
// Preset sp
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.db;
|
||
|
|
// Preset wz
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.db;
|
||
|
|
// Preset pc
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.db;
|
||
|
|
// Preset ir
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.db;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[0] = 8'h43;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[41321] = 8'h50;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=0;
|
||
|
|
force dut.address_latch_.Q=16'h0000;
|
||
|
|
release dut.reg_control_.ctl_reg_sys_we;
|
||
|
|
release dut.reg_file_.reg_gp_we;
|
||
|
|
#2 // Execute: M1/T1 start
|
||
|
|
#1 release dut.address_latch_.Q;
|
||
|
|
#1
|
||
|
|
#6 // Wait for opcode end
|
||
|
|
force dut.reg_control_.ctl_reg_sys_we=0;
|
||
|
|
#2 pc=z.A;
|
||
|
|
#2
|
||
|
|
#1 force dut.reg_file_.reg_gp_we=0;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=1;
|
||
|
|
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,"* Reg af f=%h !=00",dut.reg_file_.b2v_latch_af_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h02) $fdisplay(f,"* Reg af a=%h !=02",dut.reg_file_.b2v_latch_af_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h98) $fdisplay(f,"* Reg bc c=%h !=98",dut.reg_file_.b2v_latch_bc_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'hd8) $fdisplay(f,"* Reg bc b=%h !=d8",dut.reg_file_.b2v_latch_bc_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hd8) $fdisplay(f,"* Reg de e=%h !=d8",dut.reg_file_.b2v_latch_de_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h90) $fdisplay(f,"* Reg de d=%h !=90",dut.reg_file_.b2v_latch_de_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h69) $fdisplay(f,"* Reg hl l=%h !=69",dut.reg_file_.b2v_latch_hl_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'ha1) $fdisplay(f,"* Reg hl h=%h !=a1",dut.reg_file_.b2v_latch_hl_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
|
||
|
|
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
|
||
|
|
#1 // End opcode
|
||
|
|
|
||
|
|
force dut.ir_.ctl_ir_we=1;
|
||
|
|
force dut.ir_.db=0;
|
||
|
|
#2 release dut.ir_.ctl_ir_we;
|
||
|
|
release dut.ir_.db;
|
||
|
|
$fdisplay(f,"Testing opcode 6e LD L,(HL)");
|
||
|
|
// Preset af
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.db=8'h02;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.db;
|
||
|
|
// Preset bc
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.db=8'h98;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.db=8'hcf;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.db;
|
||
|
|
// Preset de
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.db=8'hd8;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.db=8'h90;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.db;
|
||
|
|
// Preset hl
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.db=8'h69;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.db=8'ha1;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.db;
|
||
|
|
// Preset af2
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.db;
|
||
|
|
// Preset bc2
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.db;
|
||
|
|
// Preset de2
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.db;
|
||
|
|
// Preset hl2
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.db;
|
||
|
|
// Preset ix
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.db;
|
||
|
|
// Preset iy
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.db;
|
||
|
|
// Preset sp
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.db;
|
||
|
|
// Preset wz
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.db;
|
||
|
|
// Preset pc
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.db;
|
||
|
|
// Preset ir
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.db;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[0] = 8'h6e;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[41321] = 8'h50;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=0;
|
||
|
|
force dut.address_latch_.Q=16'h0000;
|
||
|
|
release dut.reg_control_.ctl_reg_sys_we;
|
||
|
|
release dut.reg_file_.reg_gp_we;
|
||
|
|
#2 // Execute: M1/T1 start
|
||
|
|
#1 release dut.address_latch_.Q;
|
||
|
|
#1
|
||
|
|
#12 // Wait for opcode end
|
||
|
|
force dut.reg_control_.ctl_reg_sys_we=0;
|
||
|
|
#2 pc=z.A;
|
||
|
|
#2
|
||
|
|
#1 force dut.reg_file_.reg_gp_we=0;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=1;
|
||
|
|
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,"* Reg af f=%h !=00",dut.reg_file_.b2v_latch_af_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h02) $fdisplay(f,"* Reg af a=%h !=02",dut.reg_file_.b2v_latch_af_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h98) $fdisplay(f,"* Reg bc c=%h !=98",dut.reg_file_.b2v_latch_bc_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'hcf) $fdisplay(f,"* Reg bc b=%h !=cf",dut.reg_file_.b2v_latch_bc_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hd8) $fdisplay(f,"* Reg de e=%h !=d8",dut.reg_file_.b2v_latch_de_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h90) $fdisplay(f,"* Reg de d=%h !=90",dut.reg_file_.b2v_latch_de_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h50) $fdisplay(f,"* Reg hl l=%h !=50",dut.reg_file_.b2v_latch_hl_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'ha1) $fdisplay(f,"* Reg hl h=%h !=a1",dut.reg_file_.b2v_latch_hl_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
|
||
|
|
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
|
||
|
|
#1 // End opcode
|
||
|
|
|
||
|
|
force dut.ir_.ctl_ir_we=1;
|
||
|
|
force dut.ir_.db=0;
|
||
|
|
#2 release dut.ir_.ctl_ir_we;
|
||
|
|
release dut.ir_.db;
|
||
|
|
$fdisplay(f,"Testing opcode e3 EX (SP),HL");
|
||
|
|
// Preset af
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.db;
|
||
|
|
// Preset bc
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.db;
|
||
|
|
// Preset de
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.db;
|
||
|
|
// Preset hl
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.db=8'h22;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.db=8'h4d;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.db;
|
||
|
|
// Preset af2
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.db;
|
||
|
|
// Preset bc2
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.db;
|
||
|
|
// Preset de2
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.db;
|
||
|
|
// Preset hl2
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.db;
|
||
|
|
// Preset ix
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.db;
|
||
|
|
// Preset iy
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.db;
|
||
|
|
// Preset sp
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.db=8'h73;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.db=8'h03;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.db;
|
||
|
|
// Preset wz
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.db;
|
||
|
|
// Preset pc
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.db;
|
||
|
|
// Preset ir
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.db;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[0] = 8'he3;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[883] = 8'h8e;
|
||
|
|
ram.Mem[884] = 8'he1;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=0;
|
||
|
|
force dut.address_latch_.Q=16'h0000;
|
||
|
|
release dut.reg_control_.ctl_reg_sys_we;
|
||
|
|
release dut.reg_file_.reg_gp_we;
|
||
|
|
#2 // Execute: M1/T1 start
|
||
|
|
#1 release dut.address_latch_.Q;
|
||
|
|
#1
|
||
|
|
#36 // Wait for opcode end
|
||
|
|
force dut.reg_control_.ctl_reg_sys_we=0;
|
||
|
|
#2 pc=z.A;
|
||
|
|
#2
|
||
|
|
#1 force dut.reg_file_.reg_gp_we=0;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=1;
|
||
|
|
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,"* Reg af f=%h !=00",dut.reg_file_.b2v_latch_af_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h00) $fdisplay(f,"* Reg af a=%h !=00",dut.reg_file_.b2v_latch_af_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h00) $fdisplay(f,"* Reg bc c=%h !=00",dut.reg_file_.b2v_latch_bc_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h00) $fdisplay(f,"* Reg bc b=%h !=00",dut.reg_file_.b2v_latch_bc_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h00) $fdisplay(f,"* Reg de e=%h !=00",dut.reg_file_.b2v_latch_de_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h00) $fdisplay(f,"* Reg de d=%h !=00",dut.reg_file_.b2v_latch_de_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h8e) $fdisplay(f,"* Reg hl l=%h !=8e",dut.reg_file_.b2v_latch_hl_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'he1) $fdisplay(f,"* Reg hl h=%h !=e1",dut.reg_file_.b2v_latch_hl_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h73) $fdisplay(f,"* Reg sp p=%h !=73",dut.reg_file_.b2v_latch_sp_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h03) $fdisplay(f,"* Reg sp s=%h !=03",dut.reg_file_.b2v_latch_sp_hi.latch);
|
||
|
|
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
|
||
|
|
if (ram.Mem[883]!==8'h22) $fdisplay(f,"* Mem[373]=%h !=22",ram.Mem[883]);
|
||
|
|
if (ram.Mem[884]!==8'h4d) $fdisplay(f,"* Mem[374]=%h !=4d",ram.Mem[884]);
|
||
|
|
#1 // End opcode
|
||
|
|
|
||
|
|
force dut.ir_.ctl_ir_we=1;
|
||
|
|
force dut.ir_.db=0;
|
||
|
|
#2 release dut.ir_.ctl_ir_we;
|
||
|
|
release dut.ir_.db;
|
||
|
|
$fdisplay(f,"Testing opcode 03 INC BC");
|
||
|
|
// Preset af
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.db;
|
||
|
|
// Preset bc
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.db=8'h9a;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.db=8'h78;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.db;
|
||
|
|
// Preset de
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.db;
|
||
|
|
// Preset hl
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.db;
|
||
|
|
// Preset af2
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.db;
|
||
|
|
// Preset bc2
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.db;
|
||
|
|
// Preset de2
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.db;
|
||
|
|
// Preset hl2
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.db;
|
||
|
|
// Preset ix
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.db;
|
||
|
|
// Preset iy
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.db;
|
||
|
|
// Preset sp
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.db;
|
||
|
|
// Preset wz
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.db;
|
||
|
|
// Preset pc
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.db;
|
||
|
|
// Preset ir
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.db;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[0] = 8'h03;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=0;
|
||
|
|
force dut.address_latch_.Q=16'h0000;
|
||
|
|
release dut.reg_control_.ctl_reg_sys_we;
|
||
|
|
release dut.reg_file_.reg_gp_we;
|
||
|
|
#2 // Execute: M1/T1 start
|
||
|
|
#1 release dut.address_latch_.Q;
|
||
|
|
#1
|
||
|
|
#10 // Wait for opcode end
|
||
|
|
force dut.reg_control_.ctl_reg_sys_we=0;
|
||
|
|
#2 pc=z.A;
|
||
|
|
#2
|
||
|
|
#1 force dut.reg_file_.reg_gp_we=0;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=1;
|
||
|
|
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,"* Reg af f=%h !=00",dut.reg_file_.b2v_latch_af_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h00) $fdisplay(f,"* Reg af a=%h !=00",dut.reg_file_.b2v_latch_af_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h9b) $fdisplay(f,"* Reg bc c=%h !=9b",dut.reg_file_.b2v_latch_bc_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h78) $fdisplay(f,"* Reg bc b=%h !=78",dut.reg_file_.b2v_latch_bc_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h00) $fdisplay(f,"* Reg de e=%h !=00",dut.reg_file_.b2v_latch_de_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h00) $fdisplay(f,"* Reg de d=%h !=00",dut.reg_file_.b2v_latch_de_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h00) $fdisplay(f,"* Reg hl l=%h !=00",dut.reg_file_.b2v_latch_hl_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h00) $fdisplay(f,"* Reg hl h=%h !=00",dut.reg_file_.b2v_latch_hl_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
|
||
|
|
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
|
||
|
|
#1 // End opcode
|
||
|
|
|
||
|
|
force dut.ir_.ctl_ir_we=1;
|
||
|
|
force dut.ir_.db=0;
|
||
|
|
#2 release dut.ir_.ctl_ir_we;
|
||
|
|
release dut.ir_.db;
|
||
|
|
$fdisplay(f,"Testing opcode 3b DEC SP");
|
||
|
|
// Preset af
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.db;
|
||
|
|
// Preset bc
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.db;
|
||
|
|
// Preset de
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.db;
|
||
|
|
// Preset hl
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.db;
|
||
|
|
// Preset af2
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.db;
|
||
|
|
// Preset bc2
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.db;
|
||
|
|
// Preset de2
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.db;
|
||
|
|
// Preset hl2
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.db;
|
||
|
|
// Preset ix
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.db;
|
||
|
|
// Preset iy
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.db;
|
||
|
|
// Preset sp
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.db=8'h36;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.db=8'h9d;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.db;
|
||
|
|
// Preset wz
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.db;
|
||
|
|
// Preset pc
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.db;
|
||
|
|
// Preset ir
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.db;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[0] = 8'h3b;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=0;
|
||
|
|
force dut.address_latch_.Q=16'h0000;
|
||
|
|
release dut.reg_control_.ctl_reg_sys_we;
|
||
|
|
release dut.reg_file_.reg_gp_we;
|
||
|
|
#2 // Execute: M1/T1 start
|
||
|
|
#1 release dut.address_latch_.Q;
|
||
|
|
#1
|
||
|
|
#10 // Wait for opcode end
|
||
|
|
force dut.reg_control_.ctl_reg_sys_we=0;
|
||
|
|
#2 pc=z.A;
|
||
|
|
#2
|
||
|
|
#1 force dut.reg_file_.reg_gp_we=0;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=1;
|
||
|
|
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,"* Reg af f=%h !=00",dut.reg_file_.b2v_latch_af_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h00) $fdisplay(f,"* Reg af a=%h !=00",dut.reg_file_.b2v_latch_af_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h00) $fdisplay(f,"* Reg bc c=%h !=00",dut.reg_file_.b2v_latch_bc_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h00) $fdisplay(f,"* Reg bc b=%h !=00",dut.reg_file_.b2v_latch_bc_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h00) $fdisplay(f,"* Reg de e=%h !=00",dut.reg_file_.b2v_latch_de_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h00) $fdisplay(f,"* Reg de d=%h !=00",dut.reg_file_.b2v_latch_de_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h00) $fdisplay(f,"* Reg hl l=%h !=00",dut.reg_file_.b2v_latch_hl_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h00) $fdisplay(f,"* Reg hl h=%h !=00",dut.reg_file_.b2v_latch_hl_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h35) $fdisplay(f,"* Reg sp p=%h !=35",dut.reg_file_.b2v_latch_sp_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h9d) $fdisplay(f,"* Reg sp s=%h !=9d",dut.reg_file_.b2v_latch_sp_hi.latch);
|
||
|
|
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
|
||
|
|
#1 // End opcode
|
||
|
|
|
||
|
|
force dut.ir_.ctl_ir_we=1;
|
||
|
|
force dut.ir_.db=0;
|
||
|
|
#2 release dut.ir_.ctl_ir_we;
|
||
|
|
release dut.ir_.db;
|
||
|
|
$fdisplay(f,"Testing opcode 07 RLCA");
|
||
|
|
// Preset af
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.db=8'h88;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.db;
|
||
|
|
// Preset bc
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.db;
|
||
|
|
// Preset de
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.db;
|
||
|
|
// Preset hl
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.db;
|
||
|
|
// Preset af2
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.db;
|
||
|
|
// Preset bc2
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.db;
|
||
|
|
// Preset de2
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.db;
|
||
|
|
// Preset hl2
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.db;
|
||
|
|
// Preset ix
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.db;
|
||
|
|
// Preset iy
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.db;
|
||
|
|
// Preset sp
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.db;
|
||
|
|
// Preset wz
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.db;
|
||
|
|
// Preset pc
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.db;
|
||
|
|
// Preset ir
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.db;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[0] = 8'h07;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=0;
|
||
|
|
force dut.address_latch_.Q=16'h0000;
|
||
|
|
release dut.reg_control_.ctl_reg_sys_we;
|
||
|
|
release dut.reg_file_.reg_gp_we;
|
||
|
|
#2 // Execute: M1/T1 start
|
||
|
|
#1 release dut.address_latch_.Q;
|
||
|
|
#1
|
||
|
|
#6 // Wait for opcode end
|
||
|
|
force dut.reg_control_.ctl_reg_sys_we=0;
|
||
|
|
#2 pc=z.A;
|
||
|
|
#2
|
||
|
|
#1 force dut.reg_file_.reg_gp_we=0;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=1;
|
||
|
|
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h01) $fdisplay(f,"* Reg af f=%h !=01",dut.reg_file_.b2v_latch_af_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h11) $fdisplay(f,"* Reg af a=%h !=11",dut.reg_file_.b2v_latch_af_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h00) $fdisplay(f,"* Reg bc c=%h !=00",dut.reg_file_.b2v_latch_bc_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h00) $fdisplay(f,"* Reg bc b=%h !=00",dut.reg_file_.b2v_latch_bc_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h00) $fdisplay(f,"* Reg de e=%h !=00",dut.reg_file_.b2v_latch_de_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h00) $fdisplay(f,"* Reg de d=%h !=00",dut.reg_file_.b2v_latch_de_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h00) $fdisplay(f,"* Reg hl l=%h !=00",dut.reg_file_.b2v_latch_hl_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h00) $fdisplay(f,"* Reg hl h=%h !=00",dut.reg_file_.b2v_latch_hl_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
|
||
|
|
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
|
||
|
|
#1 // End opcode
|
||
|
|
|
||
|
|
force dut.ir_.ctl_ir_we=1;
|
||
|
|
force dut.ir_.db=0;
|
||
|
|
#2 release dut.ir_.ctl_ir_we;
|
||
|
|
release dut.ir_.db;
|
||
|
|
$fdisplay(f,"Testing opcode 1f RRA");
|
||
|
|
// Preset af
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.db=8'hc4;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.db=8'h01;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.db;
|
||
|
|
// Preset bc
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.db;
|
||
|
|
// Preset de
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.db;
|
||
|
|
// Preset hl
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.db;
|
||
|
|
// Preset af2
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.db;
|
||
|
|
// Preset bc2
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.db;
|
||
|
|
// Preset de2
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.db;
|
||
|
|
// Preset hl2
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.db;
|
||
|
|
// Preset ix
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.db;
|
||
|
|
// Preset iy
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.db;
|
||
|
|
// Preset sp
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.db;
|
||
|
|
// Preset wz
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.db;
|
||
|
|
// Preset pc
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.db;
|
||
|
|
// Preset ir
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.db;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[0] = 8'h1f;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=0;
|
||
|
|
force dut.address_latch_.Q=16'h0000;
|
||
|
|
release dut.reg_control_.ctl_reg_sys_we;
|
||
|
|
release dut.reg_file_.reg_gp_we;
|
||
|
|
#2 // Execute: M1/T1 start
|
||
|
|
#1 release dut.address_latch_.Q;
|
||
|
|
#1
|
||
|
|
#6 // Wait for opcode end
|
||
|
|
force dut.reg_control_.ctl_reg_sys_we=0;
|
||
|
|
#2 pc=z.A;
|
||
|
|
#2
|
||
|
|
#1 force dut.reg_file_.reg_gp_we=0;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=1;
|
||
|
|
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'hc5) $fdisplay(f,"* Reg af f=%h !=c5",dut.reg_file_.b2v_latch_af_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h00) $fdisplay(f,"* Reg af a=%h !=00",dut.reg_file_.b2v_latch_af_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h00) $fdisplay(f,"* Reg bc c=%h !=00",dut.reg_file_.b2v_latch_bc_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h00) $fdisplay(f,"* Reg bc b=%h !=00",dut.reg_file_.b2v_latch_bc_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h00) $fdisplay(f,"* Reg de e=%h !=00",dut.reg_file_.b2v_latch_de_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h00) $fdisplay(f,"* Reg de d=%h !=00",dut.reg_file_.b2v_latch_de_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h00) $fdisplay(f,"* Reg hl l=%h !=00",dut.reg_file_.b2v_latch_hl_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h00) $fdisplay(f,"* Reg hl h=%h !=00",dut.reg_file_.b2v_latch_hl_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
|
||
|
|
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
|
||
|
|
#1 // End opcode
|
||
|
|
|
||
|
|
force dut.ir_.ctl_ir_we=1;
|
||
|
|
force dut.ir_.db=0;
|
||
|
|
#2 release dut.ir_.ctl_ir_we;
|
||
|
|
release dut.ir_.db;
|
||
|
|
$fdisplay(f,"Testing opcode cb09 RRC C");
|
||
|
|
// Preset af
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.db=8'h18;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.db;
|
||
|
|
// Preset bc
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.db=8'h5c;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.db=8'h12;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.db;
|
||
|
|
// Preset de
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.db=8'h97;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.db=8'hdd;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.db;
|
||
|
|
// Preset hl
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.db=8'hc6;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.db=8'h59;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.db;
|
||
|
|
// Preset af2
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.db;
|
||
|
|
// Preset bc2
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.db;
|
||
|
|
// Preset de2
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.db;
|
||
|
|
// Preset hl2
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.db;
|
||
|
|
// Preset ix
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.db;
|
||
|
|
// Preset iy
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.db;
|
||
|
|
// Preset sp
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.db;
|
||
|
|
// Preset wz
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.db;
|
||
|
|
// Preset pc
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.db;
|
||
|
|
// Preset ir
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.db;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[0] = 8'hcb;
|
||
|
|
ram.Mem[1] = 8'h09;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[22982] = 8'h9e;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=0;
|
||
|
|
force dut.address_latch_.Q=16'h0000;
|
||
|
|
release dut.reg_control_.ctl_reg_sys_we;
|
||
|
|
release dut.reg_file_.reg_gp_we;
|
||
|
|
#2 // Execute: M1/T1 start
|
||
|
|
#1 release dut.address_latch_.Q;
|
||
|
|
#1
|
||
|
|
#14 // Wait for opcode end
|
||
|
|
force dut.reg_control_.ctl_reg_sys_we=0;
|
||
|
|
#2 pc=z.A;
|
||
|
|
#2
|
||
|
|
#1 force dut.reg_file_.reg_gp_we=0;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=1;
|
||
|
|
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h2c) $fdisplay(f,"* Reg af f=%h !=2c",dut.reg_file_.b2v_latch_af_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h18) $fdisplay(f,"* Reg af a=%h !=18",dut.reg_file_.b2v_latch_af_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h2e) $fdisplay(f,"* Reg bc c=%h !=2e",dut.reg_file_.b2v_latch_bc_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h12) $fdisplay(f,"* Reg bc b=%h !=12",dut.reg_file_.b2v_latch_bc_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h97) $fdisplay(f,"* Reg de e=%h !=97",dut.reg_file_.b2v_latch_de_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'hdd) $fdisplay(f,"* Reg de d=%h !=dd",dut.reg_file_.b2v_latch_de_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'hc6) $fdisplay(f,"* Reg hl l=%h !=c6",dut.reg_file_.b2v_latch_hl_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h59) $fdisplay(f,"* Reg hl h=%h !=59",dut.reg_file_.b2v_latch_hl_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
|
||
|
|
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
|
||
|
|
#1 // End opcode
|
||
|
|
|
||
|
|
force dut.ir_.ctl_ir_we=1;
|
||
|
|
force dut.ir_.db=0;
|
||
|
|
#2 release dut.ir_.ctl_ir_we;
|
||
|
|
release dut.ir_.db;
|
||
|
|
$fdisplay(f,"Testing opcode cb11 RL C");
|
||
|
|
// Preset af
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.db=8'h65;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.db;
|
||
|
|
// Preset bc
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.db=8'h5c;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.db=8'he2;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.db;
|
||
|
|
// Preset de
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.db=8'h8a;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.db=8'h4b;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.db;
|
||
|
|
// Preset hl
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.db=8'h42;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.db=8'hed;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.db;
|
||
|
|
// Preset af2
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.db;
|
||
|
|
// Preset bc2
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.db;
|
||
|
|
// Preset de2
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.db;
|
||
|
|
// Preset hl2
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.db;
|
||
|
|
// Preset ix
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.db;
|
||
|
|
// Preset iy
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.db;
|
||
|
|
// Preset sp
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.db;
|
||
|
|
// Preset wz
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.db;
|
||
|
|
// Preset pc
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.db;
|
||
|
|
// Preset ir
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.db;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[0] = 8'hcb;
|
||
|
|
ram.Mem[1] = 8'h11;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[60738] = 8'hb7;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=0;
|
||
|
|
force dut.address_latch_.Q=16'h0000;
|
||
|
|
release dut.reg_control_.ctl_reg_sys_we;
|
||
|
|
release dut.reg_file_.reg_gp_we;
|
||
|
|
#2 // Execute: M1/T1 start
|
||
|
|
#1 release dut.address_latch_.Q;
|
||
|
|
#1
|
||
|
|
#14 // Wait for opcode end
|
||
|
|
force dut.reg_control_.ctl_reg_sys_we=0;
|
||
|
|
#2 pc=z.A;
|
||
|
|
#2
|
||
|
|
#1 force dut.reg_file_.reg_gp_we=0;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=1;
|
||
|
|
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'hac) $fdisplay(f,"* Reg af f=%h !=ac",dut.reg_file_.b2v_latch_af_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h65) $fdisplay(f,"* Reg af a=%h !=65",dut.reg_file_.b2v_latch_af_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'hb8) $fdisplay(f,"* Reg bc c=%h !=b8",dut.reg_file_.b2v_latch_bc_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'he2) $fdisplay(f,"* Reg bc b=%h !=e2",dut.reg_file_.b2v_latch_bc_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h8a) $fdisplay(f,"* Reg de e=%h !=8a",dut.reg_file_.b2v_latch_de_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h4b) $fdisplay(f,"* Reg de d=%h !=4b",dut.reg_file_.b2v_latch_de_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h42) $fdisplay(f,"* Reg hl l=%h !=42",dut.reg_file_.b2v_latch_hl_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hed) $fdisplay(f,"* Reg hl h=%h !=ed",dut.reg_file_.b2v_latch_hl_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
|
||
|
|
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
|
||
|
|
#1 // End opcode
|
||
|
|
|
||
|
|
force dut.ir_.ctl_ir_we=1;
|
||
|
|
force dut.ir_.db=0;
|
||
|
|
#2 release dut.ir_.ctl_ir_we;
|
||
|
|
release dut.ir_.db;
|
||
|
|
$fdisplay(f,"Testing opcode cb36 SLL (HL)*");
|
||
|
|
// Preset af
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.db=8'h8a;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.db;
|
||
|
|
// Preset bc
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.db=8'h85;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.db=8'h11;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.db;
|
||
|
|
// Preset de
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.db=8'hde;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.db=8'h1d;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.db;
|
||
|
|
// Preset hl
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.db=8'h38;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.db=8'h6d;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.db;
|
||
|
|
// Preset af2
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.db;
|
||
|
|
// Preset bc2
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.db;
|
||
|
|
// Preset de2
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.db;
|
||
|
|
// Preset hl2
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.db;
|
||
|
|
// Preset ix
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.db;
|
||
|
|
// Preset iy
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.db;
|
||
|
|
// Preset sp
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.db;
|
||
|
|
// Preset wz
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.db;
|
||
|
|
// Preset pc
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.db;
|
||
|
|
// Preset ir
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.db;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[0] = 8'hcb;
|
||
|
|
ram.Mem[1] = 8'h36;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[27960] = 8'hf1;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=0;
|
||
|
|
force dut.address_latch_.Q=16'h0000;
|
||
|
|
release dut.reg_control_.ctl_reg_sys_we;
|
||
|
|
release dut.reg_file_.reg_gp_we;
|
||
|
|
#2 // Execute: M1/T1 start
|
||
|
|
#1 release dut.address_latch_.Q;
|
||
|
|
#1
|
||
|
|
#28 // Wait for opcode end
|
||
|
|
force dut.reg_control_.ctl_reg_sys_we=0;
|
||
|
|
#2 pc=z.A;
|
||
|
|
#2
|
||
|
|
#1 force dut.reg_file_.reg_gp_we=0;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=1;
|
||
|
|
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'ha1) $fdisplay(f,"* Reg af f=%h !=a1",dut.reg_file_.b2v_latch_af_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h8a) $fdisplay(f,"* Reg af a=%h !=8a",dut.reg_file_.b2v_latch_af_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h85) $fdisplay(f,"* Reg bc c=%h !=85",dut.reg_file_.b2v_latch_bc_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h11) $fdisplay(f,"* Reg bc b=%h !=11",dut.reg_file_.b2v_latch_bc_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hde) $fdisplay(f,"* Reg de e=%h !=de",dut.reg_file_.b2v_latch_de_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h1d) $fdisplay(f,"* Reg de d=%h !=1d",dut.reg_file_.b2v_latch_de_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h38) $fdisplay(f,"* Reg hl l=%h !=38",dut.reg_file_.b2v_latch_hl_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h6d) $fdisplay(f,"* Reg hl h=%h !=6d",dut.reg_file_.b2v_latch_hl_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
|
||
|
|
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
|
||
|
|
if (ram.Mem[27960]!==8'he3) $fdisplay(f,"* Mem[6d38]=%h !=e3",ram.Mem[27960]);
|
||
|
|
#1 // End opcode
|
||
|
|
|
||
|
|
force dut.ir_.ctl_ir_we=1;
|
||
|
|
force dut.ir_.db=0;
|
||
|
|
#2 release dut.ir_.ctl_ir_we;
|
||
|
|
release dut.ir_.db;
|
||
|
|
$fdisplay(f,"Testing opcode cb52 BIT 2,D");
|
||
|
|
// Preset af
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.db=8'h8b;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.db;
|
||
|
|
// Preset bc
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.db=8'h7a;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.db=8'hff;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.db;
|
||
|
|
// Preset de
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.db=8'hff;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.db=8'hb0;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.db;
|
||
|
|
// Preset hl
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.db=8'h44;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.db=8'hac;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.db;
|
||
|
|
// Preset af2
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.db;
|
||
|
|
// Preset bc2
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.db;
|
||
|
|
// Preset de2
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.db;
|
||
|
|
// Preset hl2
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.db;
|
||
|
|
// Preset ix
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.db;
|
||
|
|
// Preset iy
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.db;
|
||
|
|
// Preset sp
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.db;
|
||
|
|
// Preset wz
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.db;
|
||
|
|
// Preset pc
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.db;
|
||
|
|
// Preset ir
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.db;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[0] = 8'hcb;
|
||
|
|
ram.Mem[1] = 8'h52;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[44100] = 8'h00;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=0;
|
||
|
|
force dut.address_latch_.Q=16'h0000;
|
||
|
|
release dut.reg_control_.ctl_reg_sys_we;
|
||
|
|
release dut.reg_file_.reg_gp_we;
|
||
|
|
#2 // Execute: M1/T1 start
|
||
|
|
#1 release dut.address_latch_.Q;
|
||
|
|
#1
|
||
|
|
#14 // Wait for opcode end
|
||
|
|
force dut.reg_control_.ctl_reg_sys_we=0;
|
||
|
|
#2 pc=z.A;
|
||
|
|
#2
|
||
|
|
#1 force dut.reg_file_.reg_gp_we=0;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=1;
|
||
|
|
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h74) $fdisplay(f,"* Reg af f=%h !=74",dut.reg_file_.b2v_latch_af_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h8b) $fdisplay(f,"* Reg af a=%h !=8b",dut.reg_file_.b2v_latch_af_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h7a) $fdisplay(f,"* Reg bc c=%h !=7a",dut.reg_file_.b2v_latch_bc_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'hff) $fdisplay(f,"* Reg bc b=%h !=ff",dut.reg_file_.b2v_latch_bc_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hff) $fdisplay(f,"* Reg de e=%h !=ff",dut.reg_file_.b2v_latch_de_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'hb0) $fdisplay(f,"* Reg de d=%h !=b0",dut.reg_file_.b2v_latch_de_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h44) $fdisplay(f,"* Reg hl l=%h !=44",dut.reg_file_.b2v_latch_hl_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hac) $fdisplay(f,"* Reg hl h=%h !=ac",dut.reg_file_.b2v_latch_hl_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
|
||
|
|
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
|
||
|
|
#1 // End opcode
|
||
|
|
|
||
|
|
force dut.ir_.ctl_ir_we=1;
|
||
|
|
force dut.ir_.db=0;
|
||
|
|
#2 release dut.ir_.ctl_ir_we;
|
||
|
|
release dut.ir_.db;
|
||
|
|
$fdisplay(f,"Testing opcode cb93 RES 2,E");
|
||
|
|
// Preset af
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.db=8'hc2;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.db;
|
||
|
|
// Preset bc
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.db=8'h05;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.db=8'h4e;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.db;
|
||
|
|
// Preset de
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.db=8'hf8;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.db=8'hb3;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.db;
|
||
|
|
// Preset hl
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.db=8'h34;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.db=8'h22;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.db;
|
||
|
|
// Preset af2
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.db;
|
||
|
|
// Preset bc2
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.db;
|
||
|
|
// Preset de2
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.db;
|
||
|
|
// Preset hl2
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.db;
|
||
|
|
// Preset ix
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.db;
|
||
|
|
// Preset iy
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.db;
|
||
|
|
// Preset sp
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.db;
|
||
|
|
// Preset wz
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.db;
|
||
|
|
// Preset pc
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.db;
|
||
|
|
// Preset ir
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.db;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[0] = 8'hcb;
|
||
|
|
ram.Mem[1] = 8'h93;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[8756] = 8'ha0;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=0;
|
||
|
|
force dut.address_latch_.Q=16'h0000;
|
||
|
|
release dut.reg_control_.ctl_reg_sys_we;
|
||
|
|
release dut.reg_file_.reg_gp_we;
|
||
|
|
#2 // Execute: M1/T1 start
|
||
|
|
#1 release dut.address_latch_.Q;
|
||
|
|
#1
|
||
|
|
#14 // Wait for opcode end
|
||
|
|
force dut.reg_control_.ctl_reg_sys_we=0;
|
||
|
|
#2 pc=z.A;
|
||
|
|
#2
|
||
|
|
#1 force dut.reg_file_.reg_gp_we=0;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=1;
|
||
|
|
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,"* Reg af f=%h !=00",dut.reg_file_.b2v_latch_af_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hc2) $fdisplay(f,"* Reg af a=%h !=c2",dut.reg_file_.b2v_latch_af_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h05) $fdisplay(f,"* Reg bc c=%h !=05",dut.reg_file_.b2v_latch_bc_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h4e) $fdisplay(f,"* Reg bc b=%h !=4e",dut.reg_file_.b2v_latch_bc_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hf8) $fdisplay(f,"* Reg de e=%h !=f8",dut.reg_file_.b2v_latch_de_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'hb3) $fdisplay(f,"* Reg de d=%h !=b3",dut.reg_file_.b2v_latch_de_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h34) $fdisplay(f,"* Reg hl l=%h !=34",dut.reg_file_.b2v_latch_hl_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h22) $fdisplay(f,"* Reg hl h=%h !=22",dut.reg_file_.b2v_latch_hl_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
|
||
|
|
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
|
||
|
|
#1 // End opcode
|
||
|
|
|
||
|
|
force dut.ir_.ctl_ir_we=1;
|
||
|
|
force dut.ir_.db=0;
|
||
|
|
#2 release dut.ir_.ctl_ir_we;
|
||
|
|
release dut.ir_.db;
|
||
|
|
$fdisplay(f,"Testing opcode cbc4 SET 0,H");
|
||
|
|
// Preset af
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.db=8'h7e;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.db;
|
||
|
|
// Preset bc
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.db=8'h5a;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.db=8'h54;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.db;
|
||
|
|
// Preset de
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.db=8'hcf;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.db=8'h6e;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.db;
|
||
|
|
// Preset hl
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.db=8'h76;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.db=8'h58;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.db;
|
||
|
|
// Preset af2
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.db;
|
||
|
|
// Preset bc2
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.db;
|
||
|
|
// Preset de2
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.db;
|
||
|
|
// Preset hl2
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.db;
|
||
|
|
// Preset ix
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.db;
|
||
|
|
// Preset iy
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.db;
|
||
|
|
// Preset sp
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.db;
|
||
|
|
// Preset wz
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.db;
|
||
|
|
// Preset pc
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.db;
|
||
|
|
// Preset ir
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.db;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[0] = 8'hcb;
|
||
|
|
ram.Mem[1] = 8'hc4;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[22646] = 8'h9d;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=0;
|
||
|
|
force dut.address_latch_.Q=16'h0000;
|
||
|
|
release dut.reg_control_.ctl_reg_sys_we;
|
||
|
|
release dut.reg_file_.reg_gp_we;
|
||
|
|
#2 // Execute: M1/T1 start
|
||
|
|
#1 release dut.address_latch_.Q;
|
||
|
|
#1
|
||
|
|
#14 // Wait for opcode end
|
||
|
|
force dut.reg_control_.ctl_reg_sys_we=0;
|
||
|
|
#2 pc=z.A;
|
||
|
|
#2
|
||
|
|
#1 force dut.reg_file_.reg_gp_we=0;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=1;
|
||
|
|
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,"* Reg af f=%h !=00",dut.reg_file_.b2v_latch_af_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h7e) $fdisplay(f,"* Reg af a=%h !=7e",dut.reg_file_.b2v_latch_af_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h5a) $fdisplay(f,"* Reg bc c=%h !=5a",dut.reg_file_.b2v_latch_bc_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h54) $fdisplay(f,"* Reg bc b=%h !=54",dut.reg_file_.b2v_latch_bc_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hcf) $fdisplay(f,"* Reg de e=%h !=cf",dut.reg_file_.b2v_latch_de_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h6e) $fdisplay(f,"* Reg de d=%h !=6e",dut.reg_file_.b2v_latch_de_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h76) $fdisplay(f,"* Reg hl l=%h !=76",dut.reg_file_.b2v_latch_hl_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h59) $fdisplay(f,"* Reg hl h=%h !=59",dut.reg_file_.b2v_latch_hl_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
|
||
|
|
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
|
||
|
|
#1 // End opcode
|
||
|
|
|
||
|
|
force dut.ir_.ctl_ir_we=1;
|
||
|
|
force dut.ir_.db=0;
|
||
|
|
#2 release dut.ir_.ctl_ir_we;
|
||
|
|
release dut.ir_.db;
|
||
|
|
$fdisplay(f,"Testing opcode dd75 LD (IX+d),L");
|
||
|
|
// Preset af
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.db=8'h72;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.db=8'h57;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.db;
|
||
|
|
// Preset bc
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.db=8'h33;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.db=8'he8;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.db;
|
||
|
|
// Preset de
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.db=8'h3e;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.db=8'hb6;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.db;
|
||
|
|
// Preset hl
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.db=8'h4f;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.db=8'h73;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.db;
|
||
|
|
// Preset af2
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.db;
|
||
|
|
// Preset bc2
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.db;
|
||
|
|
// Preset de2
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.db;
|
||
|
|
// Preset hl2
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.db;
|
||
|
|
// Preset ix
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.db=8'h4c;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.db=8'hae;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.db;
|
||
|
|
// Preset iy
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.db=8'hc2;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.db=8'he8;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.db;
|
||
|
|
// Preset sp
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.db;
|
||
|
|
// Preset wz
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.db;
|
||
|
|
// Preset pc
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.db;
|
||
|
|
// Preset ir
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.db;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[0] = 8'hdd;
|
||
|
|
ram.Mem[1] = 8'h75;
|
||
|
|
ram.Mem[2] = 8'h30;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=0;
|
||
|
|
force dut.address_latch_.Q=16'h0000;
|
||
|
|
release dut.reg_control_.ctl_reg_sys_we;
|
||
|
|
release dut.reg_file_.reg_gp_we;
|
||
|
|
#2 // Execute: M1/T1 start
|
||
|
|
#1 release dut.address_latch_.Q;
|
||
|
|
#1
|
||
|
|
#36 // Wait for opcode end
|
||
|
|
force dut.reg_control_.ctl_reg_sys_we=0;
|
||
|
|
#2 pc=z.A;
|
||
|
|
#2
|
||
|
|
#1 force dut.reg_file_.reg_gp_we=0;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=1;
|
||
|
|
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h72) $fdisplay(f,"* Reg af f=%h !=72",dut.reg_file_.b2v_latch_af_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h57) $fdisplay(f,"* Reg af a=%h !=57",dut.reg_file_.b2v_latch_af_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h33) $fdisplay(f,"* Reg bc c=%h !=33",dut.reg_file_.b2v_latch_bc_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'he8) $fdisplay(f,"* Reg bc b=%h !=e8",dut.reg_file_.b2v_latch_bc_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h3e) $fdisplay(f,"* Reg de e=%h !=3e",dut.reg_file_.b2v_latch_de_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'hb6) $fdisplay(f,"* Reg de d=%h !=b6",dut.reg_file_.b2v_latch_de_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h4f) $fdisplay(f,"* Reg hl l=%h !=4f",dut.reg_file_.b2v_latch_hl_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h73) $fdisplay(f,"* Reg hl h=%h !=73",dut.reg_file_.b2v_latch_hl_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h4c) $fdisplay(f,"* Reg ix x=%h !=4c",dut.reg_file_.b2v_latch_ix_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'hae) $fdisplay(f,"* Reg ix i=%h !=ae",dut.reg_file_.b2v_latch_ix_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'hc2) $fdisplay(f,"* Reg iy y=%h !=c2",dut.reg_file_.b2v_latch_iy_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'he8) $fdisplay(f,"* Reg iy i=%h !=e8",dut.reg_file_.b2v_latch_iy_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
|
||
|
|
if (pc!==16'h0003) $fdisplay(f,"* PC=%h !=0003",pc);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
|
||
|
|
if (ram.Mem[44668]!==8'h4f) $fdisplay(f,"* Mem[ae7c]=%h !=4f",ram.Mem[44668]);
|
||
|
|
#1 // End opcode
|
||
|
|
|
||
|
|
force dut.ir_.ctl_ir_we=1;
|
||
|
|
force dut.ir_.db=0;
|
||
|
|
#2 release dut.ir_.ctl_ir_we;
|
||
|
|
release dut.ir_.db;
|
||
|
|
$fdisplay(f,"Testing opcode dd4e LD C,(IX+d)");
|
||
|
|
// Preset af
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af_lo.db=8'hf7;
|
||
|
|
force dut.reg_file_.b2v_latch_af_hi.db=8'h7b;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af_hi.db;
|
||
|
|
// Preset bc
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_lo.db=8'h05;
|
||
|
|
force dut.reg_file_.b2v_latch_bc_hi.db=8'h66;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc_hi.db;
|
||
|
|
// Preset de
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de_lo.db=8'h55;
|
||
|
|
force dut.reg_file_.b2v_latch_de_hi.db=8'h8d;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de_hi.db;
|
||
|
|
// Preset hl
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_lo.db=8'hf2;
|
||
|
|
force dut.reg_file_.b2v_latch_hl_hi.db=8'hde;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl_hi.db;
|
||
|
|
// Preset af2
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_af2_hi.db;
|
||
|
|
// Preset bc2
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_bc2_hi.db;
|
||
|
|
// Preset de2
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_de2_hi.db;
|
||
|
|
// Preset hl2
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_hl2_hi.db;
|
||
|
|
// Preset ix
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_lo.db=8'h4b;
|
||
|
|
force dut.reg_file_.b2v_latch_ix_hi.db=8'hd9;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ix_hi.db;
|
||
|
|
// Preset iy
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_lo.db=8'hfb;
|
||
|
|
force dut.reg_file_.b2v_latch_iy_hi.db=8'h17;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_iy_hi.db;
|
||
|
|
// Preset sp
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_sp_hi.db;
|
||
|
|
// Preset wz
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_wz_hi.db;
|
||
|
|
// Preset pc
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_pc_hi.db;
|
||
|
|
// Preset ir
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.we=1;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
|
||
|
|
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
|
||
|
|
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.we;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_lo.db;
|
||
|
|
release dut.reg_file_.b2v_latch_ir_hi.db;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[0] = 8'hdd;
|
||
|
|
ram.Mem[1] = 8'h4e;
|
||
|
|
ram.Mem[2] = 8'h2e;
|
||
|
|
// Preset memory
|
||
|
|
ram.Mem[55673] = 8'h76;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=0;
|
||
|
|
force dut.address_latch_.Q=16'h0000;
|
||
|
|
release dut.reg_control_.ctl_reg_sys_we;
|
||
|
|
release dut.reg_file_.reg_gp_we;
|
||
|
|
#2 // Execute: M1/T1 start
|
||
|
|
#1 release dut.address_latch_.Q;
|
||
|
|
#1
|
||
|
|
#36 // Wait for opcode end
|
||
|
|
force dut.reg_control_.ctl_reg_sys_we=0;
|
||
|
|
#2 pc=z.A;
|
||
|
|
#2
|
||
|
|
#1 force dut.reg_file_.reg_gp_we=0;
|
||
|
|
force dut.z80_top_ifc_n.fpga_reset=1;
|
||
|
|
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'hf7) $fdisplay(f,"* Reg af f=%h !=f7",dut.reg_file_.b2v_latch_af_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h7b) $fdisplay(f,"* Reg af a=%h !=7b",dut.reg_file_.b2v_latch_af_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h76) $fdisplay(f,"* Reg bc c=%h !=76",dut.reg_file_.b2v_latch_bc_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h66) $fdisplay(f,"* Reg bc b=%h !=66",dut.reg_file_.b2v_latch_bc_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h55) $fdisplay(f,"* Reg de e=%h !=55",dut.reg_file_.b2v_latch_de_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h8d) $fdisplay(f,"* Reg de d=%h !=8d",dut.reg_file_.b2v_latch_de_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'hf2) $fdisplay(f,"* Reg hl l=%h !=f2",dut.reg_file_.b2v_latch_hl_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hde) $fdisplay(f,"* Reg hl h=%h !=de",dut.reg_file_.b2v_latch_hl_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h4b) $fdisplay(f,"* Reg ix x=%h !=4b",dut.reg_file_.b2v_latch_ix_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'hd9) $fdisplay(f,"* Reg ix i=%h !=d9",dut.reg_file_.b2v_latch_ix_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'hfb) $fdisplay(f,"* Reg iy y=%h !=fb",dut.reg_file_.b2v_latch_iy_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h17) $fdisplay(f,"* Reg iy i=%h !=17",dut.reg_file_.b2v_latch_iy_hi.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
|
||
|
|
if (pc!==16'h0003) $fdisplay(f,"* PC=%h !=0003",pc);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
|
||
|
|
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
|
||
|
|
#1 // End opcode
|
||
|
|
|
||
|
|
`define TOTAL_CLKS 1588
|
||
|
|
$fdisplay(f,"=== Tests completed ===");
|