87 lines
2.7 KiB
Verilog
87 lines
2.7 KiB
Verilog
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// Copyright (C) 1991-2013 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// CREATED "Thu Nov 06 23:28:26 2014"
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module data_pins(
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bus_db_pin_oe,
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bus_db_pin_re,
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ctl_bus_db_we,
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clk,
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ctl_bus_db_oe,
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D,
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db
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);
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input wire bus_db_pin_oe;
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input wire bus_db_pin_re;
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input wire ctl_bus_db_we;
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input wire clk;
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input wire ctl_bus_db_oe;
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inout wire [7:0] D;
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inout wire [7:0] db;
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reg [7:0] dout;
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wire [7:0] SYNTHESIZED_WIRE_0;
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wire SYNTHESIZED_WIRE_1;
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wire SYNTHESIZED_WIRE_2;
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wire [7:0] SYNTHESIZED_WIRE_3;
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wire [7:0] SYNTHESIZED_WIRE_4;
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always@(posedge SYNTHESIZED_WIRE_1)
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begin
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if (SYNTHESIZED_WIRE_2)
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begin
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dout[7:0] <= SYNTHESIZED_WIRE_0[7:0];
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end
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end
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assign SYNTHESIZED_WIRE_4 = {ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we} & db;
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assign SYNTHESIZED_WIRE_3 = {bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re} & D;
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assign SYNTHESIZED_WIRE_0 = SYNTHESIZED_WIRE_3 | SYNTHESIZED_WIRE_4;
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assign SYNTHESIZED_WIRE_2 = ctl_bus_db_we | bus_db_pin_re;
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assign db[7] = ctl_bus_db_oe ? dout[7] : 1'bz;
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assign db[6] = ctl_bus_db_oe ? dout[6] : 1'bz;
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assign db[5] = ctl_bus_db_oe ? dout[5] : 1'bz;
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assign db[4] = ctl_bus_db_oe ? dout[4] : 1'bz;
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assign db[3] = ctl_bus_db_oe ? dout[3] : 1'bz;
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assign db[2] = ctl_bus_db_oe ? dout[2] : 1'bz;
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assign db[1] = ctl_bus_db_oe ? dout[1] : 1'bz;
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assign db[0] = ctl_bus_db_oe ? dout[0] : 1'bz;
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assign D[7] = bus_db_pin_oe ? dout[7] : 1'bz;
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assign D[6] = bus_db_pin_oe ? dout[6] : 1'bz;
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assign D[5] = bus_db_pin_oe ? dout[5] : 1'bz;
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assign D[4] = bus_db_pin_oe ? dout[4] : 1'bz;
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assign D[3] = bus_db_pin_oe ? dout[3] : 1'bz;
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assign D[2] = bus_db_pin_oe ? dout[2] : 1'bz;
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assign D[1] = bus_db_pin_oe ? dout[1] : 1'bz;
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assign D[0] = bus_db_pin_oe ? dout[0] : 1'bz;
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assign SYNTHESIZED_WIRE_1 = ~clk;
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endmodule
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