42 lines
1.5 KiB
Verilog
42 lines
1.5 KiB
Verilog
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//============================================================================
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// Bus switch in bus A-Z80 CPU
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//
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// Copyright 2014, 2016 Goran Devic
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//
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// This module provides control data bus switch signals. The sole purpose of
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// having these wires defined in this module is to get all control signals
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// (which are processed by genglobals.py) to appear in the list of global
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// control signals ("globals.vh") for consistency.
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//============================================================================
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module bus_switch
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(
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input wire ctl_sw_1u, // Control input for the SW1 upstream
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input wire ctl_sw_1d, // Control input for the SW1 downstream
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input wire ctl_sw_2u, // Control input for the SW2 upstream
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input wire ctl_sw_2d, // Control input for the SW2 downstream
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input wire ctl_sw_mask543_en, // Enables masking [5:3] on the data bus switch 1
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//--------------------------------------------------------------------
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output wire bus_sw_1u, // SW1 upstream
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output wire bus_sw_1d, // SW1 downstream
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output wire bus_sw_2u, // SW2 upstream
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output wire bus_sw_2d, // SW2 downstream
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output wire bus_sw_mask543_en // Affects SW1 downstream
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);
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assign bus_sw_1u = ctl_sw_1u;
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assign bus_sw_1d = ctl_sw_1d;
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assign bus_sw_2u = ctl_sw_2u;
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assign bus_sw_2d = ctl_sw_2d;
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assign bus_sw_mask543_en = ctl_sw_mask543_en;
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endmodule
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