101 lines
2.2 KiB
Verilog
101 lines
2.2 KiB
Verilog
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// Copyright (C) 1991-2013 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// CREATED "Mon Oct 13 12:17:04 2014"
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module alu_core(
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cy_in,
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S,
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V,
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R,
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op1,
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op2,
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cy_out,
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vf_out,
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result
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);
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input wire cy_in;
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input wire S;
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input wire V;
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input wire R;
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input wire [3:0] op1;
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input wire [3:0] op2;
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output wire cy_out;
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output wire vf_out;
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output wire [3:0] result;
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wire [3:0] result_ALTERA_SYNTHESIZED;
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wire SYNTHESIZED_WIRE_0;
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wire SYNTHESIZED_WIRE_1;
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wire SYNTHESIZED_WIRE_5;
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wire SYNTHESIZED_WIRE_3;
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assign cy_out = SYNTHESIZED_WIRE_3;
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alu_slice b2v_alu_slice_bit_0(
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.cy_in(cy_in),
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.op1(op1[0]),
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.op2(op2[0]),
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.S(S),
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.V(V),
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.R(R),
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.result(result_ALTERA_SYNTHESIZED[0]),
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.cy_out(SYNTHESIZED_WIRE_0));
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alu_slice b2v_alu_slice_bit_1(
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.cy_in(SYNTHESIZED_WIRE_0),
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.op1(op1[1]),
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.op2(op2[1]),
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.S(S),
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.V(V),
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.R(R),
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.result(result_ALTERA_SYNTHESIZED[1]),
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.cy_out(SYNTHESIZED_WIRE_1));
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alu_slice b2v_alu_slice_bit_2(
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.cy_in(SYNTHESIZED_WIRE_1),
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.op1(op1[2]),
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.op2(op2[2]),
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.S(S),
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.V(V),
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.R(R),
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.result(result_ALTERA_SYNTHESIZED[2]),
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.cy_out(SYNTHESIZED_WIRE_5));
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alu_slice b2v_alu_slice_bit_3(
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.cy_in(SYNTHESIZED_WIRE_5),
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.op1(op1[3]),
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.op2(op2[3]),
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.S(S),
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.V(V),
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.R(R),
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.result(result_ALTERA_SYNTHESIZED[3]),
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.cy_out(SYNTHESIZED_WIRE_3));
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assign vf_out = SYNTHESIZED_WIRE_3 ^ SYNTHESIZED_WIRE_5;
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assign result = result_ALTERA_SYNTHESIZED;
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endmodule
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