545 lines
20 KiB
Plaintext
545 lines
20 KiB
Plaintext
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Analysis & Synthesis report for spectrum
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Sat Apr 2 18:53:05 2022
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Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Analysis & Synthesis Summary
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3. Analysis & Synthesis Settings
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4. Parallel Compilation
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5. Analysis & Synthesis Messages
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6. Analysis & Synthesis Suppressed Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 1991-2013 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors. Please refer to the
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applicable agreement for further details.
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+---------------------------------------------------------------------------------+
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; Analysis & Synthesis Summary ;
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+------------------------------------+--------------------------------------------+
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; Analysis & Synthesis Status ; Failed - Sat Apr 2 18:53:05 2022 ;
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; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
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; Revision Name ; spectrum ;
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; Top-level Entity Name ; spectrum ;
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; Family ; Cyclone IV E ;
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; Total logic elements ; N/A until Partition Merge ;
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; Total combinational functions ; N/A until Partition Merge ;
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; Dedicated logic registers ; N/A until Partition Merge ;
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; Total registers ; N/A until Partition Merge ;
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; Total pins ; N/A until Partition Merge ;
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; Total virtual pins ; N/A until Partition Merge ;
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; Total memory bits ; N/A until Partition Merge ;
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; Embedded Multiplier 9-bit elements ; N/A until Partition Merge ;
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; Total PLLs ; N/A until Partition Merge ;
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+------------------------------------+--------------------------------------------+
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+--------------------------------------------------------------------------------+
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; Analysis & Synthesis Settings ;
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+--------------------------------------------------------------------------------+
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Option : Device
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Setting : EP4CE22F17C6
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Default Value :
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Option : Top-level entity name
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Setting : spectrum
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Default Value : spectrum
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Option : Family name
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Setting : Cyclone IV E
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Default Value : Cyclone IV GX
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Option : Use smart compilation
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Setting : Off
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Default Value : Off
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Option : Enable parallel Assembler and TimeQuest Timing Analyzer during compilation
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Setting : On
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Default Value : On
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Option : Enable compact report table
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Setting : Off
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Default Value : Off
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Option : Restructure Multiplexers
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Setting : Auto
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Default Value : Auto
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Option : Create Debugging Nodes for IP Cores
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Setting : Off
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Default Value : Off
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Option : Preserve fewer node names
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Setting : On
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Default Value : On
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Option : Disable OpenCore Plus hardware evaluation
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Setting : Off
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Default Value : Off
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Option : Verilog Version
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Setting : Verilog_2001
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Default Value : Verilog_2001
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Option : VHDL Version
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Setting : VHDL_1993
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Default Value : VHDL_1993
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Option : State Machine Processing
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Setting : Auto
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Default Value : Auto
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Option : Safe State Machine
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Setting : Off
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Default Value : Off
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Option : Extract Verilog State Machines
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Setting : On
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Default Value : On
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Option : Extract VHDL State Machines
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Setting : On
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Default Value : On
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Option : Ignore Verilog initial constructs
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Setting : Off
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Default Value : Off
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Option : Iteration limit for constant Verilog loops
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Setting : 5000
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Default Value : 5000
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Option : Iteration limit for non-constant Verilog loops
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Setting : 250
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Default Value : 250
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Option : Add Pass-Through Logic to Inferred RAMs
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Setting : On
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Default Value : On
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Option : Infer RAMs from Raw Logic
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Setting : On
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Default Value : On
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Option : Parallel Synthesis
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Setting : On
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Default Value : On
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Option : DSP Block Balancing
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Setting : Auto
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Default Value : Auto
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Option : NOT Gate Push-Back
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Setting : On
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Default Value : On
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Option : Power-Up Don't Care
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Setting : On
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Default Value : On
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Option : Remove Redundant Logic Cells
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Setting : Off
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Default Value : Off
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Option : Remove Duplicate Registers
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Setting : On
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Default Value : On
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Option : Ignore CARRY Buffers
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Setting : Off
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Default Value : Off
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Option : Ignore CASCADE Buffers
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Setting : Off
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Default Value : Off
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Option : Ignore GLOBAL Buffers
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Setting : Off
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Default Value : Off
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Option : Ignore ROW GLOBAL Buffers
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Setting : Off
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Default Value : Off
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Option : Ignore LCELL Buffers
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Setting : Off
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Default Value : Off
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Option : Ignore SOFT Buffers
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Setting : On
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Default Value : On
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Option : Limit AHDL Integers to 32 Bits
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Setting : Off
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Default Value : Off
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Option : Optimization Technique
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Setting : Balanced
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Default Value : Balanced
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Option : Carry Chain Length
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Setting : 70
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Default Value : 70
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Option : Auto Carry Chains
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Setting : On
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Default Value : On
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Option : Auto Open-Drain Pins
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Setting : On
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Default Value : On
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Option : Perform WYSIWYG Primitive Resynthesis
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Setting : Off
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Default Value : Off
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Option : Auto ROM Replacement
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Setting : On
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Default Value : On
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Option : Auto RAM Replacement
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Setting : On
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Default Value : On
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Option : Auto DSP Block Replacement
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Setting : On
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Default Value : On
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Option : Auto Shift Register Replacement
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Setting : Auto
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Default Value : Auto
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Option : Allow Shift Register Merging across Hierarchies
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Setting : Auto
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Default Value : Auto
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Option : Auto Clock Enable Replacement
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Setting : On
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Default Value : On
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Option : Strict RAM Replacement
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Setting : Off
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Default Value : Off
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Option : Allow Synchronous Control Signals
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Setting : On
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Default Value : On
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Option : Force Use of Synchronous Clear Signals
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Setting : Off
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Default Value : Off
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Option : Auto RAM Block Balancing
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Setting : On
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Default Value : On
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Option : Auto RAM to Logic Cell Conversion
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Setting : Off
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Default Value : Off
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Option : Auto Resource Sharing
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Setting : Off
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Default Value : Off
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Option : Allow Any RAM Size For Recognition
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Setting : Off
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Default Value : Off
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Option : Allow Any ROM Size For Recognition
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Setting : Off
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Default Value : Off
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Option : Allow Any Shift Register Size For Recognition
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Setting : Off
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Default Value : Off
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Option : Use LogicLock Constraints during Resource Balancing
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Setting : On
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Default Value : On
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Option : Ignore translate_off and synthesis_off directives
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Setting : Off
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Default Value : Off
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Option : Timing-Driven Synthesis
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Setting : On
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Default Value : On
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Option : Report Parameter Settings
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Setting : On
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Default Value : On
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Option : Report Source Assignments
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Setting : On
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Default Value : On
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Option : Report Connectivity Checks
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Setting : On
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Default Value : On
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Option : Ignore Maximum Fan-Out Assignments
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Setting : Off
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Default Value : Off
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Option : Synchronization Register Chain Length
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Setting : 2
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Default Value : 2
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Option : PowerPlay Power Optimization
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Setting : Normal compilation
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Default Value : Normal compilation
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Option : HDL message level
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Setting : Level2
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Default Value : Level2
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Option : Suppress Register Optimization Related Messages
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Setting : Off
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Default Value : Off
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Option : Number of Removed Registers Reported in Synthesis Report
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Setting : 5000
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Default Value : 5000
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Option : Number of Swept Nodes Reported in Synthesis Report
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Setting : 5000
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Default Value : 5000
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Option : Number of Inverted Registers Reported in Synthesis Report
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Setting : 100
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Default Value : 100
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Option : Clock MUX Protection
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Setting : On
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Default Value : On
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Option : Auto Gated Clock Conversion
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Setting : Off
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Default Value : Off
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Option : Block Design Naming
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Setting : Auto
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Default Value : Auto
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Option : SDC constraint protection
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Setting : Off
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Default Value : Off
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Option : Synthesis Effort
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Setting : Auto
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Default Value : Auto
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Option : Shift Register Replacement - Allow Asynchronous Clear Signal
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Setting : On
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Default Value : On
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Option : Pre-Mapping Resynthesis Optimization
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Setting : Off
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Default Value : Off
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Option : Analysis & Synthesis Message Level
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Setting : Medium
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Default Value : Medium
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Option : Disable Register Merging Across Hierarchies
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Setting : Auto
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Default Value : Auto
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Option : Resource Aware Inference For Block RAM
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Setting : On
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Default Value : On
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Option : Synthesis Seed
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Setting : 1
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Default Value : 1
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+--------------------------------------------------------------------------------+
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Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
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+-------------------------------------+
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; Parallel Compilation ;
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+----------------------------+--------+
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; Processors ; Number ;
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+----------------------------+--------+
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; Number detected on machine ; 12 ;
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; Maximum allowed ; 1 ;
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+----------------------------+--------+
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+-------------------------------+
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; Analysis & Synthesis Messages ;
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+-------------------------------+
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Info: *******************************************************************
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Info: Running Quartus II 32-bit Analysis & Synthesis
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Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
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||
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Info: Processing started: Sat Apr 2 18:53:04 2022
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Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum
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Warning (20028): Parallel compilation is not licensed and has been disabled
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Info (12021): Found 1 design units, including 1 entities, in source file spectrum.sv
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Info (12023): Found entity 1: spectrum
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Info (12021): Found 1 design units, including 1 entities, in source file rom0.v
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Info (12023): Found entity 1: rom0
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Info (12021): Found 1 design units, including 1 entities, in source file ram16.v
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Info (12023): Found entity 1: ram16
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Info (12021): Found 1 design units, including 1 entities, in source file ram32.v
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Info (12023): Found entity 1: ram32
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Info (12021): Found 1 design units, including 1 entities, in source file pll.v
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Info (12023): Found entity 1: pll
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Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu.v
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Info (12023): Found entity 1: alu
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Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_bit_select.v
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Info (12023): Found entity 1: alu_bit_select
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Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_control.v
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Info (12023): Found entity 1: alu_control
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Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_core.v
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Info (12023): Found entity 1: alu_core
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Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_flags.v
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Info (12023): Found entity 1: alu_flags
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Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2.v
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Info (12023): Found entity 1: alu_mux_2
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Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2z.v
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Info (12023): Found entity 1: alu_mux_2z
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Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_3z.v
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Info (12023): Found entity 1: alu_mux_3z
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Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_4.v
|
||
|
|
Info (12023): Found entity 1: alu_mux_4
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_8.v
|
||
|
|
Info (12023): Found entity 1: alu_mux_8
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_prep_daa.v
|
||
|
|
Info (12023): Found entity 1: alu_prep_daa
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_select.v
|
||
|
|
Info (12023): Found entity 1: alu_select
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_shifter_core.v
|
||
|
|
Info (12023): Found entity 1: alu_shifter_core
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_slice.v
|
||
|
|
Info (12023): Found entity 1: alu_slice
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/clk_delay.v
|
||
|
|
Info (12023): Found entity 1: clk_delay
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/decode_state.v
|
||
|
|
Info (12023): Found entity 1: decode_state
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/execute.v
|
||
|
|
Info (12023): Found entity 1: execute
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/interrupts.v
|
||
|
|
Info (12023): Found entity 1: interrupts
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/ir.v
|
||
|
|
Info (12023): Found entity 1: ir
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/memory_ifc.v
|
||
|
|
Info (12023): Found entity 1: memory_ifc
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/pin_control.v
|
||
|
|
Info (12023): Found entity 1: pin_control
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/pla_decode.v
|
||
|
|
Info (12023): Found entity 1: pla_decode
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/resets.v
|
||
|
|
Info (12023): Found entity 1: resets
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/sequencer.v
|
||
|
|
Info (12023): Found entity 1: sequencer
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/address_latch.v
|
||
|
|
Info (12023): Found entity 1: address_latch
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/address_mux.v
|
||
|
|
Info (12023): Found entity 1: address_mux
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/address_pins.v
|
||
|
|
Info (12023): Found entity 1: address_pins
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/bus_control.v
|
||
|
|
Info (12023): Found entity 1: bus_control
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/bus_switch.v
|
||
|
|
Info (12023): Found entity 1: bus_switch
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/control_pins_n.v
|
||
|
|
Info (12023): Found entity 1: control_pins_n
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/data_pins.v
|
||
|
|
Info (12023): Found entity 1: data_pins
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/data_switch.v
|
||
|
|
Info (12023): Found entity 1: data_switch
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/data_switch_mask.v
|
||
|
|
Info (12023): Found entity 1: data_switch_mask
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec.v
|
||
|
|
Info (12023): Found entity 1: inc_dec
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec_2bit.v
|
||
|
|
Info (12023): Found entity 1: inc_dec_2bit
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu/toplevel/z80_top_direct_n.v
|
||
|
|
Info (12023): Found entity 1: z80_top_direct_n
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu/registers/reg_control.v
|
||
|
|
Info (12023): Found entity 1: reg_control
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu/registers/reg_file.v
|
||
|
|
Info (12023): Found entity 1: reg_file
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu/registers/reg_latch.v
|
||
|
|
Info (12023): Found entity 1: reg_latch
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file ula/clocks.sv
|
||
|
|
Info (12023): Found entity 1: clocks
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file ula/zx_kbd.sv
|
||
|
|
Info (12023): Found entity 1: zx_keyboard
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file ula/video.sv
|
||
|
|
Info (12023): Found entity 1: video
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file ula/ula.sv
|
||
|
|
Info (12023): Found entity 1: ula
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file ula/ps2_kbd.sv
|
||
|
|
Info (12023): Found entity 1: ps2_keyboard
|
||
|
|
Info (12021): Found 2 design units, including 1 entities, in source file ula/i2c_loader.vhd
|
||
|
|
Info (12022): Found design unit 1: i2c_loader-i2c_loader_arch
|
||
|
|
Info (12023): Found entity 1: i2c_loader
|
||
|
|
Info (12021): Found 2 design units, including 1 entities, in source file ula/i2s_intf.vhd
|
||
|
|
Info (12022): Found design unit 1: i2s_intf-i2s_intf_arch
|
||
|
|
Info (12023): Found entity 1: i2s_intf
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file rom_scr.v
|
||
|
|
Info (12023): Found entity 1: rom_scr
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file pll_video.v
|
||
|
|
Info (12023): Found entity 1: pll_video
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file ram_video.v
|
||
|
|
Info (12023): Found entity 1: ram_video
|
||
|
|
Info (12021): Found 2 design units, including 1 entities, in source file sdram.vhdl
|
||
|
|
Info (12022): Found design unit 1: sdram_controller-rtl
|
||
|
|
Info (12023): Found entity 1: sdram_controller
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file sdram_clk_gen.v
|
||
|
|
Info (12023): Found entity 1: sdram_clk_gen
|
||
|
|
Warning (10335): Unrecognized synthesis attribute "IOB" at output_files/output_files/sdram.v(118)
|
||
|
|
Warning (10335): Unrecognized synthesis attribute "IOB" at output_files/output_files/sdram.v(120)
|
||
|
|
Warning (10335): Unrecognized synthesis attribute "IOB" at output_files/output_files/sdram.v(122)
|
||
|
|
Warning (10335): Unrecognized synthesis attribute "IOB" at output_files/output_files/sdram.v(124)
|
||
|
|
Warning (10335): Unrecognized synthesis attribute "IOB" at output_files/output_files/sdram.v(126)
|
||
|
|
Warning (10335): Unrecognized synthesis attribute "IOB" at output_files/output_files/sdram.v(128)
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file output_files/output_files/sdram.v
|
||
|
|
Info (12023): Found entity 1: sdram
|
||
|
|
Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(118)
|
||
|
|
Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(120)
|
||
|
|
Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(122)
|
||
|
|
Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(124)
|
||
|
|
Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(126)
|
||
|
|
Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(128)
|
||
|
|
Error (10228): Verilog HDL error at sdram.v(12): module "sdram" cannot be declared more than once File: /home/benny/work/fpga/spectrum/sdram.v Line: 12
|
||
|
|
Info (10499): HDL info at sdram.v(12): see declaration for object "sdram"
|
||
|
|
Info (12021): Found 0 design units, including 0 entities, in source file sdram.v
|
||
|
|
Info (144001): Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg
|
||
|
|
Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 1 error, 13 warnings
|
||
|
|
Error: Peak virtual memory: 397 megabytes
|
||
|
|
Error: Processing ended: Sat Apr 2 18:53:05 2022
|
||
|
|
Error: Elapsed time: 00:00:01
|
||
|
|
Error: Total CPU time (on all processors): 00:00:01
|
||
|
|
|
||
|
|
|
||
|
|
+------------------------------------------+
|
||
|
|
; Analysis & Synthesis Suppressed Messages ;
|
||
|
|
+------------------------------------------+
|
||
|
|
The suppressed messages can be found in /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg.
|
||
|
|
|
||
|
|
|