97 lines
4.0 KiB
Verilog
97 lines
4.0 KiB
Verilog
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//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=2 clk0_phase_shift="0" clk1_divide_by=1 clk1_duty_cycle=50 clk1_multiply_by=2 clk1_phase_shift="3000" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=sdram_clk_gen" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
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//VERSION_BEGIN 13.1 cbx_altclkbuf 2013:10:17:09:48:19:SJ cbx_altiobuf_bidir 2013:10:17:09:48:19:SJ cbx_altiobuf_in 2013:10:17:09:48:19:SJ cbx_altiobuf_out 2013:10:17:09:48:19:SJ cbx_altpll 2013:10:17:09:48:19:SJ cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_counter 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ cbx_stratixiii 2013:10:17:09:48:19:SJ cbx_stratixv 2013:10:17:09:48:19:SJ cbx_util_mgl 2013:10:17:09:48:19:SJ VERSION_END
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//CBXI_INSTANCE_NAME="spectrum_sdram_controller_sdram_sdram_clk_gen_sdram_clk_pll_altpll_altpll_component"
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// synthesis VERILOG_INPUT_VERSION VERILOG_2001
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// altera message_off 10463
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// Copyright (C) 1991-2013 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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//synthesis_resources = cycloneive_pll 1
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//synopsys translate_off
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`timescale 1 ps / 1 ps
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//synopsys translate_on
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module sdram_clk_gen_altpll
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(
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clk,
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inclk) /* synthesis synthesis_clearbox=1 */;
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output [4:0] clk;
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input [1:0] inclk;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri0 [1:0] inclk;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire [4:0] wire_pll1_clk;
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wire wire_pll1_fbout;
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cycloneive_pll pll1
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(
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.activeclock(),
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.clk(wire_pll1_clk),
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.clkbad(),
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.fbin(wire_pll1_fbout),
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.fbout(wire_pll1_fbout),
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.inclk(inclk),
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.locked(),
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.phasedone(),
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.scandataout(),
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.scandone(),
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.vcooverrange(),
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.vcounderrange()
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`ifndef FORMAL_VERIFICATION
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// synopsys translate_off
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`endif
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,
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.areset(1'b0),
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.clkswitch(1'b0),
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.configupdate(1'b0),
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.pfdena(1'b1),
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.phasecounterselect({3{1'b0}}),
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.phasestep(1'b0),
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.phaseupdown(1'b0),
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.scanclk(1'b0),
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.scanclkena(1'b1),
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.scandata(1'b0)
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`ifndef FORMAL_VERIFICATION
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// synopsys translate_on
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`endif
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);
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defparam
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pll1.bandwidth_type = "auto",
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pll1.clk0_divide_by = 1,
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pll1.clk0_duty_cycle = 50,
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pll1.clk0_multiply_by = 2,
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pll1.clk0_phase_shift = "0",
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pll1.clk1_divide_by = 1,
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pll1.clk1_duty_cycle = 50,
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pll1.clk1_multiply_by = 2,
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pll1.clk1_phase_shift = "3000",
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pll1.compensate_clock = "clk0",
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pll1.inclk0_input_frequency = 20000,
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pll1.operation_mode = "normal",
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pll1.pll_type = "auto",
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pll1.lpm_type = "cycloneive_pll";
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assign
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clk = {wire_pll1_clk[4:0]};
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endmodule //sdram_clk_gen_altpll
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//VALID FILE
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