68 lines
3.4 KiB
Plaintext
68 lines
3.4 KiB
Plaintext
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--lpm_mux CASCADE_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone IV E" IGNORE_CASCADE_BUFFERS="OFF" LPM_SIZE=2 LPM_WIDTH=15 LPM_WIDTHS=1 data result sel
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--VERSION_BEGIN 13.1 cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ VERSION_END
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-- Copyright (C) 1991-2013 Altera Corporation
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, Altera MegaCore Function License
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-- Agreement, or other applicable license agreement, including,
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-- without limitation, that your use is for the sole purpose of
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-- programming logic devices manufactured by Altera and sold by
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-- Altera or its authorized distributors. Please refer to the
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-- applicable agreement for further details.
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--synthesis_resources = lut 15
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SUBDESIGN mux_ssc
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(
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data[29..0] : input;
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result[14..0] : output;
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sel[0..0] : input;
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)
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VARIABLE
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result_node[14..0] : WIRE;
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sel_node[0..0] : WIRE;
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w_data102w[1..0] : WIRE;
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w_data114w[1..0] : WIRE;
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w_data126w[1..0] : WIRE;
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w_data138w[1..0] : WIRE;
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w_data150w[1..0] : WIRE;
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w_data162w[1..0] : WIRE;
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w_data174w[1..0] : WIRE;
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w_data18w[1..0] : WIRE;
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w_data30w[1..0] : WIRE;
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w_data42w[1..0] : WIRE;
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w_data4w[1..0] : WIRE;
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w_data54w[1..0] : WIRE;
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w_data66w[1..0] : WIRE;
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w_data78w[1..0] : WIRE;
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w_data90w[1..0] : WIRE;
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BEGIN
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result[] = result_node[];
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result_node[] = ( ((sel_node[] & w_data174w[1..1]) # ((! sel_node[]) & w_data174w[0..0])), ((sel_node[] & w_data162w[1..1]) # ((! sel_node[]) & w_data162w[0..0])), ((sel_node[] & w_data150w[1..1]) # ((! sel_node[]) & w_data150w[0..0])), ((sel_node[] & w_data138w[1..1]) # ((! sel_node[]) & w_data138w[0..0])), ((sel_node[] & w_data126w[1..1]) # ((! sel_node[]) & w_data126w[0..0])), ((sel_node[] & w_data114w[1..1]) # ((! sel_node[]) & w_data114w[0..0])), ((sel_node[] & w_data102w[1..1]) # ((! sel_node[]) & w_data102w[0..0])), ((sel_node[] & w_data90w[1..1]) # ((! sel_node[]) & w_data90w[0..0])), ((sel_node[] & w_data78w[1..1]) # ((! sel_node[]) & w_data78w[0..0])), ((sel_node[] & w_data66w[1..1]) # ((! sel_node[]) & w_data66w[0..0])), ((sel_node[] & w_data54w[1..1]) # ((! sel_node[]) & w_data54w[0..0])), ((sel_node[] & w_data42w[1..1]) # ((! sel_node[]) & w_data42w[0..0])), ((sel_node[] & w_data30w[1..1]) # ((! sel_node[]) & w_data30w[0..0])), ((sel_node[] & w_data18w[1..1]) # ((! sel_node[]) & w_data18w[0..0])), ((sel_node[] & w_data4w[1..1]) # ((! sel_node[]) & w_data4w[0..0])));
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sel_node[] = ( sel[0..0]);
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w_data102w[] = ( data[23..23], data[8..8]);
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w_data114w[] = ( data[24..24], data[9..9]);
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w_data126w[] = ( data[25..25], data[10..10]);
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w_data138w[] = ( data[26..26], data[11..11]);
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w_data150w[] = ( data[27..27], data[12..12]);
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w_data162w[] = ( data[28..28], data[13..13]);
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w_data174w[] = ( data[29..29], data[14..14]);
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w_data18w[] = ( data[16..16], data[1..1]);
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w_data30w[] = ( data[17..17], data[2..2]);
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w_data42w[] = ( data[18..18], data[3..3]);
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w_data4w[] = ( data[15..15], data[0..0]);
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w_data54w[] = ( data[19..19], data[4..4]);
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w_data66w[] = ( data[20..20], data[5..5]);
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w_data78w[] = ( data[21..21], data[6..6]);
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w_data90w[] = ( data[22..22], data[7..7]);
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END;
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--VALID FILE
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