86 lines
2.4 KiB
Verilog
86 lines
2.4 KiB
Verilog
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//============================================================================
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// Z80 Top level using the direct module declaration
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//============================================================================
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`timescale 1us/ 100 ns
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module z80_top_direct_n(
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output wire nM1,
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output wire nMREQ,
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output wire nIORQ,
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output wire nRD,
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output wire nWR,
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output wire nRFSH,
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output wire nHALT,
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output wire nBUSACK,
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input wire nWAIT,
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input wire nINT,
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input wire nNMI,
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input wire nRESET,
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input wire nBUSRQ,
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input wire CLK,
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output wire [15:0] A,
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inout wire [7:0] D
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);
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// Include core A-Z80 level connecting all internal modules
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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`include "core.vh"
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// Address, Data and Control bus drivers connecting to external pins
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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address_pins address_pins_(
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.clk (clk),
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.bus_ab_pin_we (bus_ab_pin_we),
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.pin_control_oe (pin_control_oe),
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.address (address),
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.abus (A)
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);
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data_pins data_pins_(
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.bus_db_pin_oe (bus_db_pin_oe),
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.bus_db_pin_re (bus_db_pin_re),
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.ctl_bus_db_we (ctl_bus_db_we),
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.ctl_bus_db_oe (ctl_bus_db_oe),
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.clk (clk),
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.db (db0),
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.D (D)
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);
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control_pins_n control_pins_(
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.busack (busack),
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.CPUCLK (CLK),
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.pin_control_oe(pin_control_oe),
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.in_halt (in_halt),
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.pin_nWAIT (nWAIT),
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.pin_nBUSRQ (nBUSRQ),
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.pin_nINT (nINT),
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.pin_nNMI (nNMI),
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.pin_nRESET (nRESET),
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.nM1_out (nM1_out),
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.nRFSH_out (nRFSH_out),
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.nRD_out (nRD_out),
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.nWR_out (nWR_out),
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.nIORQ_out (nIORQ_out),
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.nMREQ_out (nMREQ_out),
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.nmi (nmi),
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.busrq (busrq),
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.clk (clk),
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.intr (intr),
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.mwait (mwait),
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.reset_in (reset_in),
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.pin_nM1 (nM1),
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.pin_nMREQ (nMREQ),
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.pin_nIORQ (nIORQ),
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.pin_nRD (nRD),
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.pin_nWR (nWR),
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.pin_nRFSH (nRFSH),
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.pin_nHALT (nHALT),
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.pin_nBUSACK (nBUSACK)
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);
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endmodule
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