33 lines
848 B
Systemverilog
33 lines
848 B
Systemverilog
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//--------------------------------------------------------------
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// Interrupt test for simulation
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// This model injects an interrupt opcode on the bus
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//--------------------------------------------------------------
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module iorq (Data, M1, IORQ);
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// Set to 1 if you want debug printout on each IO access
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int debug = 0;
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inout [7:0] Data;
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input M1, IORQ;
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// Define the opcode to be sent through IORQ (FF=RST38, C7=RST0,...)
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// To test interrupts in mode 0, uncommend one of these lines (pushed opcode):
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//`define OPCODE 8'hFF
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//`define OPCODE 8'hC7
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// To test interrupts in mode 2, uncommend this line (this is a vector):
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`define OPCODE 8'h80
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// Return data on an IORQ condition
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assign Data = (!M1 && !IORQ) ? `OPCODE : {8{1'bz}};
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int fd;
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always @(!M1 && !IORQ) begin
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if (debug)
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$strobe("[IORQ] DB=%H", `OPCODE);
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end
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endmodule
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