64 lines
2.6 KiB
Python
64 lines
2.6 KiB
Python
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#!/usr/bin/env python3
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#
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# This script reads and parses selected Verilog and SystemVerilog modules
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# and generates a set of Verilog include files for the Z80 top-level block.
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#
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#-------------------------------------------------------------------------------
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# Copyright (C) 2014 Goran Devic
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of the GNU General Public License as published by the Free
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# Software Foundation; either version 2 of the License, or (at your option)
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# any later version.
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#
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# This program is distributed in the hope that it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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# more details.
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#-------------------------------------------------------------------------------
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import os
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with open('../top-level-files.txt') as f:
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files = f.read().splitlines()
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# Create a file that should be included in the top-level source
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with open('globals.vh', 'w') as file1:
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file1.write("// Automatically generated by genglobals.py\n")
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# Keep track of duplicated symbols across all files
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globals = []
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# Read and parse each file from the list of input files
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for infile in files:
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wires = []
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if not os.path.isfile('../' + infile):
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continue
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with open('../' + infile, "r") as f:
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for line in f:
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info = line.split()
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if len(info)>2:
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# There can be only one driver for each signal so we read only the outputs
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if info[0]=="output" and (info[1]=="wire" or info[1]=="reg" or info[1]=="logic"):
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# There are 2 cases: wires and buses
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if info[2].startswith('['):
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wires.append(info[2] + ' ' + info[3].strip(';,'))
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else:
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wires.append(info[2].strip(';,'))
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if len(wires)>0:
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with open('globals.vh', 'a') as file1:
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file1.write("\n// Module: " + infile + "\n")
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for wire in wires:
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# Everything in globals is a wire
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# (Can't use 'logic' since some buses are bidirectional)
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if wire in globals:
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file1.write("// wire " + wire + "; (previously defined)\n")
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else:
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file1.write("wire " + wire + ";\n")
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globals.append(wire)
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# Touch files that include 'globals.vh' to ensure it will recompile correctly
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os.utime("core.vh", None)
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os.utime("z80_top_direct_n.v", None)
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os.utime("z80_top_ifc_n.sv", None)
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