70 lines
2.3 KiB
Verilog
70 lines
2.3 KiB
Verilog
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// Copyright (C) 1991-2013 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// CREATED "Sun Nov 16 16:56:05 2014"
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module address_pins(
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clk,
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bus_ab_pin_we,
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pin_control_oe,
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address,
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abus
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);
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input wire clk;
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input wire bus_ab_pin_we;
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input wire pin_control_oe;
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input wire [15:0] address;
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output wire [15:0] abus;
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wire SYNTHESIZED_WIRE_0;
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reg [15:0] DFFE_apin_latch;
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always@(posedge SYNTHESIZED_WIRE_0)
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begin
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if (bus_ab_pin_we)
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begin
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DFFE_apin_latch[15:0] <= address[15:0];
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end
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end
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assign abus[15] = pin_control_oe ? DFFE_apin_latch[15] : 1'bz;
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assign abus[14] = pin_control_oe ? DFFE_apin_latch[14] : 1'bz;
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assign abus[13] = pin_control_oe ? DFFE_apin_latch[13] : 1'bz;
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assign abus[12] = pin_control_oe ? DFFE_apin_latch[12] : 1'bz;
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assign abus[11] = pin_control_oe ? DFFE_apin_latch[11] : 1'bz;
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assign abus[10] = pin_control_oe ? DFFE_apin_latch[10] : 1'bz;
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assign abus[9] = pin_control_oe ? DFFE_apin_latch[9] : 1'bz;
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assign abus[8] = pin_control_oe ? DFFE_apin_latch[8] : 1'bz;
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assign abus[7] = pin_control_oe ? DFFE_apin_latch[7] : 1'bz;
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assign abus[6] = pin_control_oe ? DFFE_apin_latch[6] : 1'bz;
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assign abus[5] = pin_control_oe ? DFFE_apin_latch[5] : 1'bz;
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assign abus[4] = pin_control_oe ? DFFE_apin_latch[4] : 1'bz;
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assign abus[3] = pin_control_oe ? DFFE_apin_latch[3] : 1'bz;
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assign abus[2] = pin_control_oe ? DFFE_apin_latch[2] : 1'bz;
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assign abus[1] = pin_control_oe ? DFFE_apin_latch[1] : 1'bz;
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assign abus[0] = pin_control_oe ? DFFE_apin_latch[0] : 1'bz;
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assign SYNTHESIZED_WIRE_0 = ~clk;
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endmodule
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