359 lines
8.0 KiB
Verilog
359 lines
8.0 KiB
Verilog
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// Copyright (C) 1991-2013 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// CREATED "Sat Dec 10 09:01:30 2016"
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module alu_flags(
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ctl_flags_oe,
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ctl_flags_bus,
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ctl_flags_alu,
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alu_sf_out,
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alu_yf_out,
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alu_xf_out,
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ctl_flags_nf_set,
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alu_zero,
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shift_cf_out,
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alu_core_cf_out,
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daa_cf_out,
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ctl_flags_cf_set,
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ctl_flags_cf_cpl,
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pf_sel,
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ctl_flags_cf_we,
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ctl_flags_sz_we,
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ctl_flags_xy_we,
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ctl_flags_hf_we,
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ctl_flags_pf_we,
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ctl_flags_nf_we,
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ctl_flags_cf2_we,
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ctl_flags_hf_cpl,
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ctl_flags_use_cf2,
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ctl_flags_hf2_we,
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ctl_flags_nf_clr,
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ctl_alu_zero_16bit,
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clk,
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ctl_flags_cf2_sel_shift,
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ctl_flags_cf2_sel_daa,
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nhold_clk_wait,
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flags_sf,
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flags_zf,
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flags_hf,
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flags_pf,
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flags_cf,
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flags_nf,
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flags_cf_latch,
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flags_hf2,
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db
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);
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input wire ctl_flags_oe;
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input wire ctl_flags_bus;
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input wire ctl_flags_alu;
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input wire alu_sf_out;
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input wire alu_yf_out;
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input wire alu_xf_out;
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input wire ctl_flags_nf_set;
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input wire alu_zero;
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input wire shift_cf_out;
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input wire alu_core_cf_out;
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input wire daa_cf_out;
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input wire ctl_flags_cf_set;
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input wire ctl_flags_cf_cpl;
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input wire pf_sel;
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input wire ctl_flags_cf_we;
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input wire ctl_flags_sz_we;
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input wire ctl_flags_xy_we;
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input wire ctl_flags_hf_we;
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input wire ctl_flags_pf_we;
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input wire ctl_flags_nf_we;
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input wire ctl_flags_cf2_we;
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input wire ctl_flags_hf_cpl;
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input wire ctl_flags_use_cf2;
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input wire ctl_flags_hf2_we;
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input wire ctl_flags_nf_clr;
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input wire ctl_alu_zero_16bit;
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input wire clk;
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input wire ctl_flags_cf2_sel_shift;
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input wire ctl_flags_cf2_sel_daa;
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input wire nhold_clk_wait;
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output wire flags_sf;
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output wire flags_zf;
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output wire flags_hf;
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output wire flags_pf;
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output wire flags_cf;
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output wire flags_nf;
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output wire flags_cf_latch;
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output reg flags_hf2;
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inout wire [7:0] db;
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reg flags_xf;
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reg flags_yf;
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wire [1:0] sel;
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reg DFFE_inst_latch_hf;
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wire SYNTHESIZED_WIRE_0;
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wire SYNTHESIZED_WIRE_1;
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wire SYNTHESIZED_WIRE_2;
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wire SYNTHESIZED_WIRE_3;
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wire SYNTHESIZED_WIRE_4;
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wire SYNTHESIZED_WIRE_5;
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wire SYNTHESIZED_WIRE_6;
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wire SYNTHESIZED_WIRE_7;
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reg SYNTHESIZED_WIRE_39;
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wire SYNTHESIZED_WIRE_8;
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wire SYNTHESIZED_WIRE_9;
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wire SYNTHESIZED_WIRE_10;
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wire SYNTHESIZED_WIRE_11;
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wire SYNTHESIZED_WIRE_12;
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wire SYNTHESIZED_WIRE_13;
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wire SYNTHESIZED_WIRE_14;
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wire SYNTHESIZED_WIRE_15;
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wire SYNTHESIZED_WIRE_16;
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wire SYNTHESIZED_WIRE_17;
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wire SYNTHESIZED_WIRE_18;
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wire SYNTHESIZED_WIRE_19;
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wire SYNTHESIZED_WIRE_20;
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wire SYNTHESIZED_WIRE_21;
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wire SYNTHESIZED_WIRE_22;
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reg DFFE_inst_latch_sf;
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wire SYNTHESIZED_WIRE_23;
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reg DFFE_inst_latch_pf;
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reg DFFE_inst_latch_nf;
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wire SYNTHESIZED_WIRE_24;
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wire SYNTHESIZED_WIRE_25;
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wire SYNTHESIZED_WIRE_26;
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wire SYNTHESIZED_WIRE_27;
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wire SYNTHESIZED_WIRE_28;
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wire SYNTHESIZED_WIRE_29;
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wire SYNTHESIZED_WIRE_40;
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wire SYNTHESIZED_WIRE_32;
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wire SYNTHESIZED_WIRE_33;
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wire SYNTHESIZED_WIRE_34;
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wire SYNTHESIZED_WIRE_35;
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wire SYNTHESIZED_WIRE_36;
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wire SYNTHESIZED_WIRE_37;
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reg DFFE_inst_latch_cf;
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reg DFFE_inst_latch_cf2;
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wire SYNTHESIZED_WIRE_38;
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assign flags_sf = DFFE_inst_latch_sf;
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assign flags_zf = SYNTHESIZED_WIRE_39;
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assign flags_hf = SYNTHESIZED_WIRE_23;
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assign flags_pf = DFFE_inst_latch_pf;
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assign flags_cf = SYNTHESIZED_WIRE_24;
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assign flags_nf = DFFE_inst_latch_nf;
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assign flags_cf_latch = DFFE_inst_latch_cf;
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assign SYNTHESIZED_WIRE_38 = 0;
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assign SYNTHESIZED_WIRE_10 = db[7] & ctl_flags_bus;
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assign SYNTHESIZED_WIRE_17 = alu_xf_out & ctl_flags_alu;
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assign SYNTHESIZED_WIRE_20 = db[2] & ctl_flags_bus;
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assign SYNTHESIZED_WIRE_19 = pf_sel & ctl_flags_alu;
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assign SYNTHESIZED_WIRE_2 = db[1] & ctl_flags_bus;
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assign SYNTHESIZED_WIRE_23 = DFFE_inst_latch_hf ^ ctl_flags_hf_cpl;
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assign SYNTHESIZED_WIRE_22 = db[0] & ctl_flags_bus;
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assign SYNTHESIZED_WIRE_21 = ctl_flags_alu & alu_core_cf_out;
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assign SYNTHESIZED_WIRE_8 = ~ctl_flags_cf2_we;
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assign SYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_0 ^ ctl_flags_cf_cpl;
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assign SYNTHESIZED_WIRE_1 = alu_sf_out & ctl_flags_alu;
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assign SYNTHESIZED_WIRE_9 = alu_sf_out & ctl_flags_alu;
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assign SYNTHESIZED_WIRE_5 = ctl_flags_nf_set | SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;
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assign SYNTHESIZED_WIRE_37 = SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_4;
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assign SYNTHESIZED_WIRE_32 = SYNTHESIZED_WIRE_5 & SYNTHESIZED_WIRE_6;
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assign SYNTHESIZED_WIRE_6 = ~ctl_flags_nf_clr;
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assign SYNTHESIZED_WIRE_7 = ~ctl_alu_zero_16bit;
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assign SYNTHESIZED_WIRE_4 = SYNTHESIZED_WIRE_7 | SYNTHESIZED_WIRE_39;
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assign SYNTHESIZED_WIRE_27 = ctl_flags_cf_we & nhold_clk_wait & SYNTHESIZED_WIRE_8;
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assign SYNTHESIZED_WIRE_29 = ctl_flags_cf2_we & nhold_clk_wait;
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assign SYNTHESIZED_WIRE_12 = db[6] & ctl_flags_bus;
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assign SYNTHESIZED_WIRE_34 = SYNTHESIZED_WIRE_9 | SYNTHESIZED_WIRE_10;
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assign SYNTHESIZED_WIRE_3 = SYNTHESIZED_WIRE_11 | SYNTHESIZED_WIRE_12;
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assign SYNTHESIZED_WIRE_36 = SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14;
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assign SYNTHESIZED_WIRE_40 = SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16;
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assign SYNTHESIZED_WIRE_35 = SYNTHESIZED_WIRE_17 | SYNTHESIZED_WIRE_18;
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assign SYNTHESIZED_WIRE_33 = SYNTHESIZED_WIRE_19 | SYNTHESIZED_WIRE_20;
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assign SYNTHESIZED_WIRE_11 = alu_zero & ctl_flags_alu;
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assign SYNTHESIZED_WIRE_26 = SYNTHESIZED_WIRE_21 | SYNTHESIZED_WIRE_22;
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assign db[7] = ctl_flags_oe ? DFFE_inst_latch_sf : 1'bz;
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assign SYNTHESIZED_WIRE_14 = db[5] & ctl_flags_bus;
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assign db[6] = ctl_flags_oe ? SYNTHESIZED_WIRE_39 : 1'bz;
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assign db[5] = ctl_flags_oe ? flags_yf : 1'bz;
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assign db[4] = ctl_flags_oe ? SYNTHESIZED_WIRE_23 : 1'bz;
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assign db[3] = ctl_flags_oe ? flags_xf : 1'bz;
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assign db[2] = ctl_flags_oe ? DFFE_inst_latch_pf : 1'bz;
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assign db[1] = ctl_flags_oe ? DFFE_inst_latch_nf : 1'bz;
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assign db[0] = ctl_flags_oe ? SYNTHESIZED_WIRE_24 : 1'bz;
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assign SYNTHESIZED_WIRE_13 = alu_yf_out & ctl_flags_alu;
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assign SYNTHESIZED_WIRE_0 = ctl_flags_cf_set | SYNTHESIZED_WIRE_25;
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assign SYNTHESIZED_WIRE_16 = db[4] & ctl_flags_bus;
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assign SYNTHESIZED_WIRE_15 = alu_core_cf_out & ctl_flags_alu;
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assign SYNTHESIZED_WIRE_18 = db[3] & ctl_flags_bus;
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always@(posedge clk)
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begin
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if (SYNTHESIZED_WIRE_27)
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begin
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DFFE_inst_latch_cf <= SYNTHESIZED_WIRE_26;
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end
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end
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always@(posedge clk)
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begin
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if (SYNTHESIZED_WIRE_29)
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begin
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DFFE_inst_latch_cf2 <= SYNTHESIZED_WIRE_28;
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end
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end
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always@(posedge clk)
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begin
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if (ctl_flags_hf_we)
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begin
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DFFE_inst_latch_hf <= SYNTHESIZED_WIRE_40;
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end
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end
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always@(posedge clk)
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begin
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if (ctl_flags_hf2_we)
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begin
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flags_hf2 <= SYNTHESIZED_WIRE_40;
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end
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end
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always@(posedge clk)
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begin
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if (ctl_flags_nf_we)
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begin
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DFFE_inst_latch_nf <= SYNTHESIZED_WIRE_32;
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end
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end
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always@(posedge clk)
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begin
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if (ctl_flags_pf_we)
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begin
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DFFE_inst_latch_pf <= SYNTHESIZED_WIRE_33;
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end
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end
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always@(posedge clk)
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begin
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if (ctl_flags_sz_we)
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begin
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DFFE_inst_latch_sf <= SYNTHESIZED_WIRE_34;
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end
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end
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always@(posedge clk)
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begin
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if (ctl_flags_xy_we)
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begin
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flags_xf <= SYNTHESIZED_WIRE_35;
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end
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end
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always@(posedge clk)
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begin
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if (ctl_flags_xy_we)
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begin
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flags_yf <= SYNTHESIZED_WIRE_36;
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end
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end
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always@(posedge clk)
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begin
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if (ctl_flags_sz_we)
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begin
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SYNTHESIZED_WIRE_39 <= SYNTHESIZED_WIRE_37;
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end
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end
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alu_mux_2 b2v_inst_mux_cf(
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.in0(DFFE_inst_latch_cf),
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.in1(DFFE_inst_latch_cf2),
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.sel1(ctl_flags_use_cf2),
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.out(SYNTHESIZED_WIRE_25));
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alu_mux_4 b2v_inst_mux_cf2(
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.in0(alu_core_cf_out),
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.in1(shift_cf_out),
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||
|
|
.in2(daa_cf_out),
|
||
|
|
.in3(SYNTHESIZED_WIRE_38),
|
||
|
|
.sel(sel),
|
||
|
|
.out(SYNTHESIZED_WIRE_28));
|
||
|
|
|
||
|
|
assign sel[0] = ctl_flags_cf2_sel_shift;
|
||
|
|
assign sel[1] = ctl_flags_cf2_sel_daa;
|
||
|
|
|
||
|
|
endmodule
|