2022-04-02 14:56:02 +03:00
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648899774991 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648899774992 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 14:42:54 2022 " "Processing started: Sat Apr 2 14:42:54 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648899774992 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648899774992 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648899774992 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648899775174 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.sv 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.sv" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775242 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775242 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775243 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775243 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram16.v 1 1 " "Found 1 design units, including 1 entities, in source file ram16.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram16 " "Found entity 1: ram16" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775244 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775244 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram32.v 1 1 " "Found 1 design units, including 1 entities, in source file ram32.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram32 " "Found entity 1: ram32" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775245 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775245 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll.v 1 1 " "Found 1 design units, including 1 entities, in source file pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll " "Found entity 1: pll" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775246 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775246 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu " "Found entity 1: alu" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775248 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775248 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_bit_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_bit_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_bit_select " "Found entity 1: alu_bit_select" { } { { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775249 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775249 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_control " "Found entity 1: alu_control" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775250 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775250 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_core " "Found entity 1: alu_core" { } { { "cpu/alu/alu_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775250 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775250 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_flags.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_flags.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_flags " "Found entity 1: alu_flags" { } { { "cpu/alu/alu_flags.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775252 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775252 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2 " "Found entity 1: alu_mux_2" { } { { "cpu/alu/alu_mux_2.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775252 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775252 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2z " "Found entity 1: alu_mux_2z" { } { { "cpu/alu/alu_mux_2z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775253 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775253 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_3z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_3z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_3z " "Found entity 1: alu_mux_3z" { } { { "cpu/alu/alu_mux_3z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_3z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775254 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775254 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_4.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_4.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_4 " "Found entity 1: alu_mux_4" { } { { "cpu/alu/alu_mux_4.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_4.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775254 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775254 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_8.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_8 " "Found entity 1: alu_mux_8" { } { { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775255 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775255 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_prep_daa.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_prep_daa.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_prep_daa " "Found entity 1: alu_prep_daa" { } { { "cpu/alu/alu_prep_daa.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_prep_daa.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775256 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775256 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_select " "Found entity 1: alu_select" { } { { "cpu/alu/alu_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775257 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775257 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_shifter_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_shifter_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_shifter_core " "Found entity 1: alu_shifter_core" { } { { "cpu/alu/alu_shifter_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_shifter_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775258 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775258 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_slice.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_slice.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_slice " "Found entity 1: alu_slice" { } { { "cpu/alu/alu_slice.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_slice.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775258 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775258 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/clk_delay.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/clk_delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_delay " "Found entity 1: clk_delay" { } { { "cpu/control/clk_delay.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/clk_delay.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775259 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775259 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/decode_state.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/decode_state.v" { { "Info" "ISGN_ENTITY_NAME" "1 decode_state " "Found entity 1: decode_state" { } { { "cpu/control/decode_state.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/decode_state.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775260 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775260 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/execute.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/execute.v" { { "Info" "ISGN_ENTITY_NAME" "1 execute " "Found entity 1: execute" { } { { "cpu/control/execute.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/execute.v" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775286 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775286 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/interrupts.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/interrupts.v" { { "Info" "ISGN_ENTITY_NAME" "1 interrupts " "Found entity 1: interrupts" { } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775287 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775287 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/ir.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/ir.v" { { "Info" "ISGN_ENTITY_NAME" "1 ir " "Found entity 1: ir" { } { { "cpu/control/ir.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/ir.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775288 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775288 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/memory_ifc.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/memory_ifc.v" { { "Info" "ISGN_ENTITY_NAME" "1 memory_ifc " "Found entity 1: memory_ifc" { } { { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775289 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775289 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pin_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pin_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 pin_control " "Found entity 1: pin_control" { } { { "cpu/control/pin_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pin_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775290 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775290 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pla_decode.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pla_decode.v" { { "Info" "ISGN_ENTITY_NAME" "1 pla_decode " "Found entity 1: pla_decode" { } { { "cpu/control/pla_decode.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pla_decode.v" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775291 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775291 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/resets.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/resets.v" { { "Info" "ISGN_ENTITY_NAME" "1 resets " "Found entity 1: resets" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775292 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775292 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/sequencer.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/sequencer.v" { { "Info" "ISGN_ENTITY_NAME" "1 sequencer " "Found entity 1: sequencer" { } { { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775293 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775293 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_latch " "Found entity 1: address_latch" { } { { "cpu/bus/address_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775294 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775294 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_mux.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_mux " "Found entity 1: address_mux" { } { { "cpu/bus/address_mux.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_mux.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775295 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775295 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_pins " "Found entity 1: address_pins" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775296 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775296 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_control " "Found entity 1: bus_control" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775296 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775296 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_switch " "Found entity 1: bus_switch" { } { { "cpu/bus/bus_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_switch.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775297 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775297 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/control_pins_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/control_pins_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_pins_n " "Found entity 1: control_pins_n" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775298 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775298 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_pins " "Found entity 1: data_pins" { } { { "cpu/bus/data_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775299 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775299 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch " "Found entity 1: data_switch" { } { { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775300 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775300 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch_mask.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch_mask.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch_mask " "Found entity 1: data_switch_mask" { } { { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775301 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775301 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec " "Found entity 1: inc_dec" { } { { "cpu/bus/inc_dec.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775302 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775302 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec_2bit.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec_2bit.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec_2bit " "Found entity 1: inc_dec_2bit" { } { { "cpu/bus/inc_dec_2bit.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec_2bit.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775302 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775302 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "nRESET nreset z80_top_direct_n.v(19) " "Verilog HDL Declaration information at z80_top_direct_n.v(19): object \"nRESET\" differs only in case from object \"nreset\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 19 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648899775305 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CLK clk z80_top_direct_n.v(22) " "Verilog HDL Declaration information at z80_top_direct_n.v(22): object \"CLK\" differs only in case from object \"clk\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648899775305 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/toplevel/z80_top_direct_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/toplevel/z80_top_direct_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 z80_top_direct_n " "Found entity 1: z80_top_direct_n" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775305 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775305 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_control " "Found entity 1: reg_control" { } { { "cpu/registers/reg_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775306 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775306 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_file.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_file.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_file " "Found entity 1: reg_file" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775308 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775308 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_latch " "Found entity 1: reg_latch" { } { { "cpu/registers/reg_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775308 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775308 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/clocks.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/clocks.sv" { { "Info" "ISGN_ENTITY_NAME" "1 clocks " "Found entity 1: clocks" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775309 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775309 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/zx_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/zx_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 zx_keyboard " "Found entity 1: zx_keyboard" { } { { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775310 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775310 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/video.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/video.sv" { { "Info" "ISGN_ENTITY_NAME" "1 video " "Found entity 1: video" { } { { "ula/video.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/video.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775311 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775311 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ula.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ula.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ula " "Found entity 1: ula" { } { { "ula/ula.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775312 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775312 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ps2_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ps2_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ps2_keyboard " "Found entity 1: ps2_keyboard" { } { { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775313 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775313 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2c_loader.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2c_loader.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2c_loader-i2c_loader_arch " "Found design unit 1: i2c_loader-i2c_loader_arch" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 64 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775612 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2c_loader " "Found entity 1: i2c_loader" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775612 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775612 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2s_intf.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2s_intf.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2s_intf-i2s_intf_arch " "Found design unit 1: i2s_intf-i2s_intf_arch" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 82 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775613 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2s_intf " "Found entity 1: i2s_intf" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775613 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775613 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom_scr.v 1 1 " "Found 1 design units, including 1 entities, in source file rom_scr.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom_scr " "Found entity 1: rom_scr" { } { { "rom_scr.v" "" { Text "/home/benny/work/fpga/spectrum/rom_scr.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775616 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775616 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_video.v 1 1 " "Found 1 design units, including 1 entities, in source file pll_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_video " "Found entity 1: pll_video" { } { { "pll_video.v" "" { Text "/home/benny/work/fpga/spectrum/pll_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775617 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775617 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram_video.v 1 1 " "Found 1 design units, including 1 entities, in source file ram_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram_video " "Found entity 1: ram_video" { } { { "ram_video.v" "" { Text "/home/benny/work/fpga/spectrum/ram_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775618 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775618 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram.vhdl 2 1 " "Found 2 design units, including 1 entities, in source file sdram.vhdl" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sdram_controller-rtl " "Found design unit 1: sdram_controller-rtl" { } { { "sdram.vhdl" "" { Text "/home/benny/work/fpga/spectrum/sdram.vhdl" 42 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775620 ""} { "Info" "ISGN_ENTITY_NAME" "1 sdram_controller " "Found entity 1: sdram_controller" { } { { "sdram.vhdl" "" { Text "/home/benny/work/fpga/spectrum/sdram.vhdl" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775620 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775620 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_clk_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_clk_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdram_clk_gen " "Found entity 1: sdram_clk_gen" { } { { "sdram_clk_gen.v" "" { Text "/home/benny/work/fpga/spectrum/sdram_clk_gen.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775621 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775621 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648899775785 ""}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED\[7..4\] spectrum.sv(1) " "Output port \"LED\[7..4\]\" at spectrum.sv(1) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648899775790 "|spectrum"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED\[1\] spectrum.sv(1) " "Output port \"LED\[1\]\" at spectrum.sv(1) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648899775790 "|spectrum"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "GPIO_1\[33..32\] spectrum.sv(20) " "Output port \"GPIO_1\[33..32\]\" at spectrum.sv(20) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648899775790 "|spectrum"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom0 rom0:rom " "Elaborating entity \"rom0\" for hierarchy \"rom0:rom\"" { } { { "spectrum.sv" "rom" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 147 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775804 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom0:rom\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775853 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "rom0:rom\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rom0:rom\|altsyncram:altsyncram_component " "Instantiated megafunction \"rom0:rom\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ./rom/gw03.hex " "Parameter \"init_file\" = \"./rom/gw03.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775854 ""} } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648899775854 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qh91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_qh91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qh91 " "Found entity 1: altsyncram_qh91" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 31 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775905 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775905 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qh91 rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated " "Elaborating entity \"altsyncram_qh91\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775906 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_c8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_c8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_c8a " "Found entity 1: decode_c8a" { } { { "db/decode_c8a.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_c8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775949 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775949 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_c8a rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode " "Elaborating entity \"decode_c8a\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode\"" { } { { "db/altsyncram_qh91.tdf" "rden_decode" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 40 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775949 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_3nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_3nb " "Found entity 1: mux_3nb" { } { { "db/mux_3nb.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/mux_3nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899775993 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899775993 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_3nb rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2 " "Elaborating entity \"mux_3nb\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2\"" { } { { "db/altsyncram_qh91.tdf" "mux2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 41 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775993 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram16 ram16:ram0 " "Elaborating entity \"ram16\" for hierarchy \"ram16:ram0\"" { } { { "spectrum.sv" "ram0" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899775997 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram16:ram0\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776001 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "ram16:ram0\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram16:ram0\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram16:ram0\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_b BYPASS " "Parameter \"clock_enable_input_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_b BYPASS " "Parameter \"clock_enable_output_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_reg_b CLOCK0 " "Parameter \"indata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ula/test_scr.hex " "Parameter \"init_file\" = \"ula/test_scr.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 16384 " "Parameter \"numwords_b\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Parameter \"outdata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rea
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_7ti2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_7ti2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_7ti2 " "Found entity 1: altsyncram_7ti2" { } { { "db/altsyncram_7ti2.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_7ti2.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899776052 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899776052 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_7ti2 ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated " "Elaborating entity \"altsyncram_7ti2\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776052 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_jsa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_jsa " "Found entity 1: decode_jsa" { } { { "db/decode_jsa.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_jsa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899776096 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899776096 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_jsa ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|decode_jsa:decode2 " "Elaborating entity \"decode_jsa\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|decode_jsa:decode2\"" { } { { "db/altsyncram_7ti2.tdf" "decode2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_7ti2.tdf" 50 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776096 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram32 ram32:ram1 " "Elaborating entity \"ram32\" for hierarchy \"ram32:ram1\"" { } { { "spectrum.sv" "ram1" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776102 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram32:ram1\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\"" { } { { "ram32.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776106 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "ram32:ram1\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram32:ram1\|altsyncram:altsyncram_component\"" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram32:ram1\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram32:ram1\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file led_patterns.mif " "Parameter \"init_file\" = \"led_patterns.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32768 " "Parameter \"numwords_a\" = \"32768\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode SINGLE_PORT " "Parameter \"operation_mode\" = \"SINGLE_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 15 " "Parameter \"widthad_a\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776107 ""} } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648899776107 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_g9i1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_g9i1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_g9i1 " "Found entity 1: altsyncram_g9i1" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899776158 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899776158 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_g9i1 ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated " "Elaborating entity \"altsyncram_g9i1\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776158 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_msa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_msa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_msa " "Found entity 1: decode_msa" { } { { "db/decode_msa.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_msa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899776202 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899776202 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_msa ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_msa:decode3 " "Elaborating entity \"decode_msa\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_msa:decode3\"" { } { { "db/altsyncram_g9i1.tdf" "decode3" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776203 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_f8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_f8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_f8a " "Found entity 1: decode_f8a" { } { { "db/decode_f8a.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_f8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899776246 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899776246 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_f8a ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_f8a:rden_decode " "Elaborating entity \"decode_f8a\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_f8a:rden_decode\"" { } { { "db/altsyncram_g9i1.tdf" "rden_decode" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 45 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776247 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_6nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_6nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_6nb " "Found entity 1: mux_6nb" { } { { "db/mux_6nb.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/mux_6nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899776291 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899776291 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_6nb ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|mux_6nb:mux2 " "Elaborating entity \"mux_6nb\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|mux_6nb:mux2\"" { } { { "db/altsyncram_g9i1.tdf" "mux2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 46 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776291 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_controller sdram_controller:sdram_ " "Elaborating entity \"sdram_controller\" for hierarchy \"sdram_controller:sdram_\"" { } { { "spectrum.sv" "sdram_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776293 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_clk_gen sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll " "Elaborating entity \"sdram_clk_gen\" for hierarchy \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\"" { } { { "sdram.vhdl" "sdram_clk_pll" { Text "/home/benny/work/fpga/spectrum/sdram.vhdl" 145 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776297 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\"" { } { { "sdram_clk_gen.v" "altpll_component" { Text "/home/benny/work/fpga/spectrum/sdram_clk_gen.v" 94 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776326 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component " "Elaborated megafunction instantiation \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\"" { } { { "sdram_clk_gen.v" "" { Text "/home/benny/work/fpga/spectrum/sdram_clk_gen.v" 94 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component " "Instantiated megafunction \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 1 " "Parameter \"clk0_divide_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 2 " "Parameter \"clk0_multiply_by\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 1 " "Parameter \"clk1_divide_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 2 " "Parameter \"clk1_multiply_by\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 3000 " "Parameter \"clk1_phase_shift\" = \"3000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=sdram_clk_gen " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=sdram_clk_gen\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Para
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sdram_clk_gen_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/sdram_clk_gen_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdram_clk_gen_altpll " "Found entity 1: sdram_clk_gen_altpll" { } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899776381 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899776381 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_clk_gen_altpll sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated " "Elaborating entity \"sdram_clk_gen_altpll\" for hierarchy \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776382 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ula ula:ula_ " "Elaborating entity \"ula\" for hierarchy \"ula:ula_\"" { } { { "spectrum.sv" "ula_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 303 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776384 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll ula:ula_\|pll:pll_ " "Elaborating entity \"pll\" for hierarchy \"ula:ula_\|pll:pll_\"" { } { { "ula/ula.sv" "pll_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776385 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll ula:ula_\|pll:pll_\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"ula:ula_\|pll:pll_\|altpll:altpll_component\"" { } { { "pll.v" "altpll_component" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776395 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "ula:ula_\|pll:pll_\|altpll:altpll_component " "Elaborated megafunction instantiation \"ula:ula_\|pll:pll_\|altpll:altpll_component\"" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776398 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ula:ula_\|pll:pll_\|altpll:altpll_component " "Instantiated megafunction \"ula:ula_\|pll:pll_\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 2000 " "Parameter \"clk0_divide_by\" = \"2000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 1007 " "Parameter \"clk0_multiply_by\" = \"1007\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 25 " "Parameter \"clk1_divide_by\" = \"25\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 7 " "Parameter \"clk1_multiply_by\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 0 " "Parameter \"clk1_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_divide_by 25 " "Parameter \"clk2_divide_by\" = \"25\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_duty_cycle 50 " "Parameter \"clk2_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_multiply_by 12 " "Parameter \"clk2_multiply_by\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_phase_shift 0 " "Parameter \"clk2_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=pll " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=pll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776399 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED "
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/pll_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/pll_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_altpll " "Found entity 1: pll_altpll" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648899776448 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648899776448 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll_altpll ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated " "Elaborating entity \"pll_altpll\" for hierarchy \"ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776449 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clocks ula:ula_\|clocks:clocks_ " "Elaborating entity \"clocks\" for hierarchy \"ula:ula_\|clocks:clocks_\"" { } { { "ula/ula.sv" "clocks_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 85 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776450 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_loader ula:ula_\|i2c_loader:i2c_loader_ " "Elaborating entity \"i2c_loader\" for hierarchy \"ula:ula_\|i2c_loader:i2c_loader_\"" { } { { "ula/ula.sv" "i2c_loader_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 124 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776451 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2s_intf ula:ula_\|i2s_intf:i2s_intf_ " "Elaborating entity \"i2s_intf\" for hierarchy \"ula:ula_\|i2s_intf:i2s_intf_\"" { } { { "ula/ula.sv" "i2s_intf_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 144 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776453 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "video ula:ula_\|video:video_ " "Elaborating entity \"video\" for hierarchy \"ula:ula_\|video:video_\"" { } { { "ula/ula.sv" "video_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 158 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776454 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ps2_keyboard ula:ula_\|ps2_keyboard:ps2_keyboard_ " "Elaborating entity \"ps2_keyboard\" for hierarchy \"ula:ula_\|ps2_keyboard:ps2_keyboard_\"" { } { { "ula/ula.sv" "ps2_keyboard_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 167 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776456 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "zx_keyboard ula:ula_\|zx_keyboard:zx_keyboard_ " "Elaborating entity \"zx_keyboard\" for hierarchy \"ula:ula_\|zx_keyboard:zx_keyboard_\"" { } { { "ula/ula.sv" "zx_keyboard_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 170 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776457 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "z80_top_direct_n z80_top_direct_n:z80_ " "Elaborating entity \"z80_top_direct_n\" for hierarchy \"z80_top_direct_n:z80_\"" { } { { "spectrum.sv" "z80_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 347 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776460 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_delay z80_top_direct_n:z80_\|clk_delay:clk_delay_ " "Elaborating entity \"clk_delay\" for hierarchy \"z80_top_direct_n:z80_\|clk_delay:clk_delay_\"" { } { { "cpu/toplevel/coremodules.vh" "clk_delay_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 20 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776463 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_state z80_top_direct_n:z80_\|decode_state:decode_state_ " "Elaborating entity \"decode_state\" for hierarchy \"z80_top_direct_n:z80_\|decode_state:decode_state_\"" { } { { "cpu/toplevel/coremodules.vh" "decode_state_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 46 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776464 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "execute z80_top_direct_n:z80_\|execute:execute_ " "Elaborating entity \"execute\" for hierarchy \"z80_top_direct_n:z80_\|execute:execute_\"" { } { { "cpu/toplevel/coremodules.vh" "execute_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 180 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776465 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "interrupts z80_top_direct_n:z80_\|interrupts:interrupts_ " "Elaborating entity \"interrupts\" for hierarchy \"z80_top_direct_n:z80_\|interrupts:interrupts_\"" { } { { "cpu/toplevel/coremodules.vh" "interrupts_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 199 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776479 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ir z80_top_direct_n:z80_\|ir:ir_ " "Elaborating entity \"ir\" for hierarchy \"z80_top_direct_n:z80_\|ir:ir_\"" { } { { "cpu/toplevel/coremodules.vh" "ir_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 208 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776480 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pin_control z80_top_direct_n:z80_\|pin_control:pin_control_ " "Elaborating entity \"pin_control\" for hierarchy \"z80_top_direct_n:z80_\|pin_control:pin_control_\"" { } { { "cpu/toplevel/coremodules.vh" "pin_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 223 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776481 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pla_decode z80_top_direct_n:z80_\|pla_decode:pla_decode_ " "Elaborating entity \"pla_decode\" for hierarchy \"z80_top_direct_n:z80_\|pla_decode:pla_decode_\"" { } { { "cpu/toplevel/coremodules.vh" "pla_decode_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 229 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776481 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "resets z80_top_direct_n:z80_\|resets:resets_ " "Elaborating entity \"resets\" for hierarchy \"z80_top_direct_n:z80_\|resets:resets_\"" { } { { "cpu/toplevel/coremodules.vh" "resets_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 240 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776483 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "memory_ifc z80_top_direct_n:z80_\|memory_ifc:memory_ifc_ " "Elaborating entity \"memory_ifc\" for hierarchy \"z80_top_direct_n:z80_\|memory_ifc:memory_ifc_\"" { } { { "cpu/toplevel/coremodules.vh" "memory_ifc_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 264 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776484 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sequencer z80_top_direct_n:z80_\|sequencer:sequencer_ " "Elaborating entity \"sequencer\" for hierarchy \"z80_top_direct_n:z80_\|sequencer:sequencer_\"" { } { { "cpu/toplevel/coremodules.vh" "sequencer_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 286 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776485 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_control z80_top_direct_n:z80_\|alu_control:alu_control_ " "Elaborating entity \"alu_control\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 326 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776486 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_4 z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_4:b2v_inst_cond_mux " "Elaborating entity \"alu_mux_4\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_4:b2v_inst_cond_mux\"" { } { { "cpu/alu/alu_control.v" "b2v_inst_cond_mux" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 205 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776487 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_8 z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux " "Elaborating entity \"alu_mux_8\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\"" { } { { "cpu/alu/alu_control.v" "b2v_inst_shift_mux" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 227 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776488 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_select z80_top_direct_n:z80_\|alu_select:alu_select_ " "Elaborating entity \"alu_select\" for hierarchy \"z80_top_direct_n:z80_\|alu_select:alu_select_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_select_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 363 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776489 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_flags z80_top_direct_n:z80_\|alu_flags:alu_flags_ " "Elaborating entity \"alu_flags\" for hierarchy \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_flags_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 405 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776489 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_2 z80_top_direct_n:z80_\|alu_flags:alu_flags_\|alu_mux_2:b2v_inst_mux_cf " "Elaborating entity \"alu_mux_2\" for hierarchy \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|alu_mux_2:b2v_inst_mux_cf\"" { } { { "cpu/alu/alu_flags.v" "b2v_inst_mux_cf" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 344 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776490 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu z80_top_direct_n:z80_\|alu:alu_ " "Elaborating entity \"alu\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 448 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776491 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_core z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core " "Elaborating entity \"alu_core\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\"" { } { { "cpu/alu/alu.v" "b2v_core" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 170 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776493 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_slice z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\|alu_slice:b2v_alu_slice_bit_0 " "Elaborating entity \"alu_slice\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\|alu_slice:b2v_alu_slice_bit_0\"" { } { { "cpu/alu/alu_core.v" "b2v_alu_slice_bit_0" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 61 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776493 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_bit_select z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select " "Elaborating entity \"alu_bit_select\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\"" { } { { "cpu/alu/alu.v" "b2v_input_bit_select" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 186 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776496 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_shifter_core z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift " "Elaborating entity \"alu_shifter_core\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\"" { } { { "cpu/alu/alu.v" "b2v_input_shift" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 197 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776496 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_2z z80_top_direct_n:z80_\|alu:alu_\|alu_mux_2z:b2v_op1_latch_mux_high " "Elaborating entity \"alu_mux_2z\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_2z:b2v_op1_latch_mux_high\"" { } { { "cpu/alu/alu.v" "b2v_op1_latch_mux_high" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 318 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776497 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_3z z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low " "Elaborating entity \"alu_mux_3z\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\"" { } { { "cpu/alu/alu.v" "b2v_op1_latch_mux_low" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 328 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776498 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_prep_daa z80_top_direct_n:z80_\|alu:alu_\|alu_prep_daa:b2v_prep_daa " "Elaborating entity \"alu_prep_daa\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_prep_daa:b2v_prep_daa\"" { } { { "cpu/alu/alu.v" "b2v_prep_daa" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 364 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776499 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_file z80_top_direct_n:z80_\|reg_file:reg_file_ " "Elaborating entity \"reg_file\" for hierarchy \"z80_top_direct_n:z80_\|reg_file:reg_file_\"" { } { { "cpu/toplevel/coremodules.vh" "reg_file_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 484 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776500 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_latch z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi " "Elaborating entity \"reg_latch\" for hierarchy \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\"" { } { { "cpu/registers/reg_file.v" "b2v_latch_af2_hi" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 279 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776502 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_control z80_top_direct_n:z80_\|reg_control:reg_control_ " "Elaborating entity \"reg_control\" for hierarchy \"z80_top_direct_n:z80_\|reg_control:reg_control_\"" { } { { "cpu/toplevel/coremodules.vh" "reg_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 531 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776514 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_latch z80_top_direct_n:z80_\|address_latch:address_latch_ " "Elaborating entity \"address_latch\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\"" { } { { "cpu/toplevel/coremodules.vh" "address_latch_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 547 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776515 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_mux z80_top_direct_n:z80_\|address_latch:address_latch_\|address_mux:b2v_inst7 " "Elaborating entity \"address_mux\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|address_mux:b2v_inst7\"" { } { { "cpu/bus/address_latch.v" "b2v_inst7" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 106 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776517 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "inc_dec z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec " "Elaborating entity \"inc_dec\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\"" { } { { "cpu/bus/address_latch.v" "b2v_inst_inc_dec" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 116 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776518 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "inc_dec_2bit z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\|inc_dec_2bit:b2v_dual_adder_0 " "Elaborating entity \"inc_dec_2bit\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\|inc_dec_2bit:b2v_dual_adder_0\"" { } { { "cpu/bus/inc_dec.v" "b2v_dual_adder_0" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 80 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776519 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bus_control z80_top_direct_n:z80_\|bus_control:bus_control_ " "Elaborating entity \"bus_control\" for hierarchy \"z80_top_direct_n:z80_\|bus_control:bus_control_\"" { } { { "cpu/toplevel/coremodules.vh" "bus_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 553 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776522 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bus_switch z80_top_direct_n:z80_\|bus_switch:bus_switch_ " "Elaborating entity \"bus_switch\" for hierarchy \"z80_top_direct_n:z80_\|bus_switch:bus_switch_\"" { } { { "cpu/toplevel/coremodules.vh" "bus_switch_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 566 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776523 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_switch z80_top_direct_n:z80_\|data_switch:sw2_ " "Elaborating entity \"data_switch\" for hierarchy \"z80_top_direct_n:z80_\|data_switch:sw2_\"" { } { { "cpu/toplevel/core.vh" "sw2_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 36 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776524 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_switch_mask z80_top_direct_n:z80_\|data_switch_mask:sw1_ " "Elaborating entity \"data_switch_mask\" for hierarchy \"z80_top_direct_n:z80_\|data_switch_mask:sw1_\"" { } { { "cpu/toplevel/core.vh" "sw1_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 39 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776524 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_pins z80_top_direct_n:z80_\|address_pins:address_pins_ " "Elaborating entity \"address_pins\" for hierarchy \"z80_top_direct_n:z80_\|address_pins:address_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "address_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 41 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776525 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_pins z80_top_direct_n:z80_\|data_pins:data_pins_ " "Elaborating entity \"data_pins\" for hierarchy \"z80_top_direct_n:z80_\|data_pins:data_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "data_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 51 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776526 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control_pins_n z80_top_direct_n:z80_\|control_pins_n:control_pins_ " "Elaborating entity \"control_pins_n\" for hierarchy \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "control_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648899776527 ""}
{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a0 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a0\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 47 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a1 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a1\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 72 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a2 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a2\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 97 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a3 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a3\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 122 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 182 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899776831 "|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a4 " "Synthesized away node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|ram_block1a4\"" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 147 2 0 } } { "altsyncram.tdf" "" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spe
{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1648899781398 ""}
{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[0\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[0\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[1\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[1\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[2\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[2\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[3\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[3\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[4\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[4\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781498 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[5\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[5\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } }
{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[0\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[0\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[7\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[7\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[6\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[6\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[5\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high\[0\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[4\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[3\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648899781504 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[2\] z80_top_direct_n:z80_\|ir:ir_\|op
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 52 -1 0 } } { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 127 -1 0 } } { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 201 -1 0 } } { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 42 -1 0 } } { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 93 -1 0 } } { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 97 -1 0 } } { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 108 -1 0 } } { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 109 -1 0 } } { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 33 -1 0 } } { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 59 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1648899781529 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1648899781529 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[1\] GND " "Pin \"LED\[1\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648899784991 "|spectrum|LED[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[4\] GND " "Pin \"LED\[4\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648899784991 "|spectrum|LED[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[5\] GND " "Pin \"LED\[5\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648899784991 "|spectrum|LED[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[6\] GND " "Pin \"LED\[6\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648899784991 "|spectrum|LED[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[7\] GND " "Pin \"LED\[7\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648899784991 "|spectrum|LED[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[24\] VCC " "Pin \"GPIO_1\[24\]\" is stuck at VCC" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648899784991 "|spectrum|GPIO_1[24]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[32\] GND " "Pin \"GPIO_1\[32\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648899784991 "|spectrum|GPIO_1[32]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[33\] GND " "Pin \"GPIO_1\[33\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648899784991 "|spectrum|GPIO_1[33]"} { "Warning" "WMLS_MLS_STUCK_PIN" "DRAM_CKE VCC " "Pin \"DRAM_CKE\" is stuck at VCC" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 27 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648899784991 "|spectrum|DRAM_CKE"} { "Warning" "WMLS_MLS_STUCK_PIN" "DRAM_CS_N GND " "Pin \"DRAM_CS_N\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 30 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648899784991 "|spectrum|DRAM_CS_N"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1648899784991 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648899785379 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1648899788636 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1648899788723 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "2 0 2 0 0 " "Adding 2 node(s), including 0 DDIO, 2 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648899788976 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899788976 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[0\] " "No output dependent on input pin \"SW\[0\]\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899789231 "|spectrum|SW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[3\] " "No output dependent on input pin \"SW\[3\]\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899789231 "|spectrum|SW[3]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1648899789231 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "2957 " "Implemented 2957 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Implemented 11 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648899789231 ""} { "Info" "ICUT_CUT_TM_OPINS" "85 " "Implemented 85 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648899789231 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "18 " "Implemented 18 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1648899789231 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2809 " "Implemented 2809 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648899789231 ""} { "Info" "ICUT_CUT_TM_RAMS" "32 " "Implemented 32 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1648899789231 ""} { "Info" "ICUT_CUT_TM_PLLS" "2 " "Implemented 2 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "Quartus II" 0 -1 1648899789231 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648899789231 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 146 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 146 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "457 " "Peak virtual memory: 457 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648899789255 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 14:43:09 2022 " "Processing ended: Sat Apr 2 14:43:09 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648899789255 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Elapsed time: 00:00:15" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648899789255 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:14 " "Total CPU time (on all processors): 00:00:14" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648899789255 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648899789255 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648899790598 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648899790599 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 14:43:10 2022 " "Processing started: Sat Apr 2 14:43:10 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648899790599 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1648899790599 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_fit --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1648899790599 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1648899790623 ""}
{ "Info" "0" "" "Project = spectrum" { } { } 0 0 "Project = spectrum" 0 0 "Fitter" 0 0 1648899790624 ""}
{ "Info" "0" "" "Revision = spectrum" { } { } 0 0 "Revision = spectrum" 0 0 "Fitter" 0 0 1648899790624 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1648899790713 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "spectrum EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"spectrum\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1648899790729 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648899790766 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648899790767 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648899790767 ""}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] 2 1 0 0 " "Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 43 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1261 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648899790833 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] 2 1 108 3000 " "Implementing clock multiplication of 2, clock division of 1, and phase shift of 108 degrees (3000 ps) for sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 43 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1262 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648899790833 ""} } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 43 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1261 9662 10382 0} } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1648899790833 ""}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] 141 280 0 0 " "Implementing clock multiplication of 141, clock division of 280, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1229 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648899790835 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] 47 168 0 0 " "Implementing clock multiplication of 47, clock division of 168, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1230 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648899790835 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] 47 98 0 0 " "Implementing clock multiplication of 47, clock division of 98, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1231 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648899790835 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1229 9662 10382 0} } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1648899790835 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1648899790913 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1648899790924 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648899791139 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648899791139 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648899791139 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1648899791139 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5104 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648899791146 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5106 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648899791146 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5108 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648899791146 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5110 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648899791146 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5112 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648899791146 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1648899791146 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1648899791149 ""}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1648899791155 ""}
{ "Warning" "WFSAC_FSAC_PLL_MERGING_PARAMETERS_MISMATCH_WARNING" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 " "The parameters of the PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 and the PLL sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 do not have the same values - hence these PLLs cannot be merged" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "M sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"M\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "M sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 10 " "The value of the parameter \"M\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 10" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "M ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 141 " "The value of the parameter \"M\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 141" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "N sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"N\" do not match for the PLL atoms sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 and PLL ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "N sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 1 " "The value of the parameter \"N\" for the PLL atom sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 is 1" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "N ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 7 " "The value of the parameter \"N\" for the PLL atom ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 is 7" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Quartus II" 0 -1 1648899791688 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "LOOP FILTER R sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 " "The values of the parameter \"LOOP FILTER R\" do not match for the PLL atoms sdram_controller:sdram_\|s
{ "Critical Warning" "WFSAC_FSAC_PLL_FED_BY_REMOTE_CLOCK_PIN_NOT_COMPENSATED" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1 0 Pin_R8 " "PLL \"sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|pll1\" input clock inclk\[0\] is not fully compensated because it is fed by a remote clock pin \"Pin_R8\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 216 0 0 } } { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 77 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1261 9662 10382 0} } } } } 1 176598 "PLL \"%1!s!\" input clock inclk\[%2!d!\] is not fully compensated because it is fed by a remote clock pin \"%3!s!\"" 0 0 "Fitter" 0 -1 1648899791706 ""}
{ "Info" "ISTA_SDC_FOUND" "spectrum.sdc " "Reading SDC File: 'spectrum.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1648899792341 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 12 KEY1 port " "Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648899792349 ""}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock spectrum.sdc 12 Argument <targets> is an empty collection " "Ignored create_clock at spectrum.sdc(12): Argument <targets> is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\] " "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792349 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1648899792349 ""}
{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792351 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792351 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792351 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792351 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792351 ""} } { } 0 332110 "%1!s!" 0 0 "Fitter" 0 -1 1648899792351 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 21 ula_\|clocks_\|clk_cpu\|regout pin " "Ignored filter at spectrum.sdc(21): ula_\|clocks_\|clk_cpu\|regout could not be matched with a pin" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648899792352 ""}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_generated_clock spectrum.sdc 21 Argument <targets> is an empty collection " "Ignored create_generated_clock at spectrum.sdc(21): Argument <targets> is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\] " "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792352 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1648899792352 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Fitter" 0 -1 1648899792352 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 56 clk_cpu clock " "Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 56 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648899792353 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 57 KEY1 clock " "Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 57 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648899792353 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[0\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[0\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648899792353 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[1\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[1\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648899792353 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[2\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[2\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648899792353 ""}
{ "Warning" "WSTA_SCC_LOOP" "507 " "Found combinational loop of 507 nodes" { { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|combout " "Node \"z80_\|bus_control_\|db\[4\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~18\|datab " "Node \"z80_\|alu_\|db_high\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~18\|combout " "Node \"z80_\|alu_\|db_high\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|combout " "Node \"z80_\|alu_\|db_high\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|combout " "Node \"z80_\|alu_\|db_high\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|datab " "Node \"z80_\|alu_\|db\[4\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|combout " "Node \"z80_\|alu_\|db\[4\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|datab " "Node \"z80_\|alu_\|db_high\[0\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|combout " "Node \"z80_\|alu_\|db_high\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|datac " "Node \"z80_\|alu_\|db_high\[0\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~53\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~53\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~55\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~55\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~55\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~55\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~56\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~56\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~56\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~56\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~57\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~57\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~57\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~57\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899792360 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~13\|dataa " "Node \"z80_\|reg_file_\|db_hi_a
{ "Critical Warning" "WSTA_SCC_LOOP_TOO_BIG" "507 " "Design contains combinational loop of 507 nodes. Estimating the delays through the loop." { } { } 1 332081 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0 "Fitter" 0 -1 1648899792376 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1648899792410 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1648899792410 "|spectrum|KEY[1]"}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1648899792425 ""}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1648899792427 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 7 clocks " "Found 7 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792427 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792427 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 beep " " 10.000 beep" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792427 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 CLOCK_50 " " 20.000 CLOCK_50" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792427 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 10.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792427 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 10.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792427 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 39.716 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 39.716 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792427 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 71.489 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 71.489 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792427 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 41.702 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 41.702 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648899792427 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1648899792427 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) " "Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G15 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G15" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792619 ""} } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5089 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792619 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C1 of PLL_1) " "Automatically promoted node sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C1 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792619 ""} } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 77 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1261 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792619 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C0 of PLL_1) " "Automatically promoted node sdram_controller:sdram_\|sdram_clk_gen:sdram_clk_pll\|altpll:altpll_component\|sdram_clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C0 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792619 ""} { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations External Clock Output CLKCTRL_PLL1E0 " "Automatically promoted destinations to use location or clock signal External Clock Output CLKCTRL_PLL1E0" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792619 ""} } { { "db/sdram_clk_gen_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/sdram_clk_gen_altpll.v" 77 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1261 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792619 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1229 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792620 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G17 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1229 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792620 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1229 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792620 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|clocks:clocks_\|clk_cpu " "Automatically promoted node ula:ula_\|clocks:clocks_\|clk_cpu " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ula:ula_\|clocks:clocks_\|clk_cpu~0 " "Destination node ula:ula_\|clocks:clocks_\|clk_cpu~0" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 31 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|clocks:clocks_|clk_cpu~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 2809 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648899792620 ""} } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 31 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|clocks:clocks_|clk_cpu } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1227 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792620 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "reset " "Automatically promoted node reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "z80_top_direct_n:z80_\|resets:resets_\|x1~0 " "Destination node z80_top_direct_n:z80_\|resets:resets_\|x1~0" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 42 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|resets:resets_|x1~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4150 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648899792620 ""} } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 73 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1471 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792620 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|resets:resets_\|SYNTHESIZED_WIRE_12 " "Automatically promoted node z80_top_direct_n:z80_\|resets:resets_\|SYNTHESIZED_WIRE_12 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[30\]~output " "Destination node GPIO_1\[30\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[30]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4185 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[0\]~output " "Destination node GPIO_1\[0\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[0]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4158 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[1\]~output " "Destination node GPIO_1\[1\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[1]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4159 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[2\]~output " "Destination node GPIO_1\[2\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[2]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4160 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[3\]~output " "Destination node GPIO_1\[3\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[3]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4161 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648899792620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[4\]~output " "Destination node GPIO_1\[4\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[4]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 4162 9662 10382 0} } } } } 0 1
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|fpga_reset " "Automatically promoted node z80_top_direct_n:z80_\|fpga_reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792621 ""} } { { "cpu/toplevel/core.vh" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 13 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|fpga_reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 917 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792621 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|interrupts:interrupts_\|SYNTHESIZED_WIRE_12 " "Automatically promoted node z80_top_direct_n:z80_\|interrupts:interrupts_\|SYNTHESIZED_WIRE_12 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648899792621 ""} } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 76 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_12 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 754 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648899792621 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1648899793449 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648899793453 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648899793453 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648899793457 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648899793462 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1648899793466 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1648899793466 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1648899793469 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1648899794289 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "8 I/O Input Buffer " "Packed 8 registers into blocks of type I/O Input Buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Quartus II" 0 -1 1648899794293 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "29 I/O Output Buffer " "Packed 29 registers into blocks of type I/O Output Buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Quartus II" 0 -1 1648899794293 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "15 " "Created 15 register duplicates" { } { } 1 176220 "Created %1!d! register duplicates" 0 0 "Quartus II" 0 -1 1648899794293 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1648899794293 ""}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_ASDO " "Node \"EPCS_ASDO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_ASDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DATA0 " "Node \"EPCS_DATA0\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DCLK " "Node \"EPCS_DCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_NCSO " "Node \"EPCS_NCSO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_NCSO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648899794431 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Fitter preparation operations ending: elapsed time is 00:00:03" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648899794433 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1648899795941 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648899796762 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1648899796784 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1648899799543 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648899799543 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1648899800437 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "4 " "Router estimated average interconnect usage is 4% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "21 X21_Y11 X31_Y22 " "Router estimated peak interconnect usage is 21% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22" { } { { "loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 1 { 0 "Router estimated peak interconnect usage is 21% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} { { 11 { 0 "Router estimated peak interconnect usage is 21% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} 21 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1648899803211 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1648899803211 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:05 " "Fitter routing operations ending: elapsed time is 00:00:05" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648899805930 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1648899805932 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1648899805932 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "1.88 " "Total time spent on timing analysis during the Fitter is 1.88 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1648899806074 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648899806133 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648899806898 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648899806949 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648899807650 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648899808810 ""}
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1648899809279 ""}
{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "57 Cyclone IV E " "57 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[0\] 3.3-V LVTTL M1 " "Pin SW\[0\] uses I/O standard 3.3-V LVTTL at M1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 149 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[3\] 3.3-V LVTTL M15 " "Pin SW\[3\] uses I/O standard 3.3-V LVTTL at M15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 152 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[0\] 3.3-V LVTTL F13 " "Pin GPIO_1\[0\] uses I/O standard 3.3-V LVTTL at F13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 153 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[1\] 3.3-V LVTTL T15 " "Pin GPIO_1\[1\] uses I/O standard 3.3-V LVTTL at T15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 154 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648899809297 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[2\] 3.3-V LVTTL T14 " "Pin GPIO_1\[2\] uses I/O standard 3.3-V
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1648899809632 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 568 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 568 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "639 " "Peak virtual memory: 639 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648899810355 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 14:43:30 2022 " "Processing ended: Sat Apr 2 14:43:30 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648899810355 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:20 " "Elapsed time: 00:00:20" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648899810355 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:20 " "Total CPU time (on all processors): 00:00:20" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648899810355 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1648899810355 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1648899812346 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648899812347 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 14:43:32 2022 " "Processing started: Sat Apr 2 14:43:32 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648899812347 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648899812347 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648899812347 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648899813443 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648899813473 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "375 " "Peak virtual memory: 375 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648899813776 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 14:43:33 2022 " "Processing ended: Sat Apr 2 14:43:33 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648899813776 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648899813776 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648899813776 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648899813776 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1648899814393 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1648899815598 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648899815599 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 14:43:35 2022 " "Processing started: Sat Apr 2 14:43:35 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648899815599 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648899815599 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648899815599 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648899815626 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648899815806 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648899815807 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648899815847 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648899815848 ""}
{ "Info" "ISTA_SDC_FOUND" "spectrum.sdc " "Reading SDC File: 'spectrum.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1648899816257 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 12 KEY1 port " "Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648899816265 ""}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock spectrum.sdc 12 Argument <targets> is an empty collection " "Ignored create_clock at spectrum.sdc(12): Argument <targets> is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\] " "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816266 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Quartus II" 0 -1 1648899816266 ""}
{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816267 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816267 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816267 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816267 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase 108.00 -duty_cycle 50.00 -name \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816267 ""} } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816267 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 21 ula_\|clocks_\|clk_cpu\|regout pin " "Ignored filter at spectrum.sdc(21): ula_\|clocks_\|clk_cpu\|regout could not be matched with a pin" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648899816267 ""}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_generated_clock spectrum.sdc 21 Argument <targets> is an empty collection " "Ignored create_generated_clock at spectrum.sdc(21): Argument <targets> is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\] " "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816267 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Quartus II" 0 -1 1648899816267 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Quartus II" 0 -1 1648899816268 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 56 clk_cpu clock " "Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 56 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648899816269 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 57 KEY1 clock " "Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 57 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648899816269 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[0\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[0\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648899816269 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[1\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[1\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648899816269 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[2\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[2\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648899816269 ""}
{ "Warning" "WSTA_SCC_LOOP" "507 " "Found combinational loop of 507 nodes" { { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|combout " "Node \"z80_\|bus_control_\|db\[1\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~22\|datad " "Node \"z80_\|alu_control_\|db\[1\]~22\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~22\|combout " "Node \"z80_\|alu_control_\|db\[1\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~23\|datac " "Node \"z80_\|alu_control_\|db\[1\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~23\|combout " "Node \"z80_\|alu_control_\|db\[1\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~23\|dataa " "Node \"z80_\|alu_\|db\[1\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~23\|combout " "Node \"z80_\|alu_\|db\[1\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~24\|datab " "Node \"z80_\|alu_\|db\[1\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~24\|combout " "Node \"z80_\|alu_\|db\[1\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|datac " "Node \"z80_\|alu_\|db_low\[1\]~13\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~13\|combout " "Node \"z80_\|alu_\|db_low\[1\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|datac " "Node \"z80_\|alu_\|db_low\[1\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|combout " "Node \"z80_\|alu_\|db_low\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~24\|datac " "Node \"z80_\|alu_\|db\[1\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|datab " "Node \"z80_\|alu_\|db_low\[0\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|combout " "Node \"z80_\|alu_\|db_low\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|datad " "Node \"z80_\|alu_\|db_low\[0\]~22\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|combout " "Node \"z80_\|alu_\|db_low\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|combout " "Node \"z80_\|alu_\|db_low\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|datac " "Node \"z80_\|alu_\|db\[0\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648899816276 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~17\|combout " "Node \"z80_\|alu
{ "Critical Warning" "WSTA_SCC_LOOP_TOO_BIG" "507 " "Design contains combinational loop of 507 nodes. Estimating the delays through the loop." { } { } 1 332081 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0 "Quartus II" 0 -1 1648899816292 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648899816322 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648899816322 "|spectrum|KEY[1]"}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816452 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648899816455 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648899816475 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648899816506 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648899816506 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -18.375 " "Worst-case setup slack is -18.375" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816507 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816507 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -18.375 -543.462 CLOCK_50 " " -18.375 -543.462 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816507 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.723 -41.132 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.723 -41.132 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816507 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.035 -48.241 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -3.035 -48.241 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816507 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.914 -2.914 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.914 -2.914 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816507 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.057 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.057 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816507 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.477 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 3.477 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816507 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899816507 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.953 " "Worst-case hold slack is -0.953" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816512 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816512 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.953 -14.699 CLOCK_50 " " -0.953 -14.699 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816512 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816512 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816512 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.357 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.357 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816512 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.358 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.358 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816512 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 7.936 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 7.936 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816512 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899816512 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -6.224 " "Worst-case recovery slack is -6.224" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816513 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816513 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.224 -458.974 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -6.224 -458.974 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816513 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899816513 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 3.682 " "Worst-case removal slack is 3.682" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816514 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816514 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.682 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 3.682 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816514 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899816514 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.752 " "Worst-case minimum pulse width slack is 4.752" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.752 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.752 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.776 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 4.776 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.488 0.000 CLOCK_50 " " 9.488 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.603 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.603 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.593 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.593 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.503 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.503 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899816515 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899816515 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648899816659 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648899816695 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648899817630 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648899817793 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648899817793 "|spectrum|KEY[1]"}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817795 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648899817812 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648899817812 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -17.547 " "Worst-case setup slack is -17.547" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -17.547 -513.385 CLOCK_50 " " -17.547 -513.385 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.416 -38.471 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.416 -38.471 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.785 -2.785 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.785 -2.785 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.660 -42.274 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -2.660 -42.274 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.134 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.134 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.130 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.130 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817816 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899817816 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.767 " "Worst-case hold slack is -0.767" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817824 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817824 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.767 -11.715 CLOCK_50 " " -0.767 -11.715 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817824 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817824 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817824 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.311 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.311 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817824 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.312 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.312 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817824 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 7.928 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 7.928 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817824 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899817824 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -5.744 " "Worst-case recovery slack is -5.744" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817828 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817828 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.744 -423.185 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -5.744 -423.185 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817828 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899817828 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 3.356 " "Worst-case removal slack is 3.356" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817832 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817832 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.356 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 3.356 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817832 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899817832 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.748 " "Worst-case minimum pulse width slack is 4.748" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817836 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817836 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.748 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.748 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817836 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.792 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 4.792 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817836 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.487 0.000 CLOCK_50 " " 9.487 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817836 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.598 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.598 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817836 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.588 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.588 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817836 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.491 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.491 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899817836 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899817836 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648899818028 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648899818319 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648899818319 "|spectrum|KEY[1]"}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818321 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648899818328 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648899818328 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -15.145 " "Worst-case setup slack is -15.145" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818335 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818335 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -15.145 -411.914 CLOCK_50 " " -15.145 -411.914 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818335 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.764 -34.680 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -3.764 -34.680 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818335 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.784 -2.784 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.784 -2.784 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818335 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.778 -28.278 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -1.778 -28.278 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818335 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.051 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.051 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818335 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.528 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 5.528 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818335 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899818335 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.677 " "Worst-case hold slack is -0.677" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.677 -10.405 CLOCK_50 " " -0.677 -10.405 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.177 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.177 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.178 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.178 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.186 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.186 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 7.892 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 7.892 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818346 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899818346 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.692 " "Worst-case recovery slack is -4.692" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818353 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818353 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.692 -358.022 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.692 -358.022 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818353 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899818353 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 2.517 " "Worst-case removal slack is 2.517" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.517 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 2.517 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818360 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899818360 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.784 " "Worst-case minimum pulse width slack is 4.784" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818367 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818367 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.784 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.784 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818367 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.790 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 4.790 0.000 sdram_\|sdram_clk_pll\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818367 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.208 0.000 CLOCK_50 " " 9.208 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818367 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.640 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.640 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818367 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818367 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.535 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.535 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648899818367 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648899818367 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648899819047 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648899819047 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 528 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 528 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "445 " "Peak virtual memory: 445 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648899819312 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 14:43:39 2022 " "Processing ended: Sat Apr 2 14:43:39 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648899819312 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648899819312 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648899819312 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648899819312 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648899821564 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648899821565 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 14:43:41 2022 " "Processing started: Sat Apr 2 14:43:41 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648899821565 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648899821565 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648899821566 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648899822459 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648899822787 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648899823112 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648899823439 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648899823700 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648899823957 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648899824212 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648899824471 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "380 " "Peak virtual memory: 380 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648899824563 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 14:43:44 2022 " "Processing ended: Sat Apr 2 14:43:44 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648899824563 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648899824563 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648899824563 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648899824563 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 1242 s " "Quartus II Full Compilation was successful. 0 errors, 1242 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648899825249 ""}
