2022-03-30 14:57:41 +03:00
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module spectrum(input CLOCK_50,
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output wire[7:0] LED,
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output wire[33:0] GPIO_0);
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// ROM, 16K
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wire[7:0] rom_data;
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rom0 rom(
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.address(A),
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.clock(CLOCK_50),
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.q(rom_data)
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);
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reg [15:0] A; // Global address bus
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wire [7:0] D; // CPU data bus
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wire [7:0] ram0_data; // Internal 16K RAM data
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wire RamWE;
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// assign RamWE = A[15:14] == 2'b01 && nIORQ == 1 && nRD == 1 && nWR == 0;
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assign RamWE = 0;
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// VRAM, 16K
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wire[12:0] vram_address;
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wire[7:0] vram_data;
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ram16 ram0(
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.clock(CLOCK_50),
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.address_a(A[13:0]),
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.data_a(D),
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.q_a(ram0_data),
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.wren_a(0),
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// .address_b({1'b0, vram_address}),
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.address_b(A[13:0]),
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.data_b(8'b0),
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.q_b(vram_data),
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.wren_b(0)
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);
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// Rest of RAM, 32K
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wire[7:0] ram1_data;
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ram32 ram1(
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.clock(CLOCK_50),
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.address(A[14:0]),
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.data(D),
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.q(ram1_data),
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.wren(0)
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);
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reg[21:0] counter;
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always @(posedge CLOCK_50)
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begin
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counter <= counter + 1;
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if (counter == 0)
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begin
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A <= A + 1;
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end
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end
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2022-03-30 11:53:01 +03:00
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2022-03-30 14:57:41 +03:00
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// make the leds blink with rom and ram0 data
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assign LED[3:0] = rom_data[3:0];
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assign LED[7:4] = ram0_data[7:4];
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// expose memories at A to GPIO_0
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assign GPIO_0[7:0] = rom_data;
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assign GPIO_0[15:8] = ram0_data;
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assign GPIO_0[23:16] = ram1_data;
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assign GPIO_0[31:24] = vram_data;
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endmodule
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