de0-zx-spectrum/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo

// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// 
// Device: Altera EP4CE22F17C6 Package FBGA256
// 

//
// This file contains Slow Corner delays for the design using part EP4CE22F17C6,
// with speed grade 6, core voltage 1.2V, and temperature 0 Celsius
//

// 
// This SDF file should be used for ModelSim-Altera (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "spectrum")
  (DATE "03/30/2022 14:56:19")
  (VENDOR "Altera")
  (PROGRAM "Quartus II 32-bit")
  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
  (DIVIDER .)
  (TIMESCALE 1 ps)

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        (IOPATH i o (2194:2194:2194) (2119:2119:2119))
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    (CELLTYPE "cycloneive_io_obuf")
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    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0\[8\]\~output)
    (DELAY
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    (CELLTYPE "cycloneive_io_obuf")
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    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0\[10\]\~output)
    (DELAY
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    (CELLTYPE "cycloneive_io_obuf")
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    (CELLTYPE "cycloneive_io_obuf")
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    (CELLTYPE "cycloneive_io_obuf")
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    (CELLTYPE "cycloneive_io_obuf")
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    (CELLTYPE "cycloneive_io_obuf")
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    (INSTANCE GPIO_0\[28\]\~output)
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        (IOPATH i o (4033:4033:4033) (3610:3610:3610))
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    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0\[29\]\~output)
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    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0\[30\]\~output)
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    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO_0\[31\]\~output)
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    (INSTANCE CLOCK_50\~input)
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      (ABSOLUTE
        (IOPATH i o (459:459:459) (708:708:708))
      )
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  )
  (CELL
    (CELLTYPE "cycloneive_clkctrl")
    (INSTANCE CLOCK_50\~inputclkctrl)
    (DELAY
      (ABSOLUTE
        (PORT inclk[0] (133:133:133) (124:124:124))
      )
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  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[0\]\~63)
    (DELAY
      (ABSOLUTE
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      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[0\])
    (DELAY
      (ABSOLUTE
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        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
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    )
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    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[1\]\~21)
    (DELAY
      (ABSOLUTE
        (PORT dataa (230:230:230) (309:309:309))
        (PORT datab (227:227:227) (300:300:300))
        (IOPATH dataa combout (300:300:300) (323:323:323))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (306:306:306) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1344:1344:1344) (1361:1361:1361))
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        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
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    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[2\]\~23)
    (DELAY
      (ABSOLUTE
        (PORT datab (228:228:228) (299:299:299))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
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  )
  (CELL
    (CELLTYPE "dffeas")
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    (DELAY
      (ABSOLUTE
        (PORT clk (1344:1344:1344) (1361:1361:1361))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
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    )
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    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[3\]\~25)
    (DELAY
      (ABSOLUTE
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        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1344:1344:1344) (1361:1361:1361))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[4\]\~27)
    (DELAY
      (ABSOLUTE
        (PORT datab (228:228:228) (299:299:299))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[4\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1344:1344:1344) (1361:1361:1361))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[5\]\~29)
    (DELAY
      (ABSOLUTE
        (PORT datab (240:240:240) (309:309:309))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1344:1344:1344) (1361:1361:1361))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[6\]\~31)
    (DELAY
      (ABSOLUTE
        (PORT dataa (229:229:229) (306:306:306))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1344:1344:1344) (1361:1361:1361))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[7\]\~33)
    (DELAY
      (ABSOLUTE
        (PORT datab (226:226:226) (299:299:299))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1344:1344:1344) (1361:1361:1361))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[8\]\~35)
    (DELAY
      (ABSOLUTE
        (PORT dataa (229:229:229) (305:305:305))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[8\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1344:1344:1344) (1361:1361:1361))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[9\]\~37)
    (DELAY
      (ABSOLUTE
        (PORT datab (226:226:226) (298:298:298))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[9\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1344:1344:1344) (1361:1361:1361))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[10\]\~39)
    (DELAY
      (ABSOLUTE
        (PORT dataa (228:228:228) (302:302:302))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[10\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1344:1344:1344) (1361:1361:1361))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[11\]\~41)
    (DELAY
      (ABSOLUTE
        (PORT datab (238:238:238) (306:306:306))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[11\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1346:1346:1346) (1364:1364:1364))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[12\]\~43)
    (DELAY
      (ABSOLUTE
        (PORT datab (381:381:381) (418:418:418))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[12\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1346:1346:1346) (1364:1364:1364))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[13\]\~45)
    (DELAY
      (ABSOLUTE
        (PORT dataa (379:379:379) (426:426:426))
        (IOPATH dataa combout (318:318:318) (323:323:323))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[13\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1346:1346:1346) (1364:1364:1364))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[14\]\~47)
    (DELAY
      (ABSOLUTE
        (PORT dataa (229:229:229) (306:306:306))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[14\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1346:1346:1346) (1364:1364:1364))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[15\]\~49)
    (DELAY
      (ABSOLUTE
        (PORT datab (227:227:227) (300:300:300))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[15\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1346:1346:1346) (1364:1364:1364))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[16\]\~51)
    (DELAY
      (ABSOLUTE
        (PORT dataa (230:230:230) (306:306:306))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[16\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1346:1346:1346) (1364:1364:1364))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[17\]\~53)
    (DELAY
      (ABSOLUTE
        (PORT dataa (231:231:231) (309:309:309))
        (IOPATH dataa combout (318:318:318) (323:323:323))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[17\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1346:1346:1346) (1364:1364:1364))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[18\]\~55)
    (DELAY
      (ABSOLUTE
        (PORT datab (229:229:229) (301:301:301))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[18\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1346:1346:1346) (1364:1364:1364))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[19\]\~57)
    (DELAY
      (ABSOLUTE
        (PORT datab (229:229:229) (302:302:302))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[19\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1346:1346:1346) (1364:1364:1364))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[20\]\~59)
    (DELAY
      (ABSOLUTE
        (PORT datab (241:241:241) (311:311:311))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[20\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1346:1346:1346) (1364:1364:1364))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE counter\[21\]\~61)
    (DELAY
      (ABSOLUTE
        (PORT datad (218:218:218) (276:276:276))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE counter\[21\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1346:1346:1346) (1364:1364:1364))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~7)
    (DELAY
      (ABSOLUTE
        (PORT dataa (658:658:658) (684:684:684))
        (PORT datac (646:646:646) (673:673:673))
        (IOPATH dataa combout (329:329:329) (332:332:332))
        (IOPATH datac combout (218:218:218) (215:215:215))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~5)
    (DELAY
      (ABSOLUTE
        (PORT dataa (230:230:230) (307:307:307))
        (PORT datab (227:227:227) (299:299:299))
        (PORT datac (201:201:201) (272:272:272))
        (PORT datad (205:205:205) (267:267:267))
        (IOPATH dataa combout (309:309:309) (326:326:326))
        (IOPATH datab combout (309:309:309) (328:328:328))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (229:229:229) (305:305:305))
        (PORT datab (226:226:226) (299:299:299))
        (PORT datac (200:200:200) (270:270:270))
        (PORT datad (203:203:203) (265:265:265))
        (IOPATH dataa combout (309:309:309) (326:326:326))
        (IOPATH datab combout (309:309:309) (328:328:328))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (231:231:231) (309:309:309))
        (PORT datab (229:229:229) (302:302:302))
        (PORT datac (352:352:352) (391:391:391))
        (PORT datad (205:205:205) (267:267:267))
        (IOPATH dataa combout (309:309:309) (326:326:326))
        (IOPATH datab combout (309:309:309) (328:328:328))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (231:231:231) (308:308:308))
        (PORT datab (228:228:228) (301:301:301))
        (PORT datac (203:203:203) (275:275:275))
        (PORT datad (353:353:353) (388:388:388))
        (IOPATH dataa combout (309:309:309) (326:326:326))
        (IOPATH datab combout (309:309:309) (328:328:328))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~3)
    (DELAY
      (ABSOLUTE
        (PORT dataa (232:232:232) (310:310:310))
        (PORT datab (229:229:229) (303:303:303))
        (PORT datac (216:216:216) (283:283:283))
        (PORT datad (219:219:219) (277:277:277))
        (IOPATH dataa combout (309:309:309) (326:326:326))
        (IOPATH datab combout (309:309:309) (328:328:328))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (366:366:366) (368:368:368))
        (PORT datab (326:326:326) (341:341:341))
        (PORT datac (326:326:326) (330:330:330))
        (PORT datad (562:562:562) (556:556:556))
        (IOPATH dataa combout (265:265:265) (269:269:269))
        (IOPATH datab combout (265:265:265) (275:275:275))
        (IOPATH datac combout (218:218:218) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[0\]\~40)
    (DELAY
      (ABSOLUTE
        (PORT dataa (184:184:184) (221:221:221))
        (PORT datab (585:585:585) (577:577:577))
        (PORT datad (331:331:331) (338:338:338))
        (IOPATH dataa combout (287:287:287) (289:289:289))
        (IOPATH datab combout (295:295:295) (294:294:294))
        (IOPATH datac combout (312:312:312) (325:325:325))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1344:1344:1344) (1361:1361:1361))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[1\]\~14)
    (DELAY
      (ABSOLUTE
        (PORT dataa (418:418:418) (472:472:472))
        (PORT datab (414:414:414) (460:460:460))
        (IOPATH dataa combout (300:300:300) (323:323:323))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datab combout (306:306:306) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE Equal0\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (832:832:832) (847:847:847))
        (PORT datab (623:623:623) (657:657:657))
        (PORT datac (532:532:532) (528:528:528))
        (PORT datad (177:177:177) (199:199:199))
        (IOPATH dataa combout (267:267:267) (269:269:269))
        (IOPATH datab combout (267:267:267) (275:275:275))
        (IOPATH datac combout (218:218:218) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1673:1673:1673) (1692:1692:1692))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (728:728:728) (735:735:735))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[2\]\~16)
    (DELAY
      (ABSOLUTE
        (PORT datab (238:238:238) (307:307:307))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1673:1673:1673) (1692:1692:1692))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (728:728:728) (735:735:735))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[3\]\~18)
    (DELAY
      (ABSOLUTE
        (PORT datab (239:239:239) (307:307:307))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1673:1673:1673) (1692:1692:1692))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (728:728:728) (735:735:735))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[4\]\~20)
    (DELAY
      (ABSOLUTE
        (PORT dataa (241:241:241) (313:313:313))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[4\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1344:1344:1344) (1361:1361:1361))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (754:754:754) (770:770:770))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[5\]\~22)
    (DELAY
      (ABSOLUTE
        (PORT datab (258:258:258) (327:327:327))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1673:1673:1673) (1692:1692:1692))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (728:728:728) (735:735:735))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[6\]\~24)
    (DELAY
      (ABSOLUTE
        (PORT dataa (259:259:259) (334:334:334))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1673:1673:1673) (1692:1692:1692))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (728:728:728) (735:735:735))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[7\]\~26)
    (DELAY
      (ABSOLUTE
        (PORT dataa (259:259:259) (334:334:334))
        (IOPATH dataa combout (318:318:318) (323:323:323))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1673:1673:1673) (1692:1692:1692))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (728:728:728) (735:735:735))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[8\]\~28)
    (DELAY
      (ABSOLUTE
        (PORT datab (259:259:259) (329:329:329))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[8\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1673:1673:1673) (1692:1692:1692))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (728:728:728) (735:735:735))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[9\]\~30)
    (DELAY
      (ABSOLUTE
        (PORT datab (241:241:241) (310:310:310))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[9\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1673:1673:1673) (1692:1692:1692))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (728:728:728) (735:735:735))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[10\]\~32)
    (DELAY
      (ABSOLUTE
        (PORT datab (241:241:241) (310:310:310))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[10\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1673:1673:1673) (1692:1692:1692))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (728:728:728) (735:735:735))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[11\]\~34)
    (DELAY
      (ABSOLUTE
        (PORT datab (259:259:259) (329:329:329))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[11\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1673:1673:1673) (1692:1692:1692))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (728:728:728) (735:735:735))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[12\]\~36)
    (DELAY
      (ABSOLUTE
        (PORT dataa (242:242:242) (314:314:314))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH dataa cout (376:376:376) (275:275:275))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[12\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1673:1673:1673) (1692:1692:1692))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (728:728:728) (735:735:735))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[13\]\~38)
    (DELAY
      (ABSOLUTE
        (PORT datab (258:258:258) (327:327:327))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datab cout (385:385:385) (280:280:280))
        (IOPATH datad combout (119:119:119) (106:106:106))
        (IOPATH cin combout (408:408:408) (387:387:387))
        (IOPATH cin cout (50:50:50) (50:50:50))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[13\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1344:1344:1344) (1361:1361:1361))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (754:754:754) (770:770:770))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1889:1889:1889) (2031:2031:2031))
        (PORT d[1] (1875:1875:1875) (1962:1962:1962))
        (PORT d[2] (1726:1726:1726) (1801:1801:1801))
        (PORT d[3] (2301:2301:2301) (2375:2375:2375))
        (PORT d[4] (2031:2031:2031) (2119:2119:2119))
        (PORT d[5] (2026:2026:2026) (2091:2091:2091))
        (PORT d[6] (1989:1989:1989) (2041:2041:2041))
        (PORT d[7] (1895:1895:1895) (2026:2026:2026))
        (PORT d[8] (2179:2179:2179) (2233:2233:2233))
        (PORT d[9] (2010:2010:2010) (2105:2105:2105))
        (PORT d[10] (2114:2114:2114) (2221:2221:2221))
        (PORT d[11] (2121:2121:2121) (2200:2200:2200))
        (PORT d[12] (2184:2184:2184) (2285:2285:2285))
        (PORT clk (1642:1642:1642) (1671:1671:1671))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1642:1642:1642) (1671:1671:1671))
        (PORT d[0] (1682:1682:1682) (1734:1734:1734))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1643:1643:1643) (1672:1672:1672))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1609:1609:1609) (1637:1637:1637))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (880:880:880) (884:884:884))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (881:881:881) (885:885:885))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (881:881:881) (885:885:885))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (881:881:881) (885:885:885))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datac (1499:1499:1499) (1573:1573:1573))
        (IOPATH datac combout (220:220:220) (216:216:216))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1351:1351:1351) (1368:1368:1368))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (198:198:198) (255:255:255))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1351:1351:1351) (1368:1368:1368))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1934:1934:1934) (2067:2067:2067))
        (PORT d[1] (1839:1839:1839) (1927:1927:1927))
        (PORT d[2] (2024:2024:2024) (2095:2095:2095))
        (PORT d[3] (2074:2074:2074) (2161:2161:2161))
        (PORT d[4] (1995:1995:1995) (2072:2072:2072))
        (PORT d[5] (2000:2000:2000) (2056:2056:2056))
        (PORT d[6] (2003:2003:2003) (2061:2061:2061))
        (PORT d[7] (1918:1918:1918) (2045:2045:2045))
        (PORT d[8] (2168:2168:2168) (2228:2228:2228))
        (PORT d[9] (1971:1971:1971) (2048:2048:2048))
        (PORT d[10] (1839:1839:1839) (1960:1960:1960))
        (PORT d[11] (2109:2109:2109) (2197:2197:2197))
        (PORT d[12] (2116:2116:2116) (2206:2206:2206))
        (PORT clk (1635:1635:1635) (1663:1663:1663))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1635:1635:1635) (1663:1663:1663))
        (PORT d[0] (1600:1600:1600) (1591:1591:1591))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1636:1636:1636) (1664:1664:1664))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1602:1602:1602) (1629:1629:1629))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (873:873:873) (876:876:876))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (877:877:877))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (877:877:877))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (877:877:877))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (851:851:851) (834:834:834))
        (PORT datab (2309:2309:2309) (2424:2424:2424))
        (PORT datac (833:833:833) (830:830:830))
        (IOPATH dataa combout (300:300:300) (323:323:323))
        (IOPATH datab combout (306:306:306) (324:324:324))
        (IOPATH datac combout (220:220:220) (216:216:216))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1903:1903:1903) (2034:2034:2034))
        (PORT d[1] (1791:1791:1791) (1873:1873:1873))
        (PORT d[2] (1932:1932:1932) (1990:1990:1990))
        (PORT d[3] (2057:2057:2057) (2132:2132:2132))
        (PORT d[4] (2010:2010:2010) (2111:2111:2111))
        (PORT d[5] (1757:1757:1757) (1820:1820:1820))
        (PORT d[6] (1729:1729:1729) (1778:1778:1778))
        (PORT d[7] (2039:2039:2039) (2130:2130:2130))
        (PORT d[8] (1634:1634:1634) (1673:1673:1673))
        (PORT d[9] (2000:2000:2000) (2095:2095:2095))
        (PORT d[10] (1516:1516:1516) (1619:1619:1619))
        (PORT d[11] (2137:2137:2137) (2232:2232:2232))
        (PORT d[12] (1833:1833:1833) (1919:1919:1919))
        (PORT clk (1631:1631:1631) (1660:1660:1660))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1631:1631:1631) (1660:1660:1660))
        (PORT d[0] (1600:1600:1600) (1588:1588:1588))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1632:1632:1632) (1661:1661:1661))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1598:1598:1598) (1626:1626:1626))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (869:869:869) (873:873:873))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (870:870:870) (874:874:874))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (870:870:870) (874:874:874))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (870:870:870) (874:874:874))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1866:1866:1866) (2004:2004:2004))
        (PORT d[1] (1807:1807:1807) (1895:1895:1895))
        (PORT d[2] (2017:2017:2017) (2097:2097:2097))
        (PORT d[3] (2064:2064:2064) (2131:2131:2131))
        (PORT d[4] (2001:2001:2001) (2097:2097:2097))
        (PORT d[5] (1520:1520:1520) (1579:1579:1579))
        (PORT d[6] (1949:1949:1949) (2003:2003:2003))
        (PORT d[7] (1985:1985:1985) (2052:2052:2052))
        (PORT d[8] (1996:1996:1996) (2041:2041:2041))
        (PORT d[9] (2060:2060:2060) (2159:2159:2159))
        (PORT d[10] (1531:1531:1531) (1645:1645:1645))
        (PORT d[11] (2020:2020:2020) (2097:2097:2097))
        (PORT d[12] (1981:1981:1981) (2109:2109:2109))
        (PORT clk (1634:1634:1634) (1662:1662:1662))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1634:1634:1634) (1662:1662:1662))
        (PORT d[0] (1564:1564:1564) (1561:1561:1561))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1635:1635:1635) (1663:1663:1663))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1601:1601:1601) (1628:1628:1628))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (872:872:872) (875:875:875))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (873:873:873) (876:876:876))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (873:873:873) (876:876:876))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (873:873:873) (876:876:876))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1)
    (DELAY
      (ABSOLUTE
        (PORT datab (880:880:880) (884:884:884))
        (PORT datac (862:862:862) (870:870:870))
        (PORT datad (2519:2519:2519) (2641:2641:2641))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datac combout (218:218:218) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1953:1953:1953) (2093:2093:2093))
        (PORT d[1] (1570:1570:1570) (1658:1658:1658))
        (PORT d[2] (2010:2010:2010) (2081:2081:2081))
        (PORT d[3] (2096:2096:2096) (2175:2175:2175))
        (PORT d[4] (1985:1985:1985) (2057:2057:2057))
        (PORT d[5] (1791:1791:1791) (1856:1856:1856))
        (PORT d[6] (1933:1933:1933) (2007:2007:2007))
        (PORT d[7] (1908:1908:1908) (2042:2042:2042))
        (PORT d[8] (1980:1980:1980) (2044:2044:2044))
        (PORT d[9] (1982:1982:1982) (2045:2045:2045))
        (PORT d[10] (1601:1601:1601) (1716:1716:1716))
        (PORT d[11] (2128:2128:2128) (2214:2214:2214))
        (PORT d[12] (2026:2026:2026) (2164:2164:2164))
        (PORT clk (1628:1628:1628) (1658:1658:1658))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1628:1628:1628) (1658:1658:1658))
        (PORT d[0] (1623:1623:1623) (1611:1611:1611))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1629:1629:1629) (1659:1659:1659))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1595:1595:1595) (1624:1624:1624))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (866:866:866) (871:871:871))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (867:867:867) (872:872:872))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (867:867:867) (872:872:872))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (867:867:867) (872:872:872))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1895:1895:1895) (2031:2031:2031))
        (PORT d[1] (1884:1884:1884) (1967:1967:1967))
        (PORT d[2] (1831:1831:1831) (1898:1898:1898))
        (PORT d[3] (2297:2297:2297) (2368:2368:2368))
        (PORT d[4] (2030:2030:2030) (2137:2137:2137))
        (PORT d[5] (1833:1833:1833) (1886:1886:1886))
        (PORT d[6] (2031:2031:2031) (2090:2090:2090))
        (PORT d[7] (1899:1899:1899) (2032:2032:2032))
        (PORT d[8] (2167:2167:2167) (2198:2198:2198))
        (PORT d[9] (2021:2021:2021) (2119:2119:2119))
        (PORT d[10] (2138:2138:2138) (2243:2243:2243))
        (PORT d[11] (2135:2135:2135) (2198:2198:2198))
        (PORT d[12] (2072:2072:2072) (2143:2143:2143))
        (PORT clk (1645:1645:1645) (1673:1673:1673))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1673:1673:1673))
        (PORT d[0] (1744:1744:1744) (1801:1801:1801))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1674:1674:1674))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1612:1612:1612) (1639:1639:1639))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (883:883:883) (886:886:886))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (884:884:884) (887:887:887))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (884:884:884) (887:887:887))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (884:884:884) (887:887:887))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (898:898:898) (905:905:905))
        (PORT datac (2220:2220:2220) (2324:2324:2324))
        (PORT datad (329:329:329) (323:323:323))
        (IOPATH dataa combout (318:318:318) (323:323:323))
        (IOPATH datac combout (218:218:218) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1602:1602:1602) (1731:1731:1731))
        (PORT d[1] (1816:1816:1816) (1922:1922:1922))
        (PORT d[2] (2006:2006:2006) (2073:2073:2073))
        (PORT d[3] (2062:2062:2062) (2127:2127:2127))
        (PORT d[4] (1931:1931:1931) (1992:1992:1992))
        (PORT d[5] (1757:1757:1757) (1818:1818:1818))
        (PORT d[6] (1698:1698:1698) (1745:1745:1745))
        (PORT d[7] (1718:1718:1718) (1774:1774:1774))
        (PORT d[8] (1736:1736:1736) (1779:1779:1779))
        (PORT d[9] (1773:1773:1773) (1862:1862:1862))
        (PORT d[10] (1634:1634:1634) (1748:1748:1748))
        (PORT d[11] (1729:1729:1729) (1781:1781:1781))
        (PORT d[12] (1897:1897:1897) (1934:1934:1934))
        (PORT clk (1635:1635:1635) (1664:1664:1664))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1635:1635:1635) (1664:1664:1664))
        (PORT d[0] (1570:1570:1570) (1575:1575:1575))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1636:1636:1636) (1665:1665:1665))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1602:1602:1602) (1630:1630:1630))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (873:873:873) (877:877:877))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (878:878:878))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (878:878:878))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (878:878:878))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1837:1837:1837) (1958:1958:1958))
        (PORT d[1] (1794:1794:1794) (1867:1867:1867))
        (PORT d[2] (2014:2014:2014) (2091:2091:2091))
        (PORT d[3] (2055:2055:2055) (2132:2132:2132))
        (PORT d[4] (1972:1972:1972) (2034:2034:2034))
        (PORT d[5] (1740:1740:1740) (1796:1796:1796))
        (PORT d[6] (1669:1669:1669) (1735:1735:1735))
        (PORT d[7] (1768:1768:1768) (1868:1868:1868))
        (PORT d[8] (1731:1731:1731) (1791:1791:1791))
        (PORT d[9] (2027:2027:2027) (2128:2128:2128))
        (PORT d[10] (1960:1960:1960) (2059:2059:2059))
        (PORT d[11] (1721:1721:1721) (1787:1787:1787))
        (PORT d[12] (1954:1954:1954) (2083:2083:2083))
        (PORT clk (1635:1635:1635) (1662:1662:1662))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1635:1635:1635) (1662:1662:1662))
        (PORT d[0] (1602:1602:1602) (1608:1608:1608))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1636:1636:1636) (1663:1663:1663))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1602:1602:1602) (1628:1628:1628))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (873:873:873) (875:875:875))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (876:876:876))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (876:876:876))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (876:876:876))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~3)
    (DELAY
      (ABSOLUTE
        (PORT dataa (676:676:676) (691:691:691))
        (PORT datac (1755:1755:1755) (1876:1876:1876))
        (PORT datad (329:329:329) (322:322:322))
        (IOPATH dataa combout (307:307:307) (306:306:306))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2024:2024:2024) (2066:2066:2066))
        (PORT clk (1643:1643:1643) (1671:1671:1671))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1907:1907:1907) (2040:2040:2040))
        (PORT d[1] (2033:2033:2033) (2088:2088:2088))
        (PORT d[2] (2056:2056:2056) (2145:2145:2145))
        (PORT d[3] (2117:2117:2117) (2201:2201:2201))
        (PORT d[4] (2012:2012:2012) (2113:2113:2113))
        (PORT d[5] (2062:2062:2062) (2132:2132:2132))
        (PORT d[6] (1999:1999:1999) (2053:2053:2053))
        (PORT d[7] (1924:1924:1924) (2049:2049:2049))
        (PORT d[8] (2199:2199:2199) (2253:2253:2253))
        (PORT d[9] (1991:1991:1991) (2077:2077:2077))
        (PORT d[10] (1874:1874:1874) (1999:1999:1999))
        (PORT d[11] (2165:2165:2165) (2266:2266:2266))
        (PORT d[12] (2168:2168:2168) (2269:2269:2269))
        (PORT clk (1640:1640:1640) (1669:1669:1669))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1643:1643:1643) (1671:1671:1671))
        (PORT d[0] (1803:1803:1803) (1759:1759:1759))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1672:1672:1672))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1672:1672:1672))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1672:1672:1672))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1672:1672:1672))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1607:1607:1607) (1635:1635:1635))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2028:2028:2028) (2070:2070:2070))
        (PORT clk (1643:1643:1643) (1673:1673:1673))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1887:1887:1887) (2020:2020:2020))
        (PORT d[1] (2076:2076:2076) (2132:2132:2132))
        (PORT d[2] (2013:2013:2013) (2083:2083:2083))
        (PORT d[3] (2118:2118:2118) (2202:2202:2202))
        (PORT d[4] (2031:2031:2031) (2119:2119:2119))
        (PORT d[5] (2063:2063:2063) (2133:2133:2133))
        (PORT d[6] (2000:2000:2000) (2054:2054:2054))
        (PORT d[7] (1925:1925:1925) (2050:2050:2050))
        (PORT d[8] (2200:2200:2200) (2254:2254:2254))
        (PORT d[9] (1992:1992:1992) (2078:2078:2078))
        (PORT d[10] (1875:1875:1875) (2000:2000:2000))
        (PORT d[11] (2166:2166:2166) (2267:2267:2267))
        (PORT d[12] (2169:2169:2169) (2270:2270:2270))
        (PORT clk (1642:1642:1642) (1671:1671:1671))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1643:1643:1643) (1673:1673:1673))
        (PORT d[0] (1803:1803:1803) (1759:1759:1759))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1674:1674:1674))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1674:1674:1674))
        (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1674:1674:1674))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1674:1674:1674))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1608:1608:1608) (1637:1637:1637))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2933:2933:2933) (2922:2922:2922))
        (PORT clk (1649:1649:1649) (1677:1677:1677))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1815:1815:1815) (1883:1883:1883))
        (PORT d[1] (2131:2131:2131) (2240:2240:2240))
        (PORT d[2] (1805:1805:1805) (1878:1878:1878))
        (PORT d[3] (1609:1609:1609) (1704:1704:1704))
        (PORT d[4] (2018:2018:2018) (2119:2119:2119))
        (PORT d[5] (1456:1456:1456) (1543:1543:1543))
        (PORT d[6] (1653:1653:1653) (1759:1759:1759))
        (PORT d[7] (1620:1620:1620) (1717:1717:1717))
        (PORT d[8] (1802:1802:1802) (1867:1867:1867))
        (PORT d[9] (1645:1645:1645) (1680:1680:1680))
        (PORT d[10] (1560:1560:1560) (1647:1647:1647))
        (PORT d[11] (1861:1861:1861) (1918:1918:1918))
        (PORT d[12] (1917:1917:1917) (2011:2011:2011))
        (PORT clk (1646:1646:1646) (1675:1675:1675))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1649:1649:1649) (1677:1677:1677))
        (PORT d[0] (1177:1177:1177) (1205:1205:1205))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1650:1650:1650) (1678:1678:1678))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1650:1650:1650) (1678:1678:1678))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1650:1650:1650) (1678:1678:1678))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1650:1650:1650) (1678:1678:1678))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1613:1613:1613) (1641:1641:1641))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2937:2937:2937) (2926:2926:2926))
        (PORT clk (1649:1649:1649) (1679:1679:1679))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1822:1822:1822) (1882:1882:1882))
        (PORT d[1] (2132:2132:2132) (2241:2241:2241))
        (PORT d[2] (1764:1764:1764) (1838:1838:1838))
        (PORT d[3] (1610:1610:1610) (1705:1705:1705))
        (PORT d[4] (2053:2053:2053) (2170:2170:2170))
        (PORT d[5] (1457:1457:1457) (1544:1544:1544))
        (PORT d[6] (1654:1654:1654) (1760:1760:1760))
        (PORT d[7] (1621:1621:1621) (1718:1718:1718))
        (PORT d[8] (1803:1803:1803) (1868:1868:1868))
        (PORT d[9] (1646:1646:1646) (1681:1681:1681))
        (PORT d[10] (1561:1561:1561) (1648:1648:1648))
        (PORT d[11] (1862:1862:1862) (1919:1919:1919))
        (PORT d[12] (1918:1918:1918) (2012:2012:2012))
        (PORT clk (1648:1648:1648) (1677:1677:1677))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1649:1649:1649) (1679:1679:1679))
        (PORT d[0] (1177:1177:1177) (1205:1205:1205))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1650:1650:1650) (1680:1680:1680))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1650:1650:1650) (1680:1680:1680))
        (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1650:1650:1650) (1680:1680:1680))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1650:1650:1650) (1680:1680:1680))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1643:1643:1643))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[4\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (2490:2490:2490) (2600:2600:2600))
        (PORT datac (592:592:592) (588:588:588))
        (PORT datad (1013:1013:1013) (999:999:999))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2917:2917:2917) (2901:2901:2901))
        (PORT clk (1652:1652:1652) (1679:1679:1679))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1552:1552:1552) (1631:1631:1631))
        (PORT d[1] (1766:1766:1766) (1854:1854:1854))
        (PORT d[2] (1805:1805:1805) (1879:1879:1879))
        (PORT d[3] (1635:1635:1635) (1722:1722:1722))
        (PORT d[4] (1851:1851:1851) (1935:1935:1935))
        (PORT d[5] (1741:1741:1741) (1837:1837:1837))
        (PORT d[6] (1811:1811:1811) (1890:1890:1890))
        (PORT d[7] (1873:1873:1873) (1972:1972:1972))
        (PORT d[8] (1828:1828:1828) (1897:1897:1897))
        (PORT d[9] (1890:1890:1890) (1981:1981:1981))
        (PORT d[10] (1611:1611:1611) (1704:1704:1704))
        (PORT d[11] (1813:1813:1813) (1880:1880:1880))
        (PORT d[12] (1903:1903:1903) (1997:1997:1997))
        (PORT clk (1649:1649:1649) (1677:1677:1677))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1652:1652:1652) (1679:1679:1679))
        (PORT d[0] (1443:1443:1443) (1423:1423:1423))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1653:1653:1653) (1680:1680:1680))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1653:1653:1653) (1680:1680:1680))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1653:1653:1653) (1680:1680:1680))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1653:1653:1653) (1680:1680:1680))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1616:1616:1616) (1643:1643:1643))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2921:2921:2921) (2905:2905:2905))
        (PORT clk (1652:1652:1652) (1681:1681:1681))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1561:1561:1561) (1624:1624:1624))
        (PORT d[1] (1776:1776:1776) (1869:1869:1869))
        (PORT d[2] (1764:1764:1764) (1838:1838:1838))
        (PORT d[3] (1636:1636:1636) (1723:1723:1723))
        (PORT d[4] (1831:1831:1831) (1921:1921:1921))
        (PORT d[5] (1742:1742:1742) (1838:1838:1838))
        (PORT d[6] (1812:1812:1812) (1891:1891:1891))
        (PORT d[7] (1874:1874:1874) (1973:1973:1973))
        (PORT d[8] (1829:1829:1829) (1898:1898:1898))
        (PORT d[9] (1891:1891:1891) (1982:1982:1982))
        (PORT d[10] (1612:1612:1612) (1705:1705:1705))
        (PORT d[11] (1814:1814:1814) (1881:1881:1881))
        (PORT d[12] (1904:1904:1904) (1998:1998:1998))
        (PORT clk (1651:1651:1651) (1679:1679:1679))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1652:1652:1652) (1681:1681:1681))
        (PORT d[0] (1443:1443:1443) (1423:1423:1423))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1653:1653:1653) (1682:1682:1682))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1653:1653:1653) (1682:1682:1682))
        (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1653:1653:1653) (1682:1682:1682))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1653:1653:1653) (1682:1682:1682))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1617:1617:1617) (1645:1645:1645))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2942:2942:2942) (2938:2938:2938))
        (PORT clk (1646:1646:1646) (1673:1673:1673))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1570:1570:1570) (1650:1650:1650))
        (PORT d[1] (1816:1816:1816) (1894:1894:1894))
        (PORT d[2] (1527:1527:1527) (1577:1577:1577))
        (PORT d[3] (1592:1592:1592) (1687:1687:1687))
        (PORT d[4] (1794:1794:1794) (1909:1909:1909))
        (PORT d[5] (1430:1430:1430) (1514:1514:1514))
        (PORT d[6] (1895:1895:1895) (1995:1995:1995))
        (PORT d[7] (1613:1613:1613) (1714:1714:1714))
        (PORT d[8] (1789:1789:1789) (1855:1855:1855))
        (PORT d[9] (1882:1882:1882) (1971:1971:1971))
        (PORT d[10] (2027:2027:2027) (2172:2172:2172))
        (PORT d[11] (1855:1855:1855) (1905:1905:1905))
        (PORT d[12] (1895:1895:1895) (1997:1997:1997))
        (PORT clk (1643:1643:1643) (1671:1671:1671))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1673:1673:1673))
        (PORT d[0] (1177:1177:1177) (1205:1205:1205))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1674:1674:1674))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1674:1674:1674))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1674:1674:1674))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1674:1674:1674))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1610:1610:1610) (1637:1637:1637))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2946:2946:2946) (2942:2942:2942))
        (PORT clk (1646:1646:1646) (1675:1675:1675))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1550:1550:1550) (1629:1629:1629))
        (PORT d[1] (1817:1817:1817) (1896:1896:1896))
        (PORT d[2] (1541:1541:1541) (1606:1606:1606))
        (PORT d[3] (1593:1593:1593) (1688:1688:1688))
        (PORT d[4] (1801:1801:1801) (1898:1898:1898))
        (PORT d[5] (1431:1431:1431) (1515:1515:1515))
        (PORT d[6] (1896:1896:1896) (1996:1996:1996))
        (PORT d[7] (1614:1614:1614) (1715:1715:1715))
        (PORT d[8] (1790:1790:1790) (1856:1856:1856))
        (PORT d[9] (1883:1883:1883) (1972:1972:1972))
        (PORT d[10] (2028:2028:2028) (2173:2173:2173))
        (PORT d[11] (1856:1856:1856) (1906:1906:1906))
        (PORT d[12] (1896:1896:1896) (1998:1998:1998))
        (PORT clk (1645:1645:1645) (1673:1673:1673))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1675:1675:1675))
        (PORT d[0] (1177:1177:1177) (1205:1205:1205))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1676:1676:1676))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1676:1676:1676))
        (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1676:1676:1676))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1676:1676:1676))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1639:1639:1639))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[5\]\~1)
    (DELAY
      (ABSOLUTE
        (PORT datab (246:246:246) (319:319:319))
        (PORT datac (628:628:628) (634:634:634))
        (PORT datad (329:329:329) (323:323:323))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (865:865:865) (874:874:874))
        (PORT clk (1646:1646:1646) (1672:1672:1672))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1472:1472:1472) (1537:1537:1537))
        (PORT d[1] (1564:1564:1564) (1641:1641:1641))
        (PORT d[2] (1474:1474:1474) (1544:1544:1544))
        (PORT d[3] (1579:1579:1579) (1647:1647:1647))
        (PORT d[4] (1543:1543:1543) (1633:1633:1633))
        (PORT d[5] (1370:1370:1370) (1449:1449:1449))
        (PORT d[6] (1510:1510:1510) (1570:1570:1570))
        (PORT d[7] (1787:1787:1787) (1854:1854:1854))
        (PORT d[8] (1553:1553:1553) (1630:1630:1630))
        (PORT d[9] (1606:1606:1606) (1687:1687:1687))
        (PORT d[10] (1349:1349:1349) (1445:1445:1445))
        (PORT d[11] (1744:1744:1744) (1801:1801:1801))
        (PORT d[12] (1615:1615:1615) (1699:1699:1699))
        (PORT clk (1643:1643:1643) (1670:1670:1670))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1672:1672:1672))
        (PORT d[0] (1167:1167:1167) (1141:1141:1141))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1610:1610:1610) (1636:1636:1636))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (869:869:869) (878:878:878))
        (PORT clk (1646:1646:1646) (1674:1674:1674))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1494:1494:1494) (1558:1558:1558))
        (PORT d[1] (1551:1551:1551) (1613:1613:1613))
        (PORT d[2] (1486:1486:1486) (1547:1547:1547))
        (PORT d[3] (1580:1580:1580) (1648:1648:1648))
        (PORT d[4] (1545:1545:1545) (1635:1635:1635))
        (PORT d[5] (1371:1371:1371) (1450:1450:1450))
        (PORT d[6] (1511:1511:1511) (1571:1571:1571))
        (PORT d[7] (1788:1788:1788) (1855:1855:1855))
        (PORT d[8] (1554:1554:1554) (1631:1631:1631))
        (PORT d[9] (1607:1607:1607) (1688:1688:1688))
        (PORT d[10] (1350:1350:1350) (1446:1446:1446))
        (PORT d[11] (1745:1745:1745) (1802:1802:1802))
        (PORT d[12] (1616:1616:1616) (1700:1700:1700))
        (PORT clk (1645:1645:1645) (1672:1672:1672))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1674:1674:1674))
        (PORT d[0] (1167:1167:1167) (1141:1141:1141))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1675:1675:1675))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1675:1675:1675))
        (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1675:1675:1675))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1675:1675:1675))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1638:1638:1638))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (840:840:840) (855:855:855))
        (PORT clk (1646:1646:1646) (1672:1672:1672))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1801:1801:1801) (1896:1896:1896))
        (PORT d[1] (1570:1570:1570) (1656:1656:1656))
        (PORT d[2] (1748:1748:1748) (1810:1810:1810))
        (PORT d[3] (1571:1571:1571) (1637:1637:1637))
        (PORT d[4] (1553:1553:1553) (1645:1645:1645))
        (PORT d[5] (1374:1374:1374) (1452:1452:1452))
        (PORT d[6] (1738:1738:1738) (1790:1790:1790))
        (PORT d[7] (1554:1554:1554) (1641:1641:1641))
        (PORT d[8] (1586:1586:1586) (1668:1668:1668))
        (PORT d[9] (1591:1591:1591) (1672:1672:1672))
        (PORT d[10] (1611:1611:1611) (1699:1699:1699))
        (PORT d[11] (1737:1737:1737) (1788:1788:1788))
        (PORT d[12] (1626:1626:1626) (1712:1712:1712))
        (PORT clk (1643:1643:1643) (1670:1670:1670))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1672:1672:1672))
        (PORT d[0] (1129:1129:1129) (1156:1156:1156))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1610:1610:1610) (1636:1636:1636))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (844:844:844) (859:859:859))
        (PORT clk (1646:1646:1646) (1674:1674:1674))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1802:1802:1802) (1897:1897:1897))
        (PORT d[1] (1550:1550:1550) (1635:1635:1635))
        (PORT d[2] (1491:1491:1491) (1553:1553:1553))
        (PORT d[3] (1572:1572:1572) (1638:1638:1638))
        (PORT d[4] (1541:1541:1541) (1617:1617:1617))
        (PORT d[5] (1375:1375:1375) (1453:1453:1453))
        (PORT d[6] (1739:1739:1739) (1791:1791:1791))
        (PORT d[7] (1555:1555:1555) (1642:1642:1642))
        (PORT d[8] (1587:1587:1587) (1669:1669:1669))
        (PORT d[9] (1592:1592:1592) (1673:1673:1673))
        (PORT d[10] (1612:1612:1612) (1700:1700:1700))
        (PORT d[11] (1738:1738:1738) (1789:1789:1789))
        (PORT d[12] (1627:1627:1627) (1713:1713:1713))
        (PORT clk (1645:1645:1645) (1672:1672:1672))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1674:1674:1674))
        (PORT d[0] (1129:1129:1129) (1156:1156:1156))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1675:1675:1675))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1675:1675:1675))
        (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1675:1675:1675))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1675:1675:1675))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1638:1638:1638))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[6\]\~2)
    (DELAY
      (ABSOLUTE
        (PORT datab (923:923:923) (934:934:934))
        (PORT datac (679:679:679) (740:740:740))
        (PORT datad (897:897:897) (894:894:894))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datac combout (218:218:218) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (3190:3190:3190) (3193:3193:3193))
        (PORT clk (1639:1639:1639) (1667:1667:1667))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1551:1551:1551) (1637:1637:1637))
        (PORT d[1] (1802:1802:1802) (1873:1873:1873))
        (PORT d[2] (1508:1508:1508) (1576:1576:1576))
        (PORT d[3] (1554:1554:1554) (1642:1642:1642))
        (PORT d[4] (1809:1809:1809) (1905:1905:1905))
        (PORT d[5] (1408:1408:1408) (1478:1478:1478))
        (PORT d[6] (1930:1930:1930) (2041:2041:2041))
        (PORT d[7] (1820:1820:1820) (1911:1911:1911))
        (PORT d[8] (1845:1845:1845) (1930:1930:1930))
        (PORT d[9] (1903:1903:1903) (2003:2003:2003))
        (PORT d[10] (1826:1826:1826) (1902:1902:1902))
        (PORT d[11] (1612:1612:1612) (1657:1657:1657))
        (PORT d[12] (1650:1650:1650) (1745:1745:1745))
        (PORT clk (1636:1636:1636) (1665:1665:1665))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1667:1667:1667))
        (PORT d[0] (1154:1154:1154) (1144:1144:1144))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1640:1640:1640) (1668:1668:1668))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1640:1640:1640) (1668:1668:1668))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1640:1640:1640) (1668:1668:1668))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1640:1640:1640) (1668:1668:1668))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1603:1603:1603) (1631:1631:1631))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (3194:3194:3194) (3197:3197:3197))
        (PORT clk (1639:1639:1639) (1669:1669:1669))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1561:1561:1561) (1631:1631:1631))
        (PORT d[1] (1782:1782:1782) (1852:1852:1852))
        (PORT d[2] (1549:1549:1549) (1615:1615:1615))
        (PORT d[3] (1555:1555:1555) (1643:1643:1643))
        (PORT d[4] (1797:1797:1797) (1877:1877:1877))
        (PORT d[5] (1409:1409:1409) (1479:1479:1479))
        (PORT d[6] (1931:1931:1931) (2042:2042:2042))
        (PORT d[7] (1821:1821:1821) (1912:1912:1912))
        (PORT d[8] (1846:1846:1846) (1931:1931:1931))
        (PORT d[9] (1904:1904:1904) (2004:2004:2004))
        (PORT d[10] (1827:1827:1827) (1903:1903:1903))
        (PORT d[11] (1613:1613:1613) (1658:1658:1658))
        (PORT d[12] (1651:1651:1651) (1746:1746:1746))
        (PORT clk (1638:1638:1638) (1667:1667:1667))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1669:1669:1669))
        (PORT d[0] (1154:1154:1154) (1144:1144:1144))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1640:1640:1640) (1670:1670:1670))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1640:1640:1640) (1670:1670:1670))
        (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1640:1640:1640) (1670:1670:1670))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1640:1640:1640) (1670:1670:1670))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1604:1604:1604) (1633:1633:1633))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (3173:3173:3173) (3171:3171:3171))
        (PORT clk (1639:1639:1639) (1665:1665:1665))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1779:1779:1779) (1860:1860:1860))
        (PORT d[1] (1739:1739:1739) (1832:1832:1832))
        (PORT d[2] (1547:1547:1547) (1613:1613:1613))
        (PORT d[3] (1588:1588:1588) (1675:1675:1675))
        (PORT d[4] (1857:1857:1857) (1949:1949:1949))
        (PORT d[5] (1419:1419:1419) (1493:1493:1493))
        (PORT d[6] (1933:1933:1933) (2046:2046:2046))
        (PORT d[7] (1586:1586:1586) (1682:1682:1682))
        (PORT d[8] (1501:1501:1501) (1560:1560:1560))
        (PORT d[9] (1885:1885:1885) (1979:1979:1979))
        (PORT d[10] (1609:1609:1609) (1694:1694:1694))
        (PORT d[11] (1837:1837:1837) (1907:1907:1907))
        (PORT d[12] (1895:1895:1895) (1975:1975:1975))
        (PORT clk (1636:1636:1636) (1663:1663:1663))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1665:1665:1665))
        (PORT d[0] (1183:1183:1183) (1199:1199:1199))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1640:1640:1640) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1640:1640:1640) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1640:1640:1640) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1640:1640:1640) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1603:1603:1603) (1629:1629:1629))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (3177:3177:3177) (3175:3175:3175))
        (PORT clk (1639:1639:1639) (1667:1667:1667))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1824:1824:1824) (1898:1898:1898))
        (PORT d[1] (1806:1806:1806) (1887:1887:1887))
        (PORT d[2] (1548:1548:1548) (1614:1614:1614))
        (PORT d[3] (1589:1589:1589) (1676:1676:1676))
        (PORT d[4] (1858:1858:1858) (1950:1950:1950))
        (PORT d[5] (1420:1420:1420) (1494:1494:1494))
        (PORT d[6] (1934:1934:1934) (2047:2047:2047))
        (PORT d[7] (1587:1587:1587) (1683:1683:1683))
        (PORT d[8] (1502:1502:1502) (1561:1561:1561))
        (PORT d[9] (1886:1886:1886) (1980:1980:1980))
        (PORT d[10] (1610:1610:1610) (1695:1695:1695))
        (PORT d[11] (1838:1838:1838) (1908:1908:1908))
        (PORT d[12] (1896:1896:1896) (1976:1976:1976))
        (PORT clk (1638:1638:1638) (1665:1665:1665))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1667:1667:1667))
        (PORT d[0] (1183:1183:1183) (1199:1199:1199))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1640:1640:1640) (1668:1668:1668))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1640:1640:1640) (1668:1668:1668))
        (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1640:1640:1640) (1668:1668:1668))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1640:1640:1640) (1668:1668:1668))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1604:1604:1604) (1631:1631:1631))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[7\]\~3)
    (DELAY
      (ABSOLUTE
        (PORT datab (708:708:708) (769:769:769))
        (PORT datac (624:624:624) (614:614:614))
        (PORT datad (330:330:330) (324:324:324))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1626:1626:1626) (1760:1760:1760))
        (PORT d[1] (1783:1783:1783) (1854:1854:1854))
        (PORT d[2] (1969:1969:1969) (2036:2036:2036))
        (PORT d[3] (2048:2048:2048) (2096:2096:2096))
        (PORT d[4] (1982:1982:1982) (2064:2064:2064))
        (PORT d[5] (1784:1784:1784) (1853:1853:1853))
        (PORT d[6] (1651:1651:1651) (1696:1696:1696))
        (PORT d[7] (1739:1739:1739) (1813:1813:1813))
        (PORT d[8] (1750:1750:1750) (1811:1811:1811))
        (PORT d[9] (1758:1758:1758) (1850:1850:1850))
        (PORT d[10] (1620:1620:1620) (1745:1745:1745))
        (PORT d[11] (1714:1714:1714) (1779:1779:1779))
        (PORT d[12] (2036:2036:2036) (2161:2161:2161))
        (PORT clk (1635:1635:1635) (1663:1663:1663))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1635:1635:1635) (1663:1663:1663))
        (PORT d[0] (1581:1581:1581) (1574:1574:1574))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1636:1636:1636) (1664:1664:1664))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1602:1602:1602) (1629:1629:1629))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (873:873:873) (876:876:876))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (877:877:877))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (877:877:877))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (877:877:877))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1944:1944:1944) (2072:2072:2072))
        (PORT d[1] (1807:1807:1807) (1884:1884:1884))
        (PORT d[2] (2016:2016:2016) (2089:2089:2089))
        (PORT d[3] (2086:2086:2086) (2163:2163:2163))
        (PORT d[4] (2022:2022:2022) (2116:2116:2116))
        (PORT d[5] (1816:1816:1816) (1892:1892:1892))
        (PORT d[6] (1968:1968:1968) (2013:2013:2013))
        (PORT d[7] (1903:1903:1903) (2035:2035:2035))
        (PORT d[8] (1907:1907:1907) (1957:1957:1957))
        (PORT d[9] (2005:2005:2005) (2088:2088:2088))
        (PORT d[10] (1828:1828:1828) (1940:1940:1940))
        (PORT d[11] (2103:2103:2103) (2185:2185:2185))
        (PORT d[12] (1886:1886:1886) (1965:1965:1965))
        (PORT clk (1632:1632:1632) (1660:1660:1660))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1632:1632:1632) (1660:1660:1660))
        (PORT d[0] (1587:1587:1587) (1594:1594:1594))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1633:1633:1633) (1661:1661:1661))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1599:1599:1599) (1626:1626:1626))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (870:870:870) (873:873:873))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (871:871:871) (874:874:874))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (871:871:871) (874:874:874))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (871:871:871) (874:874:874))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1086:1086:1086) (1089:1089:1089))
        (PORT datac (2311:2311:2311) (2442:2442:2442))
        (PORT datad (327:327:327) (320:320:320))
        (IOPATH dataa combout (318:318:318) (323:323:323))
        (IOPATH datac combout (218:218:218) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1893:1893:1893) (2038:2038:2038))
        (PORT d[1] (1845:1845:1845) (1924:1924:1924))
        (PORT d[2] (1979:1979:1979) (2052:2052:2052))
        (PORT d[3] (2031:2031:2031) (2090:2090:2090))
        (PORT d[4] (2013:2013:2013) (2095:2095:2095))
        (PORT d[5] (1790:1790:1790) (1864:1864:1864))
        (PORT d[6] (2001:2001:2001) (2035:2035:2035))
        (PORT d[7] (1928:1928:1928) (2062:2062:2062))
        (PORT d[8] (1681:1681:1681) (1739:1739:1739))
        (PORT d[9] (2006:2006:2006) (2093:2093:2093))
        (PORT d[10] (1586:1586:1586) (1705:1705:1705))
        (PORT d[11] (2118:2118:2118) (2204:2204:2204))
        (PORT d[12] (1873:1873:1873) (1958:1958:1958))
        (PORT clk (1628:1628:1628) (1655:1655:1655))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1628:1628:1628) (1655:1655:1655))
        (PORT d[0] (1579:1579:1579) (1579:1579:1579))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1629:1629:1629) (1656:1656:1656))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1595:1595:1595) (1621:1621:1621))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (866:866:866) (868:868:868))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (867:867:867) (869:869:869))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (867:867:867) (869:869:869))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (867:867:867) (869:869:869))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1888:1888:1888) (2021:2021:2021))
        (PORT d[1] (1603:1603:1603) (1686:1686:1686))
        (PORT d[2] (2038:2038:2038) (2119:2119:2119))
        (PORT d[3] (2058:2058:2058) (2137:2137:2137))
        (PORT d[4] (2005:2005:2005) (2088:2088:2088))
        (PORT d[5] (1532:1532:1532) (1591:1591:1591))
        (PORT d[6] (1930:1930:1930) (2000:2000:2000))
        (PORT d[7] (1802:1802:1802) (1899:1899:1899))
        (PORT d[8] (1663:1663:1663) (1710:1710:1710))
        (PORT d[9] (2040:2040:2040) (2138:2138:2138))
        (PORT d[10] (1567:1567:1567) (1688:1688:1688))
        (PORT d[11] (2009:2009:2009) (2081:2081:2081))
        (PORT d[12] (1990:1990:1990) (2129:2129:2129))
        (PORT clk (1633:1633:1633) (1661:1661:1661))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1633:1633:1633) (1661:1661:1661))
        (PORT d[0] (1579:1579:1579) (1579:1579:1579))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1634:1634:1634) (1662:1662:1662))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1600:1600:1600) (1627:1627:1627))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (871:871:871) (874:874:874))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (872:872:872) (875:875:875))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (872:872:872) (875:875:875))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (872:872:872) (875:875:875))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~5)
    (DELAY
      (ABSOLUTE
        (PORT dataa (648:648:648) (646:646:646))
        (PORT datac (866:866:866) (870:870:870))
        (PORT datad (2488:2488:2488) (2608:2608:2608))
        (IOPATH dataa combout (273:273:273) (269:269:269))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1809:1809:1809) (1908:1908:1908))
        (PORT d[1] (1513:1513:1513) (1564:1564:1564))
        (PORT d[2] (1741:1741:1741) (1796:1796:1796))
        (PORT d[3] (1755:1755:1755) (1805:1805:1805))
        (PORT d[4] (1675:1675:1675) (1746:1746:1746))
        (PORT d[5] (1550:1550:1550) (1612:1612:1612))
        (PORT d[6] (1740:1740:1740) (1788:1788:1788))
        (PORT d[7] (1452:1452:1452) (1507:1507:1507))
        (PORT d[8] (1471:1471:1471) (1518:1518:1518))
        (PORT d[9] (1437:1437:1437) (1507:1507:1507))
        (PORT d[10] (1640:1640:1640) (1762:1762:1762))
        (PORT d[11] (1496:1496:1496) (1539:1539:1539))
        (PORT d[12] (1648:1648:1648) (1698:1698:1698))
        (PORT clk (1635:1635:1635) (1664:1664:1664))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1635:1635:1635) (1664:1664:1664))
        (PORT d[0] (1552:1552:1552) (1562:1562:1562))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1636:1636:1636) (1665:1665:1665))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1602:1602:1602) (1630:1630:1630))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (873:873:873) (877:877:877))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (878:878:878))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (878:878:878))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (878:878:878))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1568:1568:1568) (1668:1668:1668))
        (PORT d[1] (1510:1510:1510) (1559:1559:1559))
        (PORT d[2] (1702:1702:1702) (1746:1746:1746))
        (PORT d[3] (1672:1672:1672) (1689:1689:1689))
        (PORT d[4] (1662:1662:1662) (1717:1717:1717))
        (PORT d[5] (1491:1491:1491) (1548:1548:1548))
        (PORT d[6] (1422:1422:1422) (1461:1461:1461))
        (PORT d[7] (1422:1422:1422) (1494:1494:1494))
        (PORT d[8] (1453:1453:1453) (1487:1487:1487))
        (PORT d[9] (1404:1404:1404) (1458:1458:1458))
        (PORT d[10] (1652:1652:1652) (1786:1786:1786))
        (PORT d[11] (1447:1447:1447) (1481:1481:1481))
        (PORT d[12] (1637:1637:1637) (1661:1661:1661))
        (PORT clk (1633:1633:1633) (1660:1660:1660))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1633:1633:1633) (1660:1660:1660))
        (PORT d[0] (1512:1512:1512) (1483:1483:1483))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1634:1634:1634) (1661:1661:1661))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1600:1600:1600) (1626:1626:1626))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (871:871:871) (873:873:873))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (872:872:872) (874:874:874))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (872:872:872) (874:874:874))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (872:872:872) (874:874:874))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (676:676:676) (688:688:688))
        (PORT datac (1719:1719:1719) (1841:1841:1841))
        (PORT datad (884:884:884) (886:886:886))
        (IOPATH dataa combout (318:318:318) (323:323:323))
        (IOPATH datac combout (218:218:218) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1880:1880:1880) (2006:2006:2006))
        (PORT d[1] (1828:1828:1828) (1902:1902:1902))
        (PORT d[2] (2053:2053:2053) (2134:2134:2134))
        (PORT d[3] (2079:2079:2079) (2168:2168:2168))
        (PORT d[4] (2023:2023:2023) (2125:2125:2125))
        (PORT d[5] (2057:2057:2057) (2126:2126:2126))
        (PORT d[6] (2013:2013:2013) (2069:2069:2069))
        (PORT d[7] (1942:1942:1942) (2060:2060:2060))
        (PORT d[8] (2167:2167:2167) (2227:2227:2227))
        (PORT d[9] (1746:1746:1746) (1831:1831:1831))
        (PORT d[10] (1878:1878:1878) (1994:1994:1994))
        (PORT d[11] (2115:2115:2115) (2196:2196:2196))
        (PORT d[12] (2151:2151:2151) (2254:2254:2254))
        (PORT clk (1638:1638:1638) (1667:1667:1667))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1638:1638:1638) (1667:1667:1667))
        (PORT d[0] (1617:1617:1617) (1612:1612:1612))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1668:1668:1668))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1605:1605:1605) (1633:1633:1633))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (876:876:876) (880:880:880))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (877:877:877) (881:881:881))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (877:877:877) (881:881:881))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (877:877:877) (881:881:881))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1886:1886:1886) (2013:2013:2013))
        (PORT d[1] (2054:2054:2054) (2118:2118:2118))
        (PORT d[2] (2118:2118:2118) (2216:2216:2216))
        (PORT d[3] (2074:2074:2074) (2156:2156:2156))
        (PORT d[4] (2031:2031:2031) (2119:2119:2119))
        (PORT d[5] (2018:2018:2018) (2074:2074:2074))
        (PORT d[6] (1803:1803:1803) (1897:1897:1897))
        (PORT d[7] (1899:1899:1899) (2031:2031:2031))
        (PORT d[8] (1896:1896:1896) (1946:1946:1946))
        (PORT d[9] (1994:1994:1994) (2090:2090:2090))
        (PORT d[10] (1861:1861:1861) (1978:1978:1978))
        (PORT d[11] (2159:2159:2159) (2236:2236:2236))
        (PORT d[12] (2096:2096:2096) (2186:2186:2186))
        (PORT clk (1644:1644:1644) (1672:1672:1672))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1672:1672:1672))
        (PORT d[0] (1757:1757:1757) (1801:1801:1801))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1638:1638:1638))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (882:882:882) (885:885:885))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (883:883:883) (886:886:886))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (883:883:883) (886:886:886))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (883:883:883) (886:886:886))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~7)
    (DELAY
      (ABSOLUTE
        (PORT datab (2541:2541:2541) (2671:2671:2671))
        (PORT datac (519:519:519) (497:497:497))
        (PORT datad (599:599:599) (600:600:600))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (3214:3214:3214) (3222:3222:3222))
        (PORT clk (1642:1642:1642) (1669:1669:1669))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1852:1852:1852) (1928:1928:1928))
        (PORT d[1] (1600:1600:1600) (1676:1676:1676))
        (PORT d[2] (1605:1605:1605) (1646:1646:1646))
        (PORT d[3] (1599:1599:1599) (1679:1679:1679))
        (PORT d[4] (1809:1809:1809) (1905:1905:1905))
        (PORT d[5] (1362:1362:1362) (1421:1421:1421))
        (PORT d[6] (1588:1588:1588) (1675:1675:1675))
        (PORT d[7] (2070:2070:2070) (2138:2138:2138))
        (PORT d[8] (1820:1820:1820) (1904:1904:1904))
        (PORT d[9] (1648:1648:1648) (1681:1681:1681))
        (PORT d[10] (1332:1332:1332) (1436:1436:1436))
        (PORT d[11] (1997:1997:1997) (2058:2058:2058))
        (PORT d[12] (1619:1619:1619) (1692:1692:1692))
        (PORT clk (1639:1639:1639) (1667:1667:1667))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1642:1642:1642) (1669:1669:1669))
        (PORT d[0] (1177:1177:1177) (1142:1142:1142))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1643:1643:1643) (1670:1670:1670))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1643:1643:1643) (1670:1670:1670))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1643:1643:1643) (1670:1670:1670))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1643:1643:1643) (1670:1670:1670))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1606:1606:1606) (1633:1633:1633))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (3218:3218:3218) (3226:3226:3226))
        (PORT clk (1642:1642:1642) (1671:1671:1671))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1866:1866:1866) (1952:1952:1952))
        (PORT d[1] (1580:1580:1580) (1656:1656:1656))
        (PORT d[2] (1628:1628:1628) (1665:1665:1665))
        (PORT d[3] (1600:1600:1600) (1680:1680:1680))
        (PORT d[4] (1797:1797:1797) (1877:1877:1877))
        (PORT d[5] (1363:1363:1363) (1422:1422:1422))
        (PORT d[6] (1589:1589:1589) (1676:1676:1676))
        (PORT d[7] (2071:2071:2071) (2139:2139:2139))
        (PORT d[8] (1821:1821:1821) (1905:1905:1905))
        (PORT d[9] (1649:1649:1649) (1682:1682:1682))
        (PORT d[10] (1333:1333:1333) (1437:1437:1437))
        (PORT d[11] (1998:1998:1998) (2059:2059:2059))
        (PORT d[12] (1620:1620:1620) (1693:1693:1693))
        (PORT clk (1641:1641:1641) (1669:1669:1669))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1642:1642:1642) (1671:1671:1671))
        (PORT d[0] (1177:1177:1177) (1142:1142:1142))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1643:1643:1643) (1672:1672:1672))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1643:1643:1643) (1672:1672:1672))
        (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1643:1643:1643) (1672:1672:1672))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1643:1643:1643) (1672:1672:1672))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1607:1607:1607) (1635:1635:1635))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (3215:3215:3215) (3223:3223:3223))
        (PORT clk (1644:1644:1644) (1671:1671:1671))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1776:1776:1776) (1867:1867:1867))
        (PORT d[1] (1829:1829:1829) (1901:1901:1901))
        (PORT d[2] (1758:1758:1758) (1837:1837:1837))
        (PORT d[3] (1648:1648:1648) (1743:1743:1743))
        (PORT d[4] (1800:1800:1800) (1893:1893:1893))
        (PORT d[5] (1360:1360:1360) (1442:1442:1442))
        (PORT d[6] (1898:1898:1898) (1971:1971:1971))
        (PORT d[7] (1609:1609:1609) (1702:1702:1702))
        (PORT d[8] (1513:1513:1513) (1575:1575:1575))
        (PORT d[9] (1870:1870:1870) (1963:1963:1963))
        (PORT d[10] (1828:1828:1828) (1908:1908:1908))
        (PORT d[11] (2022:2022:2022) (2084:2084:2084))
        (PORT d[12] (1617:1617:1617) (1713:1713:1713))
        (PORT clk (1641:1641:1641) (1669:1669:1669))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1671:1671:1671))
        (PORT d[0] (1142:1142:1142) (1176:1176:1176))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1672:1672:1672))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1672:1672:1672))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1672:1672:1672))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1672:1672:1672))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1608:1608:1608) (1635:1635:1635))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (3219:3219:3219) (3227:3227:3227))
        (PORT clk (1644:1644:1644) (1673:1673:1673))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1818:1818:1818) (1905:1905:1905))
        (PORT d[1] (1837:1837:1837) (1900:1900:1900))
        (PORT d[2] (1794:1794:1794) (1859:1859:1859))
        (PORT d[3] (1649:1649:1649) (1744:1744:1744))
        (PORT d[4] (1802:1802:1802) (1896:1896:1896))
        (PORT d[5] (1361:1361:1361) (1443:1443:1443))
        (PORT d[6] (1899:1899:1899) (1972:1972:1972))
        (PORT d[7] (1610:1610:1610) (1703:1703:1703))
        (PORT d[8] (1514:1514:1514) (1576:1576:1576))
        (PORT d[9] (1871:1871:1871) (1964:1964:1964))
        (PORT d[10] (1829:1829:1829) (1909:1909:1909))
        (PORT d[11] (2023:2023:2023) (2085:2085:2085))
        (PORT d[12] (1618:1618:1618) (1714:1714:1714))
        (PORT clk (1643:1643:1643) (1671:1671:1671))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1673:1673:1673))
        (PORT d[0] (1142:1142:1142) (1176:1176:1176))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1674:1674:1674))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1674:1674:1674))
        (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1674:1674:1674))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1674:1674:1674))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1609:1609:1609) (1637:1637:1637))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[0\]\~4)
    (DELAY
      (ABSOLUTE
        (PORT datab (244:244:244) (318:318:318))
        (PORT datac (608:608:608) (615:615:615))
        (PORT datad (891:891:891) (886:886:886))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2588:2588:2588) (2564:2564:2564))
        (PORT clk (1655:1655:1655) (1682:1682:1682))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1831:1831:1831) (1908:1908:1908))
        (PORT d[1] (1783:1783:1783) (1877:1877:1877))
        (PORT d[2] (1808:1808:1808) (1871:1871:1871))
        (PORT d[3] (1607:1607:1607) (1704:1704:1704))
        (PORT d[4] (2013:2013:2013) (2095:2095:2095))
        (PORT d[5] (1706:1706:1706) (1798:1798:1798))
        (PORT d[6] (1895:1895:1895) (2001:2001:2001))
        (PORT d[7] (1885:1885:1885) (1979:1979:1979))
        (PORT d[8] (1770:1770:1770) (1821:1821:1821))
        (PORT d[9] (1875:1875:1875) (1975:1975:1975))
        (PORT d[10] (2011:2011:2011) (2161:2161:2161))
        (PORT d[11] (1864:1864:1864) (1935:1935:1935))
        (PORT d[12] (1922:1922:1922) (2022:2022:2022))
        (PORT clk (1652:1652:1652) (1680:1680:1680))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1655:1655:1655) (1682:1682:1682))
        (PORT d[0] (1402:1402:1402) (1421:1421:1421))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1656:1656:1656) (1683:1683:1683))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1656:1656:1656) (1683:1683:1683))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1656:1656:1656) (1683:1683:1683))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1656:1656:1656) (1683:1683:1683))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1619:1619:1619) (1646:1646:1646))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2592:2592:2592) (2568:2568:2568))
        (PORT clk (1655:1655:1655) (1684:1684:1684))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1833:1833:1833) (1915:1915:1915))
        (PORT d[1] (1804:1804:1804) (1899:1899:1899))
        (PORT d[2] (1809:1809:1809) (1872:1872:1872))
        (PORT d[3] (1608:1608:1608) (1705:1705:1705))
        (PORT d[4] (2056:2056:2056) (2137:2137:2137))
        (PORT d[5] (1707:1707:1707) (1799:1799:1799))
        (PORT d[6] (1896:1896:1896) (2002:2002:2002))
        (PORT d[7] (1886:1886:1886) (1980:1980:1980))
        (PORT d[8] (1771:1771:1771) (1822:1822:1822))
        (PORT d[9] (1876:1876:1876) (1976:1976:1976))
        (PORT d[10] (2012:2012:2012) (2162:2162:2162))
        (PORT d[11] (1865:1865:1865) (1936:1936:1936))
        (PORT d[12] (1923:1923:1923) (2023:2023:2023))
        (PORT clk (1654:1654:1654) (1682:1682:1682))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1655:1655:1655) (1684:1684:1684))
        (PORT d[0] (1402:1402:1402) (1421:1421:1421))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1656:1656:1656) (1685:1685:1685))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1656:1656:1656) (1685:1685:1685))
        (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1656:1656:1656) (1685:1685:1685))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1656:1656:1656) (1685:1685:1685))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1620:1620:1620) (1648:1648:1648))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2578:2578:2578) (2553:2553:2553))
        (PORT clk (1656:1656:1656) (1683:1683:1683))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1802:1802:1802) (1856:1856:1856))
        (PORT d[1] (1798:1798:1798) (1899:1899:1899))
        (PORT d[2] (1858:1858:1858) (1885:1885:1885))
        (PORT d[3] (1630:1630:1630) (1727:1727:1727))
        (PORT d[4] (2012:2012:2012) (2112:2112:2112))
        (PORT d[5] (1616:1616:1616) (1694:1694:1694))
        (PORT d[6] (1863:1863:1863) (1938:1938:1938))
        (PORT d[7] (1884:1884:1884) (1983:1983:1983))
        (PORT d[8] (2108:2108:2108) (2174:2174:2174))
        (PORT d[9] (1901:1901:1901) (1995:1995:1995))
        (PORT d[10] (1545:1545:1545) (1626:1626:1626))
        (PORT d[11] (1843:1843:1843) (1914:1914:1914))
        (PORT d[12] (1939:1939:1939) (2044:2044:2044))
        (PORT clk (1653:1653:1653) (1681:1681:1681))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1656:1656:1656) (1683:1683:1683))
        (PORT d[0] (1418:1418:1418) (1410:1410:1410))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1657:1657:1657) (1684:1684:1684))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1657:1657:1657) (1684:1684:1684))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1657:1657:1657) (1684:1684:1684))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1657:1657:1657) (1684:1684:1684))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1620:1620:1620) (1647:1647:1647))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2582:2582:2582) (2557:2557:2557))
        (PORT clk (1656:1656:1656) (1685:1685:1685))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1816:1816:1816) (1885:1885:1885))
        (PORT d[1] (1779:1779:1779) (1879:1879:1879))
        (PORT d[2] (2152:2152:2152) (2153:2153:2153))
        (PORT d[3] (1631:1631:1631) (1728:1728:1728))
        (PORT d[4] (1814:1814:1814) (1913:1913:1913))
        (PORT d[5] (1617:1617:1617) (1695:1695:1695))
        (PORT d[6] (1864:1864:1864) (1939:1939:1939))
        (PORT d[7] (1885:1885:1885) (1984:1984:1984))
        (PORT d[8] (2109:2109:2109) (2175:2175:2175))
        (PORT d[9] (1902:1902:1902) (1996:1996:1996))
        (PORT d[10] (1546:1546:1546) (1627:1627:1627))
        (PORT d[11] (1844:1844:1844) (1915:1915:1915))
        (PORT d[12] (1940:1940:1940) (2045:2045:2045))
        (PORT clk (1655:1655:1655) (1683:1683:1683))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1656:1656:1656) (1685:1685:1685))
        (PORT d[0] (1418:1418:1418) (1410:1410:1410))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1657:1657:1657) (1686:1686:1686))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1657:1657:1657) (1686:1686:1686))
        (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1657:1657:1657) (1686:1686:1686))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1657:1657:1657) (1686:1686:1686))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1621:1621:1621) (1649:1649:1649))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[1\]\~5)
    (DELAY
      (ABSOLUTE
        (PORT datab (592:592:592) (577:577:577))
        (PORT datac (912:912:912) (984:984:984))
        (PORT datad (836:836:836) (801:801:801))
        (IOPATH datab combout (308:308:308) (300:300:300))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1976:1976:1976) (1978:1978:1978))
        (PORT clk (1649:1649:1649) (1676:1676:1676))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1927:1927:1927) (2057:2057:2057))
        (PORT d[1] (1848:1848:1848) (1935:1935:1935))
        (PORT d[2] (1742:1742:1742) (1794:1794:1794))
        (PORT d[3] (2299:2299:2299) (2356:2356:2356))
        (PORT d[4] (2323:2323:2323) (2419:2419:2419))
        (PORT d[5] (2012:2012:2012) (2052:2052:2052))
        (PORT d[6] (2084:2084:2084) (2172:2172:2172))
        (PORT d[7] (2042:2042:2042) (2129:2129:2129))
        (PORT d[8] (2074:2074:2074) (2160:2160:2160))
        (PORT d[9] (2067:2067:2067) (2132:2132:2132))
        (PORT d[10] (1880:1880:1880) (1983:1983:1983))
        (PORT d[11] (2124:2124:2124) (2205:2205:2205))
        (PORT d[12] (2072:2072:2072) (2153:2153:2153))
        (PORT clk (1646:1646:1646) (1674:1674:1674))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1649:1649:1649) (1676:1676:1676))
        (PORT d[0] (1746:1746:1746) (1806:1806:1806))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1650:1650:1650) (1677:1677:1677))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1650:1650:1650) (1677:1677:1677))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1650:1650:1650) (1677:1677:1677))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1650:1650:1650) (1677:1677:1677))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1613:1613:1613) (1640:1640:1640))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1980:1980:1980) (1982:1982:1982))
        (PORT clk (1649:1649:1649) (1678:1678:1678))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1920:1920:1920) (2060:2060:2060))
        (PORT d[1] (1870:1870:1870) (1958:1958:1958))
        (PORT d[2] (1737:1737:1737) (1806:1806:1806))
        (PORT d[3] (2300:2300:2300) (2357:2357:2357))
        (PORT d[4] (2178:2178:2178) (2246:2246:2246))
        (PORT d[5] (2013:2013:2013) (2053:2053:2053))
        (PORT d[6] (2085:2085:2085) (2173:2173:2173))
        (PORT d[7] (2043:2043:2043) (2130:2130:2130))
        (PORT d[8] (2075:2075:2075) (2161:2161:2161))
        (PORT d[9] (2068:2068:2068) (2133:2133:2133))
        (PORT d[10] (1881:1881:1881) (1984:1984:1984))
        (PORT d[11] (2125:2125:2125) (2206:2206:2206))
        (PORT d[12] (2073:2073:2073) (2154:2154:2154))
        (PORT clk (1648:1648:1648) (1676:1676:1676))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1649:1649:1649) (1678:1678:1678))
        (PORT d[0] (1746:1746:1746) (1806:1806:1806))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1650:1650:1650) (1679:1679:1679))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1650:1650:1650) (1679:1679:1679))
        (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1650:1650:1650) (1679:1679:1679))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1650:1650:1650) (1679:1679:1679))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1642:1642:1642))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2943:2943:2943) (2939:2939:2939))
        (PORT clk (1643:1643:1643) (1670:1670:1670))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1581:1581:1581) (1660:1660:1660))
        (PORT d[1] (1840:1840:1840) (1925:1925:1925))
        (PORT d[2] (1624:1624:1624) (1665:1665:1665))
        (PORT d[3] (1599:1599:1599) (1691:1691:1691))
        (PORT d[4] (1841:1841:1841) (1935:1935:1935))
        (PORT d[5] (1403:1403:1403) (1484:1484:1484))
        (PORT d[6] (1929:1929:1929) (2040:2040:2040))
        (PORT d[7] (1873:1873:1873) (1970:1970:1970))
        (PORT d[8] (1769:1769:1769) (1820:1820:1820))
        (PORT d[9] (1856:1856:1856) (1929:1929:1929))
        (PORT d[10] (1566:1566:1566) (1643:1643:1643))
        (PORT d[11] (1835:1835:1835) (1901:1901:1901))
        (PORT d[12] (1874:1874:1874) (1971:1971:1971))
        (PORT clk (1640:1640:1640) (1668:1668:1668))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1643:1643:1643) (1670:1670:1670))
        (PORT d[0] (1218:1218:1218) (1192:1192:1192))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1607:1607:1607) (1634:1634:1634))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2947:2947:2947) (2943:2943:2943))
        (PORT clk (1643:1643:1643) (1672:1672:1672))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1561:1561:1561) (1639:1639:1639))
        (PORT d[1] (1828:1828:1828) (1897:1897:1897))
        (PORT d[2] (1798:1798:1798) (1859:1859:1859))
        (PORT d[3] (1600:1600:1600) (1692:1692:1692))
        (PORT d[4] (1842:1842:1842) (1936:1936:1936))
        (PORT d[5] (1404:1404:1404) (1485:1485:1485))
        (PORT d[6] (1930:1930:1930) (2041:2041:2041))
        (PORT d[7] (1874:1874:1874) (1971:1971:1971))
        (PORT d[8] (1770:1770:1770) (1821:1821:1821))
        (PORT d[9] (1857:1857:1857) (1930:1930:1930))
        (PORT d[10] (1567:1567:1567) (1644:1644:1644))
        (PORT d[11] (1836:1836:1836) (1902:1902:1902))
        (PORT d[12] (1875:1875:1875) (1972:1972:1972))
        (PORT clk (1642:1642:1642) (1670:1670:1670))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1643:1643:1643) (1672:1672:1672))
        (PORT d[0] (1218:1218:1218) (1192:1192:1192))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1608:1608:1608) (1636:1636:1636))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[2\]\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (2061:2061:2061) (2194:2194:2194))
        (PORT datac (845:845:845) (835:835:835))
        (PORT datad (1215:1215:1215) (1172:1172:1172))
        (IOPATH dataa combout (307:307:307) (306:306:306))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2670:2670:2670) (2660:2660:2660))
        (PORT clk (1653:1653:1653) (1680:1680:1680))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1801:1801:1801) (1882:1882:1882))
        (PORT d[1] (1803:1803:1803) (1897:1897:1897))
        (PORT d[2] (1823:1823:1823) (1887:1887:1887))
        (PORT d[3] (1633:1633:1633) (1731:1731:1731))
        (PORT d[4] (1800:1800:1800) (1895:1895:1895))
        (PORT d[5] (1727:1727:1727) (1819:1819:1819))
        (PORT d[6] (1911:1911:1911) (1984:1984:1984))
        (PORT d[7] (1813:1813:1813) (1886:1886:1886))
        (PORT d[8] (2072:2072:2072) (2147:2147:2147))
        (PORT d[9] (1871:1871:1871) (1969:1969:1969))
        (PORT d[10] (2034:2034:2034) (2187:2187:2187))
        (PORT d[11] (2081:2081:2081) (2128:2128:2128))
        (PORT d[12] (1913:1913:1913) (2017:2017:2017))
        (PORT clk (1650:1650:1650) (1678:1678:1678))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1653:1653:1653) (1680:1680:1680))
        (PORT d[0] (1417:1417:1417) (1433:1433:1433))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1654:1654:1654) (1681:1681:1681))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1654:1654:1654) (1681:1681:1681))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1654:1654:1654) (1681:1681:1681))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1654:1654:1654) (1681:1681:1681))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1617:1617:1617) (1644:1644:1644))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2674:2674:2674) (2664:2664:2664))
        (PORT clk (1653:1653:1653) (1682:1682:1682))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1782:1782:1782) (1861:1861:1861))
        (PORT d[1] (1790:1790:1790) (1876:1876:1876))
        (PORT d[2] (1778:1778:1778) (1844:1844:1844))
        (PORT d[3] (1634:1634:1634) (1732:1732:1732))
        (PORT d[4] (1781:1781:1781) (1875:1875:1875))
        (PORT d[5] (1728:1728:1728) (1820:1820:1820))
        (PORT d[6] (1912:1912:1912) (1985:1985:1985))
        (PORT d[7] (1814:1814:1814) (1887:1887:1887))
        (PORT d[8] (2073:2073:2073) (2148:2148:2148))
        (PORT d[9] (1872:1872:1872) (1970:1970:1970))
        (PORT d[10] (2035:2035:2035) (2188:2188:2188))
        (PORT d[11] (2082:2082:2082) (2129:2129:2129))
        (PORT d[12] (1914:1914:1914) (2018:2018:2018))
        (PORT clk (1652:1652:1652) (1680:1680:1680))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1653:1653:1653) (1682:1682:1682))
        (PORT d[0] (1417:1417:1417) (1433:1433:1433))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1654:1654:1654) (1683:1683:1683))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1654:1654:1654) (1683:1683:1683))
        (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1654:1654:1654) (1683:1683:1683))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1654:1654:1654) (1683:1683:1683))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1618:1618:1618) (1646:1646:1646))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2136:2136:2136) (2135:2135:2135))
        (PORT clk (1657:1657:1657) (1683:1683:1683))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1816:1816:1816) (1907:1907:1907))
        (PORT d[1] (1779:1779:1779) (1879:1879:1879))
        (PORT d[2] (1754:1754:1754) (1812:1812:1812))
        (PORT d[3] (1869:1869:1869) (1959:1959:1959))
        (PORT d[4] (2052:2052:2052) (2146:2146:2146))
        (PORT d[5] (1646:1646:1646) (1724:1724:1724))
        (PORT d[6] (1869:1869:1869) (1956:1956:1956))
        (PORT d[7] (1872:1872:1872) (1961:1961:1961))
        (PORT d[8] (1741:1741:1741) (1799:1799:1799))
        (PORT d[9] (1869:1869:1869) (1964:1964:1964))
        (PORT d[10] (2133:2133:2133) (2201:2201:2201))
        (PORT d[11] (1866:1866:1866) (1911:1911:1911))
        (PORT d[12] (1919:1919:1919) (2023:2023:2023))
        (PORT clk (1654:1654:1654) (1681:1681:1681))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1657:1657:1657) (1683:1683:1683))
        (PORT d[0] (1446:1446:1446) (1411:1411:1411))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1658:1658:1658) (1684:1684:1684))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1658:1658:1658) (1684:1684:1684))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1658:1658:1658) (1684:1684:1684))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1658:1658:1658) (1684:1684:1684))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1621:1621:1621) (1647:1647:1647))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2140:2140:2140) (2139:2139:2139))
        (PORT clk (1657:1657:1657) (1685:1685:1685))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1796:1796:1796) (1887:1887:1887))
        (PORT d[1] (1780:1780:1780) (1880:1880:1880))
        (PORT d[2] (1768:1768:1768) (1842:1842:1842))
        (PORT d[3] (1870:1870:1870) (1960:1960:1960))
        (PORT d[4] (2074:2074:2074) (2167:2167:2167))
        (PORT d[5] (1647:1647:1647) (1725:1725:1725))
        (PORT d[6] (1870:1870:1870) (1957:1957:1957))
        (PORT d[7] (1873:1873:1873) (1962:1962:1962))
        (PORT d[8] (1742:1742:1742) (1800:1800:1800))
        (PORT d[9] (1870:1870:1870) (1965:1965:1965))
        (PORT d[10] (2134:2134:2134) (2202:2202:2202))
        (PORT d[11] (1867:1867:1867) (1912:1912:1912))
        (PORT d[12] (1920:1920:1920) (2024:2024:2024))
        (PORT clk (1656:1656:1656) (1683:1683:1683))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1657:1657:1657) (1685:1685:1685))
        (PORT d[0] (1446:1446:1446) (1411:1411:1411))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1658:1658:1658) (1686:1686:1686))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1658:1658:1658) (1686:1686:1686))
        (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1658:1658:1658) (1686:1686:1686))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1658:1658:1658) (1686:1686:1686))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1622:1622:1622) (1649:1649:1649))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux4\|result_node\[3\]\~7)
    (DELAY
      (ABSOLUTE
        (PORT dataa (555:555:555) (536:536:536))
        (PORT datac (806:806:806) (852:852:852))
        (PORT datad (604:604:604) (607:607:607))
        (IOPATH dataa combout (307:307:307) (306:306:306))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE A\[14\]\~41)
    (DELAY
      (ABSOLUTE
        (PORT dataa (260:260:260) (333:333:333))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH cin combout (408:408:408) (387:387:387))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE A\[14\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1344:1344:1344) (1361:1361:1361))
        (PORT d (67:67:67) (78:78:78))
        (PORT ena (754:754:754) (770:770:770))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
      (HOLD ena (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT datac (572:572:572) (597:597:597))
        (PORT datad (420:420:420) (464:464:464))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2019:2019:2019) (1994:1994:1994))
        (PORT clk (1646:1646:1646) (1674:1674:1674))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1232:1232:1232) (1284:1284:1284))
        (PORT d[1] (1224:1224:1224) (1272:1272:1272))
        (PORT d[2] (1260:1260:1260) (1298:1298:1298))
        (PORT d[3] (1251:1251:1251) (1298:1298:1298))
        (PORT d[4] (1204:1204:1204) (1261:1261:1261))
        (PORT d[5] (1179:1179:1179) (1186:1186:1186))
        (PORT d[6] (1198:1198:1198) (1239:1239:1239))
        (PORT d[7] (1389:1389:1389) (1412:1412:1412))
        (PORT d[8] (1257:1257:1257) (1306:1306:1306))
        (PORT d[9] (1238:1238:1238) (1282:1282:1282))
        (PORT d[10] (1234:1234:1234) (1284:1284:1284))
        (PORT d[11] (1247:1247:1247) (1278:1278:1278))
        (PORT d[12] (1290:1290:1290) (1333:1333:1333))
        (PORT clk (1643:1643:1643) (1672:1672:1672))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1674:1674:1674))
        (PORT d[0] (905:905:905) (872:872:872))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1675:1675:1675))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1675:1675:1675))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1675:1675:1675))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1675:1675:1675))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1610:1610:1610) (1638:1638:1638))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (881:881:881) (885:885:885))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (882:882:882) (886:886:886))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (882:882:882) (886:886:886))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (882:882:882) (886:886:886))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~2)
    (DELAY
      (ABSOLUTE
        (PORT datac (571:571:571) (597:597:597))
        (PORT datad (422:422:422) (463:463:463))
        (IOPATH datac combout (218:218:218) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (842:842:842) (835:835:835))
        (PORT clk (1646:1646:1646) (1674:1674:1674))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1456:1456:1456) (1510:1510:1510))
        (PORT d[1] (1200:1200:1200) (1268:1268:1268))
        (PORT d[2] (1487:1487:1487) (1553:1553:1553))
        (PORT d[3] (1604:1604:1604) (1681:1681:1681))
        (PORT d[4] (1552:1552:1552) (1632:1632:1632))
        (PORT d[5] (1382:1382:1382) (1461:1461:1461))
        (PORT d[6] (1548:1548:1548) (1600:1600:1600))
        (PORT d[7] (1747:1747:1747) (1806:1806:1806))
        (PORT d[8] (1532:1532:1532) (1590:1590:1590))
        (PORT d[9] (1564:1564:1564) (1627:1627:1627))
        (PORT d[10] (1611:1611:1611) (1718:1718:1718))
        (PORT d[11] (1756:1756:1756) (1813:1813:1813))
        (PORT d[12] (1634:1634:1634) (1728:1728:1728))
        (PORT clk (1643:1643:1643) (1672:1672:1672))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1674:1674:1674))
        (PORT d[0] (1243:1243:1243) (1216:1216:1216))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1675:1675:1675))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1675:1675:1675))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1675:1675:1675))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1675:1675:1675))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1610:1610:1610) (1638:1638:1638))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (881:881:881) (885:885:885))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (882:882:882) (886:886:886))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (882:882:882) (886:886:886))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (882:882:882) (886:886:886))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode261w\[2\])
    (DELAY
      (ABSOLUTE
        (PORT datac (572:572:572) (596:596:596))
        (PORT datad (421:421:421) (463:463:463))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2401:2401:2401) (2407:2407:2407))
        (PORT clk (1632:1632:1632) (1660:1660:1660))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1653:1653:1653) (1699:1699:1699))
        (PORT d[1] (1711:1711:1711) (1773:1773:1773))
        (PORT d[2] (1396:1396:1396) (1415:1415:1415))
        (PORT d[3] (1383:1383:1383) (1382:1382:1382))
        (PORT d[4] (1433:1433:1433) (1449:1449:1449))
        (PORT d[5] (1225:1225:1225) (1263:1263:1263))
        (PORT d[6] (1442:1442:1442) (1494:1494:1494))
        (PORT d[7] (1640:1640:1640) (1687:1687:1687))
        (PORT d[8] (1194:1194:1194) (1236:1236:1236))
        (PORT d[9] (1159:1159:1159) (1202:1202:1202))
        (PORT d[10] (1170:1170:1170) (1220:1220:1220))
        (PORT d[11] (1222:1222:1222) (1249:1249:1249))
        (PORT d[12] (1114:1114:1114) (1145:1145:1145))
        (PORT clk (1629:1629:1629) (1658:1658:1658))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1632:1632:1632) (1660:1660:1660))
        (PORT d[0] (993:993:993) (931:931:931))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1633:1633:1633) (1661:1661:1661))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1633:1633:1633) (1661:1661:1661))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1633:1633:1633) (1661:1661:1661))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1633:1633:1633) (1661:1661:1661))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1596:1596:1596) (1624:1624:1624))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (867:867:867) (871:871:871))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (868:868:868) (872:872:872))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (868:868:868) (872:872:872))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (868:868:868) (872:872:872))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~1)
    (DELAY
      (ABSOLUTE
        (PORT datac (571:571:571) (594:594:594))
        (PORT datad (418:418:418) (460:460:460))
        (IOPATH datac combout (218:218:218) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2248:2248:2248) (2259:2259:2259))
        (PORT clk (1645:1645:1645) (1672:1672:1672))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (950:950:950) (991:991:991))
        (PORT d[1] (970:970:970) (1028:1028:1028))
        (PORT d[2] (1002:1002:1002) (1049:1049:1049))
        (PORT d[3] (983:983:983) (1032:1032:1032))
        (PORT d[4] (1440:1440:1440) (1486:1486:1486))
        (PORT d[5] (977:977:977) (1014:1014:1014))
        (PORT d[6] (1025:1025:1025) (1073:1073:1073))
        (PORT d[7] (1175:1175:1175) (1213:1213:1213))
        (PORT d[8] (1228:1228:1228) (1263:1263:1263))
        (PORT d[9] (1023:1023:1023) (1076:1076:1076))
        (PORT d[10] (1241:1241:1241) (1287:1287:1287))
        (PORT d[11] (1046:1046:1046) (1093:1093:1093))
        (PORT d[12] (1190:1190:1190) (1219:1219:1219))
        (PORT clk (1642:1642:1642) (1670:1670:1670))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1672:1672:1672))
        (PORT d[0] (779:779:779) (745:745:745))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1609:1609:1609) (1636:1636:1636))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (880:880:880) (883:883:883))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (881:881:881) (884:884:884))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (881:881:881) (884:884:884))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (881:881:881) (884:884:884))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (606:606:606) (623:623:623))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1673:1673:1673) (1692:1692:1692))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (201:201:201) (259:259:259))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1344:1344:1344) (1362:1362:1362))
        (PORT d (67:67:67) (78:78:78))
        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (144:144:144))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1716:1716:1716) (1790:1790:1790))
        (PORT datab (1053:1053:1053) (1028:1028:1028))
        (PORT datac (789:789:789) (789:789:789))
        (PORT datad (244:244:244) (318:318:318))
        (IOPATH dataa combout (329:329:329) (332:332:332))
        (IOPATH datab combout (319:319:319) (307:307:307))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1089:1089:1089) (1087:1087:1087))
        (PORT datab (1322:1322:1322) (1323:1323:1323))
        (PORT datac (155:155:155) (185:185:185))
        (PORT datad (244:244:244) (318:318:318))
        (IOPATH dataa combout (272:272:272) (269:269:269))
        (IOPATH datab combout (275:275:275) (275:275:275))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1789:1789:1789) (1783:1783:1783))
        (PORT clk (1638:1638:1638) (1666:1666:1666))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2013:2013:2013) (2090:2090:2090))
        (PORT d[1] (1451:1451:1451) (1512:1512:1512))
        (PORT d[2] (1614:1614:1614) (1636:1636:1636))
        (PORT d[3] (1631:1631:1631) (1629:1629:1629))
        (PORT d[4] (1630:1630:1630) (1655:1655:1655))
        (PORT d[5] (1439:1439:1439) (1473:1473:1473))
        (PORT d[6] (1414:1414:1414) (1458:1458:1458))
        (PORT d[7] (1361:1361:1361) (1383:1383:1383))
        (PORT d[8] (1431:1431:1431) (1467:1467:1467))
        (PORT d[9] (1374:1374:1374) (1424:1424:1424))
        (PORT d[10] (1381:1381:1381) (1442:1442:1442))
        (PORT d[11] (1446:1446:1446) (1468:1468:1468))
        (PORT d[12] (1644:1644:1644) (1670:1670:1670))
        (PORT clk (1635:1635:1635) (1664:1664:1664))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1638:1638:1638) (1666:1666:1666))
        (PORT d[0] (1188:1188:1188) (1145:1145:1145))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1667:1667:1667))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1667:1667:1667))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1667:1667:1667))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1667:1667:1667))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1602:1602:1602) (1630:1630:1630))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (873:873:873) (877:877:877))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (878:878:878))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (878:878:878))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (878:878:878))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2098:2098:2098) (2086:2086:2086))
        (PORT clk (1638:1638:1638) (1666:1666:1666))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1834:1834:1834) (1918:1918:1918))
        (PORT d[1] (1412:1412:1412) (1473:1473:1473))
        (PORT d[2] (1624:1624:1624) (1649:1649:1649))
        (PORT d[3] (1631:1631:1631) (1634:1634:1634))
        (PORT d[4] (1626:1626:1626) (1646:1646:1646))
        (PORT d[5] (1463:1463:1463) (1501:1501:1501))
        (PORT d[6] (1438:1438:1438) (1485:1485:1485))
        (PORT d[7] (1344:1344:1344) (1378:1378:1378))
        (PORT d[8] (1429:1429:1429) (1471:1471:1471))
        (PORT d[9] (1393:1393:1393) (1438:1438:1438))
        (PORT d[10] (1401:1401:1401) (1455:1455:1455))
        (PORT d[11] (1470:1470:1470) (1496:1496:1496))
        (PORT d[12] (1616:1616:1616) (1638:1638:1638))
        (PORT clk (1635:1635:1635) (1664:1664:1664))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1638:1638:1638) (1666:1666:1666))
        (PORT d[0] (1156:1156:1156) (1085:1085:1085))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1667:1667:1667))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1667:1667:1667))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1667:1667:1667))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1667:1667:1667))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1602:1602:1602) (1630:1630:1630))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (873:873:873) (877:877:877))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (878:878:878))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (878:878:878))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (878:878:878))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2516:2516:2516) (2536:2536:2536))
        (PORT clk (1640:1640:1640) (1668:1668:1668))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (976:976:976) (1028:1028:1028))
        (PORT d[1] (1004:1004:1004) (1051:1051:1051))
        (PORT d[2] (976:976:976) (1009:1009:1009))
        (PORT d[3] (1237:1237:1237) (1260:1260:1260))
        (PORT d[4] (1205:1205:1205) (1263:1263:1263))
        (PORT d[5] (968:968:968) (1005:1005:1005))
        (PORT d[6] (952:952:952) (988:988:988))
        (PORT d[7] (1139:1139:1139) (1163:1163:1163))
        (PORT d[8] (985:985:985) (1018:1018:1018))
        (PORT d[9] (1029:1029:1029) (1070:1070:1070))
        (PORT d[10] (1007:1007:1007) (1056:1056:1056))
        (PORT d[11] (1022:1022:1022) (1058:1058:1058))
        (PORT d[12] (1000:1000:1000) (1056:1056:1056))
        (PORT clk (1637:1637:1637) (1666:1666:1666))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1640:1640:1640) (1668:1668:1668))
        (PORT d[0] (763:763:763) (705:705:705))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1641:1641:1641) (1669:1669:1669))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1641:1641:1641) (1669:1669:1669))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1641:1641:1641) (1669:1669:1669))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1641:1641:1641) (1669:1669:1669))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1604:1604:1604) (1632:1632:1632))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (875:875:875) (879:879:879))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (876:876:876) (880:880:880))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (876:876:876) (880:880:880))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (876:876:876) (880:880:880))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1419:1419:1419) (1526:1526:1526))
        (PORT datab (1396:1396:1396) (1399:1399:1399))
        (PORT datac (1222:1222:1222) (1181:1181:1181))
        (PORT datad (906:906:906) (957:957:957))
        (IOPATH dataa combout (300:300:300) (323:323:323))
        (IOPATH datab combout (306:306:306) (324:324:324))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (846:846:846) (833:833:833))
        (PORT clk (1638:1638:1638) (1666:1666:1666))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1578:1578:1578) (1701:1701:1701))
        (PORT d[1] (1611:1611:1611) (1701:1701:1701))
        (PORT d[2] (2020:2020:2020) (2087:2087:2087))
        (PORT d[3] (1708:1708:1708) (1741:1741:1741))
        (PORT d[4] (1902:1902:1902) (1974:1974:1974))
        (PORT d[5] (1505:1505:1505) (1554:1554:1554))
        (PORT d[6] (1697:1697:1697) (1744:1744:1744))
        (PORT d[7] (2016:2016:2016) (2081:2081:2081))
        (PORT d[8] (1447:1447:1447) (1491:1491:1491))
        (PORT d[9] (1416:1416:1416) (1481:1481:1481))
        (PORT d[10] (1661:1661:1661) (1776:1776:1776))
        (PORT d[11] (1497:1497:1497) (1540:1540:1540))
        (PORT d[12] (1669:1669:1669) (1721:1721:1721))
        (PORT clk (1635:1635:1635) (1664:1664:1664))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1638:1638:1638) (1666:1666:1666))
        (PORT d[0] (1083:1083:1083) (1076:1076:1076))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1667:1667:1667))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1667:1667:1667))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1667:1667:1667))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1667:1667:1667))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1602:1602:1602) (1630:1630:1630))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (873:873:873) (877:877:877))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (878:878:878))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (878:878:878))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (878:878:878))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~3)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1391:1391:1391) (1398:1398:1398))
        (PORT datab (183:183:183) (216:216:216))
        (PORT datac (1011:1011:1011) (986:986:986))
        (PORT datad (906:906:906) (964:964:964))
        (IOPATH dataa combout (273:273:273) (269:269:269))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datac combout (218:218:218) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2274:2274:2274) (2288:2288:2288))
        (PORT clk (1644:1644:1644) (1670:1670:1670))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (958:958:958) (1000:1000:1000))
        (PORT d[1] (975:975:975) (1031:1031:1031))
        (PORT d[2] (1001:1001:1001) (1048:1048:1048))
        (PORT d[3] (1220:1220:1220) (1252:1252:1252))
        (PORT d[4] (984:984:984) (1041:1041:1041))
        (PORT d[5] (986:986:986) (1027:1027:1027))
        (PORT d[6] (988:988:988) (1041:1041:1041))
        (PORT d[7] (1175:1175:1175) (1212:1212:1212))
        (PORT d[8] (1010:1010:1010) (1057:1057:1057))
        (PORT d[9] (1022:1022:1022) (1075:1075:1075))
        (PORT d[10] (999:999:999) (1058:1058:1058))
        (PORT d[11] (1045:1045:1045) (1092:1092:1092))
        (PORT d[12] (1043:1043:1043) (1091:1091:1091))
        (PORT clk (1641:1641:1641) (1668:1668:1668))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1670:1670:1670))
        (PORT d[0] (706:706:706) (665:665:665))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1608:1608:1608) (1634:1634:1634))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (879:879:879) (881:881:881))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (880:880:880) (882:882:882))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (880:880:880) (882:882:882))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (880:880:880) (882:882:882))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2122:2122:2122) (2118:2118:2118))
        (PORT clk (1635:1635:1635) (1662:1662:1662))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1381:1381:1381) (1424:1424:1424))
        (PORT d[1] (1710:1710:1710) (1772:1772:1772))
        (PORT d[2] (1429:1429:1429) (1475:1475:1475))
        (PORT d[3] (1394:1394:1394) (1403:1403:1403))
        (PORT d[4] (1405:1405:1405) (1433:1433:1433))
        (PORT d[5] (1209:1209:1209) (1255:1255:1255))
        (PORT d[6] (1455:1455:1455) (1494:1494:1494))
        (PORT d[7] (1640:1640:1640) (1686:1686:1686))
        (PORT d[8] (1202:1202:1202) (1255:1255:1255))
        (PORT d[9] (1148:1148:1148) (1200:1200:1200))
        (PORT d[10] (1158:1158:1158) (1217:1217:1217))
        (PORT d[11] (1206:1206:1206) (1241:1241:1241))
        (PORT d[12] (1415:1415:1415) (1450:1450:1450))
        (PORT clk (1632:1632:1632) (1660:1660:1660))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1635:1635:1635) (1662:1662:1662))
        (PORT d[0] (980:980:980) (930:930:930))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1636:1636:1636) (1663:1663:1663))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1636:1636:1636) (1663:1663:1663))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1636:1636:1636) (1663:1663:1663))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1636:1636:1636) (1663:1663:1663))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1599:1599:1599) (1626:1626:1626))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (870:870:870) (873:873:873))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (871:871:871) (874:874:874))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (871:871:871) (874:874:874))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (871:871:871) (874:874:874))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2109:2109:2109) (2107:2107:2107))
        (PORT clk (1637:1637:1637) (1665:1665:1665))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1618:1618:1618) (1658:1658:1658))
        (PORT d[1] (1718:1718:1718) (1770:1770:1770))
        (PORT d[2] (1441:1441:1441) (1485:1485:1485))
        (PORT d[3] (1421:1421:1421) (1448:1448:1448))
        (PORT d[4] (1436:1436:1436) (1459:1459:1459))
        (PORT d[5] (1216:1216:1216) (1264:1264:1264))
        (PORT d[6] (1452:1452:1452) (1490:1490:1490))
        (PORT d[7] (1602:1602:1602) (1636:1636:1636))
        (PORT d[8] (1183:1183:1183) (1235:1235:1235))
        (PORT d[9] (1188:1188:1188) (1244:1244:1244))
        (PORT d[10] (1164:1164:1164) (1225:1225:1225))
        (PORT d[11] (1245:1245:1245) (1283:1283:1283))
        (PORT d[12] (1127:1127:1127) (1167:1167:1167))
        (PORT clk (1634:1634:1634) (1663:1663:1663))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1637:1637:1637) (1665:1665:1665))
        (PORT d[0] (969:969:969) (940:940:940))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1638:1638:1638) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1638:1638:1638) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1638:1638:1638) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1638:1638:1638) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1601:1601:1601) (1629:1629:1629))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (872:872:872) (876:876:876))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (873:873:873) (877:877:877))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (873:873:873) (877:877:877))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (873:873:873) (877:877:877))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1075:1075:1075) (1062:1062:1062))
        (PORT datab (270:270:270) (353:353:353))
        (PORT datac (1398:1398:1398) (1471:1471:1471))
        (PORT datad (1053:1053:1053) (1034:1034:1034))
        (IOPATH dataa combout (318:318:318) (307:307:307))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2546:2546:2546) (2573:2573:2573))
        (PORT clk (1634:1634:1634) (1663:1663:1663))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (703:703:703) (745:745:745))
        (PORT d[1] (683:683:683) (727:727:727))
        (PORT d[2] (931:931:931) (960:960:960))
        (PORT d[3] (1223:1223:1223) (1251:1251:1251))
        (PORT d[4] (989:989:989) (1040:1040:1040))
        (PORT d[5] (1198:1198:1198) (1238:1238:1238))
        (PORT d[6] (940:940:940) (972:972:972))
        (PORT d[7] (1158:1158:1158) (1181:1181:1181))
        (PORT d[8] (968:968:968) (1004:1004:1004))
        (PORT d[9] (988:988:988) (1028:1028:1028))
        (PORT d[10] (1164:1164:1164) (1196:1196:1196))
        (PORT d[11] (1191:1191:1191) (1213:1213:1213))
        (PORT d[12] (1145:1145:1145) (1154:1154:1154))
        (PORT clk (1631:1631:1631) (1661:1661:1661))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1634:1634:1634) (1663:1663:1663))
        (PORT d[0] (754:754:754) (706:706:706))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1635:1635:1635) (1664:1664:1664))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1635:1635:1635) (1664:1664:1664))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1635:1635:1635) (1664:1664:1664))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1635:1635:1635) (1664:1664:1664))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1598:1598:1598) (1627:1627:1627))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (869:869:869) (874:874:874))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (870:870:870) (875:875:875))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (870:870:870) (875:875:875))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (870:870:870) (875:875:875))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~5)
    (DELAY
      (ABSOLUTE
        (PORT dataa (774:774:774) (762:762:762))
        (PORT datab (269:269:269) (353:353:353))
        (PORT datac (155:155:155) (185:185:185))
        (PORT datad (760:760:760) (734:734:734))
        (IOPATH dataa combout (300:300:300) (323:323:323))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1772:1772:1772) (1804:1804:1804))
        (PORT clk (1638:1638:1638) (1665:1665:1665))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1843:1843:1843) (1977:1977:1977))
        (PORT d[1] (1580:1580:1580) (1677:1677:1677))
        (PORT d[2] (1983:1983:1983) (2051:2051:2051))
        (PORT d[3] (2103:2103:2103) (2192:2192:2192))
        (PORT d[4] (1951:1951:1951) (2012:2012:2012))
        (PORT d[5] (1809:1809:1809) (1880:1880:1880))
        (PORT d[6] (1659:1659:1659) (1706:1706:1706))
        (PORT d[7] (1982:1982:1982) (2042:2042:2042))
        (PORT d[8] (1755:1755:1755) (1818:1818:1818))
        (PORT d[9] (1738:1738:1738) (1830:1830:1830))
        (PORT d[10] (1622:1622:1622) (1754:1754:1754))
        (PORT d[11] (1720:1720:1720) (1786:1786:1786))
        (PORT d[12] (1917:1917:1917) (1977:1977:1977))
        (PORT clk (1635:1635:1635) (1663:1663:1663))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1638:1638:1638) (1665:1665:1665))
        (PORT d[0] (1265:1265:1265) (1246:1246:1246))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1602:1602:1602) (1629:1629:1629))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (873:873:873) (876:876:876))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (877:877:877))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (877:877:877))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (877:877:877))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2806:2806:2806) (2845:2845:2845))
        (PORT clk (1644:1644:1644) (1670:1670:1670))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (966:966:966) (1011:1011:1011))
        (PORT d[1] (938:938:938) (997:997:997))
        (PORT d[2] (1198:1198:1198) (1237:1237:1237))
        (PORT d[3] (1257:1257:1257) (1319:1319:1319))
        (PORT d[4] (1270:1270:1270) (1336:1336:1336))
        (PORT d[5] (1372:1372:1372) (1448:1448:1448))
        (PORT d[6] (1256:1256:1256) (1310:1310:1310))
        (PORT d[7] (1464:1464:1464) (1511:1511:1511))
        (PORT d[8] (1242:1242:1242) (1290:1290:1290))
        (PORT d[9] (1275:1275:1275) (1328:1328:1328))
        (PORT d[10] (1258:1258:1258) (1332:1332:1332))
        (PORT d[11] (1470:1470:1470) (1503:1503:1503))
        (PORT d[12] (1229:1229:1229) (1258:1258:1258))
        (PORT clk (1641:1641:1641) (1668:1668:1668))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1670:1670:1670))
        (PORT d[0] (1014:1014:1014) (987:987:987))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1608:1608:1608) (1634:1634:1634))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (879:879:879) (881:881:881))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (880:880:880) (882:882:882))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (880:880:880) (882:882:882))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (880:880:880) (882:882:882))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1417:1417:1417) (1524:1524:1524))
        (PORT datab (949:949:949) (999:999:999))
        (PORT datac (1329:1329:1329) (1312:1312:1312))
        (PORT datad (997:997:997) (964:964:964))
        (IOPATH dataa combout (300:300:300) (323:323:323))
        (IOPATH datab combout (306:306:306) (324:324:324))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2411:2411:2411) (2414:2414:2414))
        (PORT clk (1630:1630:1630) (1658:1658:1658))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1663:1663:1663) (1721:1721:1721))
        (PORT d[1] (959:959:959) (1001:1001:1001))
        (PORT d[2] (1143:1143:1143) (1186:1186:1186))
        (PORT d[3] (1087:1087:1087) (1109:1109:1109))
        (PORT d[4] (1150:1150:1150) (1174:1174:1174))
        (PORT d[5] (971:971:971) (1020:1020:1020))
        (PORT d[6] (1466:1466:1466) (1521:1521:1521))
        (PORT d[7] (1437:1437:1437) (1466:1466:1466))
        (PORT d[8] (930:930:930) (967:967:967))
        (PORT d[9] (877:877:877) (919:919:919))
        (PORT d[10] (977:977:977) (1016:1016:1016))
        (PORT d[11] (906:906:906) (944:944:944))
        (PORT d[12] (883:883:883) (915:915:915))
        (PORT clk (1627:1627:1627) (1656:1656:1656))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1630:1630:1630) (1658:1658:1658))
        (PORT d[0] (735:735:735) (688:688:688))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1631:1631:1631) (1659:1659:1659))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1631:1631:1631) (1659:1659:1659))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1631:1631:1631) (1659:1659:1659))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1631:1631:1631) (1659:1659:1659))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1594:1594:1594) (1622:1622:1622))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (865:865:865) (869:869:869))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (866:866:866) (870:870:870))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (866:866:866) (870:870:870))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (866:866:866) (870:870:870))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2801:2801:2801) (2820:2820:2820))
        (PORT clk (1638:1638:1638) (1665:1665:1665))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (963:963:963) (998:998:998))
        (PORT d[1] (924:924:924) (970:970:970))
        (PORT d[2] (941:941:941) (970:970:970))
        (PORT d[3] (994:994:994) (1036:1036:1036))
        (PORT d[4] (965:965:965) (1016:1016:1016))
        (PORT d[5] (1412:1412:1412) (1493:1493:1493))
        (PORT d[6] (984:984:984) (1029:1029:1029))
        (PORT d[7] (1193:1193:1193) (1229:1229:1229))
        (PORT d[8] (977:977:977) (1024:1024:1024))
        (PORT d[9] (1019:1019:1019) (1071:1071:1071))
        (PORT d[10] (1176:1176:1176) (1216:1216:1216))
        (PORT d[11] (1237:1237:1237) (1265:1265:1265))
        (PORT d[12] (972:972:972) (1015:1015:1015))
        (PORT clk (1635:1635:1635) (1663:1663:1663))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1638:1638:1638) (1665:1665:1665))
        (PORT d[0] (757:757:757) (716:716:716))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1602:1602:1602) (1629:1629:1629))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (873:873:873) (876:876:876))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (877:877:877))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (877:877:877))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (877:877:877))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~7)
    (DELAY
      (ABSOLUTE
        (PORT dataa (184:184:184) (221:221:221))
        (PORT datab (945:945:945) (993:993:993))
        (PORT datac (1023:1023:1023) (1023:1023:1023))
        (PORT datad (969:969:969) (939:939:939))
        (IOPATH dataa combout (318:318:318) (307:307:307))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2120:2120:2120) (2118:2118:2118))
        (PORT clk (1636:1636:1636) (1662:1662:1662))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1345:1345:1345) (1396:1396:1396))
        (PORT d[1] (1168:1168:1168) (1224:1224:1224))
        (PORT d[2] (1440:1440:1440) (1484:1484:1484))
        (PORT d[3] (1421:1421:1421) (1445:1445:1445))
        (PORT d[4] (1435:1435:1435) (1458:1458:1458))
        (PORT d[5] (1240:1240:1240) (1292:1292:1292))
        (PORT d[6] (1163:1163:1163) (1216:1216:1216))
        (PORT d[7] (1131:1131:1131) (1148:1148:1148))
        (PORT d[8] (1182:1182:1182) (1234:1234:1234))
        (PORT d[9] (1187:1187:1187) (1243:1243:1243))
        (PORT d[10] (1163:1163:1163) (1224:1224:1224))
        (PORT d[11] (1219:1219:1219) (1253:1253:1253))
        (PORT d[12] (1151:1151:1151) (1186:1186:1186))
        (PORT clk (1633:1633:1633) (1660:1660:1660))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1636:1636:1636) (1662:1662:1662))
        (PORT d[0] (975:975:975) (944:944:944))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1637:1637:1637) (1663:1663:1663))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1637:1637:1637) (1663:1663:1663))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1637:1637:1637) (1663:1663:1663))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1637:1637:1637) (1663:1663:1663))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1600:1600:1600) (1626:1626:1626))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (871:871:871) (873:873:873))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (872:872:872) (874:874:874))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (872:872:872) (874:874:874))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (872:872:872) (874:874:874))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1129:1129:1129) (1138:1138:1138))
        (PORT clk (1635:1635:1635) (1662:1662:1662))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1576:1576:1576) (1690:1690:1690))
        (PORT d[1] (1257:1257:1257) (1308:1308:1308))
        (PORT d[2] (1422:1422:1422) (1464:1464:1464))
        (PORT d[3] (1497:1497:1497) (1539:1539:1539))
        (PORT d[4] (1679:1679:1679) (1737:1737:1737))
        (PORT d[5] (1256:1256:1256) (1305:1305:1305))
        (PORT d[6] (1421:1421:1421) (1460:1460:1460))
        (PORT d[7] (1724:1724:1724) (1778:1778:1778))
        (PORT d[8] (1174:1174:1174) (1207:1207:1207))
        (PORT d[9] (1143:1143:1143) (1200:1200:1200))
        (PORT d[10] (1628:1628:1628) (1759:1759:1759))
        (PORT d[11] (1171:1171:1171) (1220:1220:1220))
        (PORT d[12] (1390:1390:1390) (1431:1431:1431))
        (PORT clk (1632:1632:1632) (1660:1660:1660))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1635:1635:1635) (1662:1662:1662))
        (PORT d[0] (1049:1049:1049) (984:984:984))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1636:1636:1636) (1663:1663:1663))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1636:1636:1636) (1663:1663:1663))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1636:1636:1636) (1663:1663:1663))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1636:1636:1636) (1663:1663:1663))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1599:1599:1599) (1626:1626:1626))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (870:870:870) (873:873:873))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (871:871:871) (874:874:874))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (871:871:871) (874:874:874))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (871:871:871) (874:874:874))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (3048:3048:3048) (3087:3087:3087))
        (PORT clk (1646:1646:1646) (1673:1673:1673))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1288:1288:1288) (1341:1341:1341))
        (PORT d[1] (1198:1198:1198) (1262:1262:1262))
        (PORT d[2] (1259:1259:1259) (1316:1316:1316))
        (PORT d[3] (1261:1261:1261) (1319:1319:1319))
        (PORT d[4] (1257:1257:1257) (1328:1328:1328))
        (PORT d[5] (1381:1381:1381) (1446:1446:1446))
        (PORT d[6] (1518:1518:1518) (1575:1575:1575))
        (PORT d[7] (1523:1523:1523) (1576:1576:1576))
        (PORT d[8] (1290:1290:1290) (1340:1340:1340))
        (PORT d[9] (1310:1310:1310) (1377:1377:1377))
        (PORT d[10] (1248:1248:1248) (1314:1314:1314))
        (PORT d[11] (1722:1722:1722) (1758:1758:1758))
        (PORT d[12] (1602:1602:1602) (1688:1688:1688))
        (PORT clk (1643:1643:1643) (1671:1671:1671))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1673:1673:1673))
        (PORT d[0] (974:974:974) (928:928:928))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1674:1674:1674))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1674:1674:1674))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1674:1674:1674))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1674:1674:1674))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1610:1610:1610) (1637:1637:1637))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (881:881:881) (884:884:884))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (882:882:882) (885:885:885))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (882:882:882) (885:885:885))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (882:882:882) (885:885:885))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~8)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1417:1417:1417) (1526:1526:1526))
        (PORT datab (946:946:946) (1000:1000:1000))
        (PORT datac (788:788:788) (766:766:766))
        (PORT datad (1141:1141:1141) (1132:1132:1132))
        (IOPATH dataa combout (307:307:307) (323:323:323))
        (IOPATH datab combout (306:306:306) (324:324:324))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (849:849:849) (867:867:867))
        (PORT clk (1646:1646:1646) (1672:1672:1672))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1474:1474:1474) (1535:1535:1535))
        (PORT d[1] (1851:1851:1851) (1928:1928:1928))
        (PORT d[2] (1496:1496:1496) (1566:1566:1566))
        (PORT d[3] (1593:1593:1593) (1669:1669:1669))
        (PORT d[4] (1739:1739:1739) (1818:1818:1818))
        (PORT d[5] (1363:1363:1363) (1439:1439:1439))
        (PORT d[6] (1536:1536:1536) (1596:1596:1596))
        (PORT d[7] (1756:1756:1756) (1820:1820:1820))
        (PORT d[8] (1550:1550:1550) (1628:1628:1628))
        (PORT d[9] (1605:1605:1605) (1688:1688:1688))
        (PORT d[10] (1577:1577:1577) (1685:1685:1685))
        (PORT d[11] (1447:1447:1447) (1488:1488:1488))
        (PORT d[12] (1633:1633:1633) (1720:1720:1720))
        (PORT clk (1643:1643:1643) (1670:1670:1670))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1672:1672:1672))
        (PORT d[0] (1200:1200:1200) (1169:1169:1169))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1610:1610:1610) (1636:1636:1636))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (881:881:881) (883:883:883))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (882:882:882) (884:884:884))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (882:882:882) (884:884:884))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (882:882:882) (884:884:884))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~9)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1327:1327:1327) (1312:1312:1312))
        (PORT datab (182:182:182) (215:215:215))
        (PORT datac (1270:1270:1270) (1243:1243:1243))
        (PORT datad (910:910:910) (957:957:957))
        (IOPATH dataa combout (273:273:273) (269:269:269))
        (IOPATH datab combout (319:319:319) (324:324:324))
        (IOPATH datac combout (218:218:218) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2810:2810:2810) (2848:2848:2848))
        (PORT clk (1643:1643:1643) (1670:1670:1670))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (985:985:985) (1032:1032:1032))
        (PORT d[1] (1166:1166:1166) (1199:1199:1199))
        (PORT d[2] (943:943:943) (974:974:974))
        (PORT d[3] (1000:1000:1000) (1058:1058:1058))
        (PORT d[4] (974:974:974) (1029:1029:1029))
        (PORT d[5] (1398:1398:1398) (1477:1477:1477))
        (PORT d[6] (980:980:980) (1019:1019:1019))
        (PORT d[7] (1228:1228:1228) (1268:1268:1268))
        (PORT d[8] (1010:1010:1010) (1062:1062:1062))
        (PORT d[9] (1005:1005:1005) (1059:1059:1059))
        (PORT d[10] (1187:1187:1187) (1225:1225:1225))
        (PORT d[11] (1191:1191:1191) (1224:1224:1224))
        (PORT d[12] (1009:1009:1009) (1055:1055:1055))
        (PORT clk (1640:1640:1640) (1668:1668:1668))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1643:1643:1643) (1670:1670:1670))
        (PORT d[0] (727:727:727) (696:696:696))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1607:1607:1607) (1634:1634:1634))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (878:878:878) (881:881:881))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (879:879:879) (882:882:882))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (879:879:879) (882:882:882))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (879:879:879) (882:882:882))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1416:1416:1416) (1433:1433:1433))
        (PORT clk (1632:1632:1632) (1660:1660:1660))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1558:1558:1558) (1674:1674:1674))
        (PORT d[1] (1236:1236:1236) (1286:1286:1286))
        (PORT d[2] (1486:1486:1486) (1541:1541:1541))
        (PORT d[3] (1384:1384:1384) (1412:1412:1412))
        (PORT d[4] (1366:1366:1366) (1419:1419:1419))
        (PORT d[5] (1230:1230:1230) (1276:1276:1276))
        (PORT d[6] (1416:1416:1416) (1452:1452:1452))
        (PORT d[7] (1733:1733:1733) (1798:1798:1798))
        (PORT d[8] (1199:1199:1199) (1234:1234:1234))
        (PORT d[9] (1163:1163:1163) (1221:1221:1221))
        (PORT d[10] (1220:1220:1220) (1287:1287:1287))
        (PORT d[11] (1237:1237:1237) (1277:1277:1277))
        (PORT d[12] (1369:1369:1369) (1408:1408:1408))
        (PORT clk (1629:1629:1629) (1658:1658:1658))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1632:1632:1632) (1660:1660:1660))
        (PORT d[0] (1000:1000:1000) (964:964:964))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1633:1633:1633) (1661:1661:1661))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1633:1633:1633) (1661:1661:1661))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1633:1633:1633) (1661:1661:1661))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1633:1633:1633) (1661:1661:1661))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1596:1596:1596) (1624:1624:1624))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (867:867:867) (871:871:871))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (868:868:868) (872:872:872))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (868:868:868) (872:872:872))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (868:868:868) (872:872:872))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2788:2788:2788) (2821:2821:2821))
        (PORT clk (1640:1640:1640) (1668:1668:1668))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (946:946:946) (982:982:982))
        (PORT d[1] (933:933:933) (988:988:988))
        (PORT d[2] (1013:1013:1013) (1049:1049:1049))
        (PORT d[3] (976:976:976) (1031:1031:1031))
        (PORT d[4] (974:974:974) (1029:1029:1029))
        (PORT d[5] (1386:1386:1386) (1464:1464:1464))
        (PORT d[6] (1256:1256:1256) (1301:1301:1301))
        (PORT d[7] (1207:1207:1207) (1246:1246:1246))
        (PORT d[8] (983:983:983) (1032:1032:1032))
        (PORT d[9] (1025:1025:1025) (1080:1080:1080))
        (PORT d[10] (1161:1161:1161) (1196:1196:1196))
        (PORT d[11] (1264:1264:1264) (1292:1292:1292))
        (PORT d[12] (1160:1160:1160) (1184:1184:1184))
        (PORT clk (1637:1637:1637) (1666:1666:1666))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1640:1640:1640) (1668:1668:1668))
        (PORT d[0] (785:785:785) (747:747:747))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1641:1641:1641) (1669:1669:1669))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1641:1641:1641) (1669:1669:1669))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1641:1641:1641) (1669:1669:1669))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1641:1641:1641) (1669:1669:1669))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1604:1604:1604) (1632:1632:1632))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (875:875:875) (879:879:879))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (876:876:876) (880:880:880))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (876:876:876) (880:880:880))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (876:876:876) (880:880:880))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~10)
    (DELAY
      (ABSOLUTE
        (PORT dataa (889:889:889) (872:872:872))
        (PORT datab (950:950:950) (994:994:994))
        (PORT datac (978:978:978) (949:949:949))
        (PORT datad (1392:1392:1392) (1484:1484:1484))
        (IOPATH dataa combout (318:318:318) (307:307:307))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datac combout (218:218:218) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (3061:3061:3061) (3086:3086:3086))
        (PORT clk (1645:1645:1645) (1672:1672:1672))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1256:1256:1256) (1311:1311:1311))
        (PORT d[1] (1190:1190:1190) (1241:1241:1241))
        (PORT d[2] (1217:1217:1217) (1258:1258:1258))
        (PORT d[3] (1261:1261:1261) (1324:1324:1324))
        (PORT d[4] (1247:1247:1247) (1314:1314:1314))
        (PORT d[5] (1394:1394:1394) (1470:1470:1470))
        (PORT d[6] (1282:1282:1282) (1339:1339:1339))
        (PORT d[7] (1502:1502:1502) (1554:1554:1554))
        (PORT d[8] (1251:1251:1251) (1307:1307:1307))
        (PORT d[9] (1304:1304:1304) (1369:1369:1369))
        (PORT d[10] (1484:1484:1484) (1542:1542:1542))
        (PORT d[11] (1484:1484:1484) (1531:1531:1531))
        (PORT d[12] (1233:1233:1233) (1278:1278:1278))
        (PORT clk (1642:1642:1642) (1670:1670:1670))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1672:1672:1672))
        (PORT d[0] (1033:1033:1033) (995:995:995))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1609:1609:1609) (1636:1636:1636))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (880:880:880) (883:883:883))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (881:881:881) (884:884:884))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (881:881:881) (884:884:884))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (881:881:881) (884:884:884))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~11)
    (DELAY
      (ABSOLUTE
        (PORT dataa (751:751:751) (721:721:721))
        (PORT datab (944:944:944) (994:994:994))
        (PORT datac (157:157:157) (187:187:187))
        (PORT datad (1009:1009:1009) (972:972:972))
        (IOPATH dataa combout (300:300:300) (323:323:323))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1388:1388:1388) (1408:1408:1408))
        (PORT clk (1630:1630:1630) (1658:1658:1658))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1697:1697:1697) (1753:1753:1753))
        (PORT d[1] (1250:1250:1250) (1299:1299:1299))
        (PORT d[2] (1380:1380:1380) (1426:1426:1426))
        (PORT d[3] (1380:1380:1380) (1410:1410:1410))
        (PORT d[4] (1363:1363:1363) (1407:1407:1407))
        (PORT d[5] (1225:1225:1225) (1269:1269:1269))
        (PORT d[6] (1433:1433:1433) (1461:1461:1461))
        (PORT d[7] (1163:1163:1163) (1202:1202:1202))
        (PORT d[8] (1439:1439:1439) (1464:1464:1464))
        (PORT d[9] (1161:1161:1161) (1219:1219:1219))
        (PORT d[10] (1441:1441:1441) (1495:1495:1495))
        (PORT d[11] (1166:1166:1166) (1213:1213:1213))
        (PORT d[12] (1393:1393:1393) (1412:1412:1412))
        (PORT clk (1627:1627:1627) (1656:1656:1656))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1630:1630:1630) (1658:1658:1658))
        (PORT d[0] (1018:1018:1018) (944:944:944))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1631:1631:1631) (1659:1659:1659))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1631:1631:1631) (1659:1659:1659))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1631:1631:1631) (1659:1659:1659))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1631:1631:1631) (1659:1659:1659))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1594:1594:1594) (1622:1622:1622))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (865:865:865) (869:869:869))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (866:866:866) (870:870:870))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (866:866:866) (870:870:870))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (866:866:866) (870:870:870))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2391:2391:2391) (2394:2394:2394))
        (PORT clk (1626:1626:1626) (1655:1655:1655))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1675:1675:1675) (1730:1730:1730))
        (PORT d[1] (1437:1437:1437) (1460:1460:1460))
        (PORT d[2] (1414:1414:1414) (1447:1447:1447))
        (PORT d[3] (1400:1400:1400) (1420:1420:1420))
        (PORT d[4] (1359:1359:1359) (1382:1382:1382))
        (PORT d[5] (1195:1195:1195) (1228:1228:1228))
        (PORT d[6] (1165:1165:1165) (1188:1188:1188))
        (PORT d[7] (1430:1430:1430) (1454:1454:1454))
        (PORT d[8] (1181:1181:1181) (1204:1204:1204))
        (PORT d[9] (1126:1126:1126) (1168:1168:1168))
        (PORT d[10] (1495:1495:1495) (1563:1563:1563))
        (PORT d[11] (1191:1191:1191) (1216:1216:1216))
        (PORT d[12] (1354:1354:1354) (1383:1383:1383))
        (PORT clk (1623:1623:1623) (1653:1653:1653))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1626:1626:1626) (1655:1655:1655))
        (PORT d[0] (979:979:979) (906:906:906))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1627:1627:1627) (1656:1656:1656))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1627:1627:1627) (1656:1656:1656))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1627:1627:1627) (1656:1656:1656))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1627:1627:1627) (1656:1656:1656))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1590:1590:1590) (1619:1619:1619))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (861:861:861) (866:866:866))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (862:862:862) (867:867:867))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (862:862:862) (867:867:867))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (862:862:862) (867:867:867))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~12)
    (DELAY
      (ABSOLUTE
        (PORT dataa (877:877:877) (900:900:900))
        (PORT datab (816:816:816) (796:796:796))
        (PORT datac (1044:1044:1044) (1008:1008:1008))
        (PORT datad (1584:1584:1584) (1626:1626:1626))
        (IOPATH dataa combout (318:318:318) (327:327:327))
        (IOPATH datab combout (275:275:275) (275:275:275))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1124:1124:1124) (1131:1131:1131))
        (PORT clk (1637:1637:1637) (1665:1665:1665))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1491:1491:1491) (1582:1582:1582))
        (PORT d[1] (1507:1507:1507) (1554:1554:1554))
        (PORT d[2] (1712:1712:1712) (1756:1756:1756))
        (PORT d[3] (1651:1651:1651) (1679:1679:1679))
        (PORT d[4] (1674:1674:1674) (1745:1745:1745))
        (PORT d[5] (1524:1524:1524) (1583:1583:1583))
        (PORT d[6] (1711:1711:1711) (1749:1749:1749))
        (PORT d[7] (1451:1451:1451) (1515:1515:1515))
        (PORT d[8] (1467:1467:1467) (1511:1511:1511))
        (PORT d[9] (1438:1438:1438) (1495:1495:1495))
        (PORT d[10] (1623:1623:1623) (1752:1752:1752))
        (PORT d[11] (1556:1556:1556) (1610:1610:1610))
        (PORT d[12] (1662:1662:1662) (1712:1712:1712))
        (PORT clk (1634:1634:1634) (1663:1663:1663))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1637:1637:1637) (1665:1665:1665))
        (PORT d[0] (1143:1143:1143) (1159:1159:1159))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1638:1638:1638) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1638:1638:1638) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1638:1638:1638) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1638:1638:1638) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1601:1601:1601) (1629:1629:1629))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (872:872:872) (876:876:876))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (873:873:873) (877:877:877))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (873:873:873) (877:877:877))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (873:873:873) (877:877:877))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2539:2539:2539) (2563:2563:2563))
        (PORT clk (1638:1638:1638) (1665:1665:1665))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (677:677:677) (719:719:719))
        (PORT d[1] (676:676:676) (718:718:718))
        (PORT d[2] (694:694:694) (717:717:717))
        (PORT d[3] (742:742:742) (767:767:767))
        (PORT d[4] (1205:1205:1205) (1258:1258:1258))
        (PORT d[5] (793:793:793) (834:834:834))
        (PORT d[6] (1236:1236:1236) (1255:1255:1255))
        (PORT d[7] (698:698:698) (730:730:730))
        (PORT d[8] (699:699:699) (737:737:737))
        (PORT d[9] (714:714:714) (751:751:751))
        (PORT d[10] (723:723:723) (763:763:763))
        (PORT d[11] (741:741:741) (774:774:774))
        (PORT d[12] (1635:1635:1635) (1718:1718:1718))
        (PORT clk (1635:1635:1635) (1663:1663:1663))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1638:1638:1638) (1665:1665:1665))
        (PORT d[0] (662:662:662) (590:590:590))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1639:1639:1639) (1666:1666:1666))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1602:1602:1602) (1629:1629:1629))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (873:873:873) (876:876:876))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (877:877:877))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (877:877:877))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (874:874:874) (877:877:877))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~13)
    (DELAY
      (ABSOLUTE
        (PORT dataa (875:875:875) (898:898:898))
        (PORT datab (183:183:183) (216:216:216))
        (PORT datac (1068:1068:1068) (1024:1024:1024))
        (PORT datad (973:973:973) (922:922:922))
        (IOPATH dataa combout (329:329:329) (332:332:332))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2529:2529:2529) (2535:2535:2535))
        (PORT clk (1643:1643:1643) (1670:1670:1670))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (978:978:978) (1036:1036:1036))
        (PORT d[1] (984:984:984) (1046:1046:1046))
        (PORT d[2] (1008:1008:1008) (1053:1053:1053))
        (PORT d[3] (1014:1014:1014) (1059:1059:1059))
        (PORT d[4] (974:974:974) (1025:1025:1025))
        (PORT d[5] (1671:1671:1671) (1757:1757:1757))
        (PORT d[6] (1223:1223:1223) (1259:1259:1259))
        (PORT d[7] (1148:1148:1148) (1182:1182:1182))
        (PORT d[8] (992:992:992) (1032:1032:1032))
        (PORT d[9] (1017:1017:1017) (1067:1067:1067))
        (PORT d[10] (970:970:970) (1025:1025:1025))
        (PORT d[11] (1007:1007:1007) (1050:1050:1050))
        (PORT d[12] (1055:1055:1055) (1109:1109:1109))
        (PORT clk (1640:1640:1640) (1668:1668:1668))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1643:1643:1643) (1670:1670:1670))
        (PORT d[0] (755:755:755) (724:724:724))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1644:1644:1644) (1671:1671:1671))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1607:1607:1607) (1634:1634:1634))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (878:878:878) (881:881:881))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (879:879:879) (882:882:882))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (879:879:879) (882:882:882))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (879:879:879) (882:882:882))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1101:1101:1101) (1125:1125:1125))
        (PORT clk (1645:1645:1645) (1672:1672:1672))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1511:1511:1511) (1566:1566:1566))
        (PORT d[1] (1563:1563:1563) (1645:1645:1645))
        (PORT d[2] (1756:1756:1756) (1832:1832:1832))
        (PORT d[3] (1563:1563:1563) (1654:1654:1654))
        (PORT d[4] (1748:1748:1748) (1829:1829:1829))
        (PORT d[5] (1347:1347:1347) (1425:1425:1425))
        (PORT d[6] (1570:1570:1570) (1654:1654:1654))
        (PORT d[7] (2007:2007:2007) (2072:2072:2072))
        (PORT d[8] (1848:1848:1848) (1916:1916:1916))
        (PORT d[9] (1861:1861:1861) (1952:1952:1952))
        (PORT d[10] (1317:1317:1317) (1412:1412:1412))
        (PORT d[11] (1983:1983:1983) (2040:2040:2040))
        (PORT d[12] (1654:1654:1654) (1743:1743:1743))
        (PORT clk (1642:1642:1642) (1670:1670:1670))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1645:1645:1645) (1672:1672:1672))
        (PORT d[0] (992:992:992) (964:964:964))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1673:1673:1673))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1609:1609:1609) (1636:1636:1636))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (880:880:880) (883:883:883))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (881:881:881) (884:884:884))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (881:881:881) (884:884:884))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (881:881:881) (884:884:884))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~14)
    (DELAY
      (ABSOLUTE
        (PORT dataa (835:835:835) (814:814:814))
        (PORT datab (270:270:270) (353:353:353))
        (PORT datac (1396:1396:1396) (1469:1469:1469))
        (PORT datad (1345:1345:1345) (1353:1353:1353))
        (IOPATH dataa combout (307:307:307) (280:280:280))
        (IOPATH datab combout (308:308:308) (285:285:285))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (3071:3071:3071) (3114:3114:3114))
        (PORT clk (1646:1646:1646) (1674:1674:1674))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1268:1268:1268) (1320:1320:1320))
        (PORT d[1] (1217:1217:1217) (1285:1285:1285))
        (PORT d[2] (1440:1440:1440) (1483:1483:1483))
        (PORT d[3] (1589:1589:1589) (1675:1675:1675))
        (PORT d[4] (1257:1257:1257) (1328:1328:1328))
        (PORT d[5] (1355:1355:1355) (1427:1427:1427))
        (PORT d[6] (1522:1522:1522) (1581:1581:1581))
        (PORT d[7] (1484:1484:1484) (1521:1521:1521))
        (PORT d[8] (1280:1280:1280) (1341:1341:1341))
        (PORT d[9] (1290:1290:1290) (1357:1357:1357))
        (PORT d[10] (1282:1282:1282) (1367:1367:1367))
        (PORT d[11] (1462:1462:1462) (1504:1504:1504))
        (PORT d[12] (1654:1654:1654) (1743:1743:1743))
        (PORT clk (1643:1643:1643) (1672:1672:1672))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1674:1674:1674))
        (PORT d[0] (1035:1035:1035) (1000:1000:1000))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1675:1675:1675))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1675:1675:1675))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1675:1675:1675))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1675:1675:1675))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1610:1610:1610) (1638:1638:1638))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (881:881:881) (885:885:885))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (882:882:882) (886:886:886))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (882:882:882) (886:886:886))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (882:882:882) (886:886:886))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (2260:2260:2260) (2262:2262:2262))
        (PORT clk (1646:1646:1646) (1673:1673:1673))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1223:1223:1223) (1262:1262:1262))
        (PORT d[1] (1223:1223:1223) (1276:1276:1276))
        (PORT d[2] (1236:1236:1236) (1281:1281:1281))
        (PORT d[3] (1314:1314:1314) (1349:1349:1349))
        (PORT d[4] (1450:1450:1450) (1495:1495:1495))
        (PORT d[5] (1199:1199:1199) (1232:1232:1232))
        (PORT d[6] (1196:1196:1196) (1242:1242:1242))
        (PORT d[7] (1387:1387:1387) (1415:1415:1415))
        (PORT d[8] (1235:1235:1235) (1279:1279:1279))
        (PORT d[9] (1257:1257:1257) (1296:1296:1296))
        (PORT d[10] (1230:1230:1230) (1275:1275:1275))
        (PORT d[11] (1271:1271:1271) (1306:1306:1306))
        (PORT d[12] (1240:1240:1240) (1279:1279:1279))
        (PORT clk (1643:1643:1643) (1671:1671:1671))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (169:169:169))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1646:1646:1646) (1673:1673:1673))
        (PORT d[0] (925:925:925) (882:882:882))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1674:1674:1674))
        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1674:1674:1674))
        (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1674:1674:1674))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1647:1647:1647) (1674:1674:1674))
        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1610:1610:1610) (1637:1637:1637))
        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (42:42:42))
      (HOLD d (posedge clk) (142:142:142))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_register")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (881:881:881) (884:884:884))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (882:882:882) (885:885:885))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (882:882:882) (885:885:885))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_ram_pulse_generator")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (882:882:882) (885:885:885))
        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~15)
    (DELAY
      (ABSOLUTE
        (PORT dataa (183:183:183) (220:220:220))
        (PORT datab (271:271:271) (357:357:357))
        (PORT datac (1078:1078:1078) (1062:1062:1062))
        (PORT datad (998:998:998) (968:968:968))
        (IOPATH dataa combout (318:318:318) (307:307:307))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[0\]\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (877:877:877) (865:865:865))
        (PORT datac (654:654:654) (711:711:711))
        (PORT datad (598:598:598) (588:588:588))
        (IOPATH dataa combout (307:307:307) (306:306:306))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[1\]\~1)
    (DELAY
      (ABSOLUTE
        (PORT datab (937:937:937) (1015:1015:1015))
        (PORT datac (570:570:570) (553:553:553))
        (PORT datad (318:318:318) (317:317:317))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[2\]\~2)
    (DELAY
      (ABSOLUTE
        (PORT dataa (910:910:910) (902:902:902))
        (PORT datab (938:938:938) (1009:1009:1009))
        (PORT datad (1400:1400:1400) (1445:1445:1445))
        (IOPATH dataa combout (318:318:318) (307:307:307))
        (IOPATH datab combout (336:336:336) (337:337:337))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[3\]\~3)
    (DELAY
      (ABSOLUTE
        (PORT datab (937:937:937) (1015:1015:1015))
        (PORT datac (594:594:594) (599:599:599))
        (PORT datad (597:597:597) (586:586:586))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[4\]\~4)
    (DELAY
      (ABSOLUTE
        (PORT datab (940:940:940) (1012:1012:1012))
        (PORT datac (1222:1222:1222) (1191:1191:1191))
        (PORT datad (581:581:581) (581:581:581))
        (IOPATH datab combout (325:325:325) (332:332:332))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[5\]\~5)
    (DELAY
      (ABSOLUTE
        (PORT datab (614:614:614) (614:614:614))
        (PORT datac (913:913:913) (984:984:984))
        (PORT datad (605:605:605) (608:608:608))
        (IOPATH datab combout (308:308:308) (300:300:300))
        (IOPATH datac combout (220:220:220) (215:215:215))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[6\]\~6)
    (DELAY
      (ABSOLUTE
        (PORT datab (1846:1846:1846) (1889:1889:1889))
        (PORT datac (589:589:589) (596:596:596))
        (PORT datad (319:319:319) (318:318:318))
        (IOPATH datab combout (308:308:308) (300:300:300))
        (IOPATH datac combout (220:220:220) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE ram0\|altsyncram_component\|auto_generated\|mux5\|result_node\[7\]\~7)
    (DELAY
      (ABSOLUTE
        (PORT dataa (862:862:862) (868:868:868))
        (PORT datac (908:908:908) (977:977:977))
        (PORT datad (1020:1020:1020) (1011:1011:1011))
        (IOPATH dataa combout (318:318:318) (323:323:323))
        (IOPATH datac combout (218:218:218) (216:216:216))
        (IOPATH datad combout (119:119:119) (106:106:106))
      )
    )
  )
)