93 lines
3.8 KiB
Verilog
93 lines
3.8 KiB
Verilog
|
//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=50 clk0_duty_cycle=50 clk0_multiply_by=133 clk0_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=pll_sdram" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
|
||
|
|
//VERSION_BEGIN 13.1 cbx_altclkbuf 2013:10:17:09:48:19:SJ cbx_altiobuf_bidir 2013:10:17:09:48:19:SJ cbx_altiobuf_in 2013:10:17:09:48:19:SJ cbx_altiobuf_out 2013:10:17:09:48:19:SJ cbx_altpll 2013:10:17:09:48:19:SJ cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_counter 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ cbx_stratixiii 2013:10:17:09:48:19:SJ cbx_stratixv 2013:10:17:09:48:19:SJ cbx_util_mgl 2013:10:17:09:48:19:SJ VERSION_END
|
||
|
|
//CBXI_INSTANCE_NAME="spectrum_pll_sdram_sdram_clocks_altpll_altpll_component"
|
||
|
|
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
|
||
|
|
// altera message_off 10463
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
// Copyright (C) 1991-2013 Altera Corporation
|
||
|
|
// Your use of Altera Corporation's design tools, logic functions
|
||
|
|
// and other software and tools, and its AMPP partner logic
|
||
|
|
// functions, and any output files from any of the foregoing
|
||
|
|
// (including device programming or simulation files), and any
|
||
|
|
// associated documentation or information are expressly subject
|
||
|
|
// to the terms and conditions of the Altera Program License
|
||
|
|
// Subscription Agreement, Altera MegaCore Function License
|
||
|
|
// Agreement, or other applicable license agreement, including,
|
||
|
|
// without limitation, that your use is for the sole purpose of
|
||
|
|
// programming logic devices manufactured by Altera and sold by
|
||
|
|
// Altera or its authorized distributors. Please refer to the
|
||
|
|
// applicable agreement for further details.
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
//synthesis_resources = cycloneive_pll 1
|
||
|
|
//synopsys translate_off
|
||
|
|
`timescale 1 ps / 1 ps
|
||
|
|
//synopsys translate_on
|
||
|
|
module pll_sdram_altpll
|
||
|
|
(
|
||
|
|
clk,
|
||
|
|
inclk) /* synthesis synthesis_clearbox=1 */;
|
||
|
|
output [4:0] clk;
|
||
|
|
input [1:0] inclk;
|
||
|
|
`ifndef ALTERA_RESERVED_QIS
|
||
|
|
// synopsys translate_off
|
||
|
|
`endif
|
||
|
|
tri0 [1:0] inclk;
|
||
|
|
`ifndef ALTERA_RESERVED_QIS
|
||
|
|
// synopsys translate_on
|
||
|
|
`endif
|
||
|
|
|
||
|
|
wire [4:0] wire_pll1_clk;
|
||
|
|
wire wire_pll1_fbout;
|
||
|
|
|
||
|
|
cycloneive_pll pll1
|
||
|
|
(
|
||
|
|
.activeclock(),
|
||
|
|
.clk(wire_pll1_clk),
|
||
|
|
.clkbad(),
|
||
|
|
.fbin(wire_pll1_fbout),
|
||
|
|
.fbout(wire_pll1_fbout),
|
||
|
|
.inclk(inclk),
|
||
|
|
.locked(),
|
||
|
|
.phasedone(),
|
||
|
|
.scandataout(),
|
||
|
|
.scandone(),
|
||
|
|
.vcooverrange(),
|
||
|
|
.vcounderrange()
|
||
|
|
`ifndef FORMAL_VERIFICATION
|
||
|
|
// synopsys translate_off
|
||
|
|
`endif
|
||
|
|
,
|
||
|
|
.areset(1'b0),
|
||
|
|
.clkswitch(1'b0),
|
||
|
|
.configupdate(1'b0),
|
||
|
|
.pfdena(1'b1),
|
||
|
|
.phasecounterselect({3{1'b0}}),
|
||
|
|
.phasestep(1'b0),
|
||
|
|
.phaseupdown(1'b0),
|
||
|
|
.scanclk(1'b0),
|
||
|
|
.scanclkena(1'b1),
|
||
|
|
.scandata(1'b0)
|
||
|
|
`ifndef FORMAL_VERIFICATION
|
||
|
|
// synopsys translate_on
|
||
|
|
`endif
|
||
|
|
);
|
||
|
|
defparam
|
||
|
|
pll1.bandwidth_type = "auto",
|
||
|
|
pll1.clk0_divide_by = 50,
|
||
|
|
pll1.clk0_duty_cycle = 50,
|
||
|
|
pll1.clk0_multiply_by = 133,
|
||
|
|
pll1.clk0_phase_shift = "0",
|
||
|
|
pll1.compensate_clock = "clk0",
|
||
|
|
pll1.inclk0_input_frequency = 20000,
|
||
|
|
pll1.operation_mode = "normal",
|
||
|
|
pll1.pll_type = "auto",
|
||
|
|
pll1.lpm_type = "cycloneive_pll";
|
||
|
|
assign
|
||
|
|
clk = {wire_pll1_clk[4:0]};
|
||
|
|
endmodule //pll_sdram_altpll
|
||
|
|
//VALID FILE
|