104 lines
9.9 KiB
Plaintext
104 lines
9.9 KiB
Plaintext
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--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_SIZE=6 LPM_WIDTH=8 LPM_WIDTHS=3 data result sel
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--VERSION_BEGIN 13.1 cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ VERSION_END
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-- Copyright (C) 1991-2013 Altera Corporation
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, Altera MegaCore Function License
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-- Agreement, or other applicable license agreement, including,
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-- without limitation, that your use is for the sole purpose of
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-- programming logic devices manufactured by Altera and sold by
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-- Altera or its authorized distributors. Please refer to the
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-- applicable agreement for further details.
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--synthesis_resources = lut 40
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SUBDESIGN mux_9nb
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(
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data[47..0] : input;
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result[7..0] : output;
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sel[2..0] : input;
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)
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VARIABLE
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result_node[7..0] : WIRE;
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sel_ffs_wire[2..0] : WIRE;
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sel_node[2..0] : WIRE;
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w_data1001w[3..0] : WIRE;
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w_data1002w[3..0] : WIRE;
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w_data1048w[7..0] : WIRE;
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w_data1068w[3..0] : WIRE;
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w_data1069w[3..0] : WIRE;
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w_data1115w[7..0] : WIRE;
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w_data1135w[3..0] : WIRE;
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w_data1136w[3..0] : WIRE;
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w_data1182w[7..0] : WIRE;
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w_data1202w[3..0] : WIRE;
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w_data1203w[3..0] : WIRE;
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w_data1249w[7..0] : WIRE;
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w_data1269w[3..0] : WIRE;
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w_data1270w[3..0] : WIRE;
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w_data1316w[7..0] : WIRE;
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w_data1336w[3..0] : WIRE;
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w_data1337w[3..0] : WIRE;
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w_data845w[7..0] : WIRE;
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w_data865w[3..0] : WIRE;
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w_data866w[3..0] : WIRE;
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w_data914w[7..0] : WIRE;
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w_data934w[3..0] : WIRE;
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w_data935w[3..0] : WIRE;
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w_data981w[7..0] : WIRE;
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w_sel1003w[1..0] : WIRE;
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w_sel1070w[1..0] : WIRE;
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w_sel1137w[1..0] : WIRE;
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w_sel1204w[1..0] : WIRE;
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w_sel1271w[1..0] : WIRE;
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w_sel1338w[1..0] : WIRE;
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w_sel867w[1..0] : WIRE;
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w_sel936w[1..0] : WIRE;
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BEGIN
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result[] = result_node[];
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result_node[] = ( ((sel_node[2..2] & (((w_data1337w[1..1] & w_sel1338w[0..0]) & (! (((w_data1337w[0..0] & (! w_sel1338w[1..1])) & (! w_sel1338w[0..0])) # (w_sel1338w[1..1] & (w_sel1338w[0..0] # w_data1337w[2..2]))))) # ((((w_data1337w[0..0] & (! w_sel1338w[1..1])) & (! w_sel1338w[0..0])) # (w_sel1338w[1..1] & (w_sel1338w[0..0] # w_data1337w[2..2]))) & (w_data1337w[3..3] # (! w_sel1338w[0..0]))))) # ((! sel_node[2..2]) & (((w_data1336w[1..1] & w_sel1338w[0..0]) & (! (((w_data1336w[0..0] & (! w_sel1338w[1..1])) & (! w_sel1338w[0..0])) # (w_sel1338w[1..1] & (w_sel1338w[0..0] # w_data1336w[2..2]))))) # ((((w_data1336w[0..0] & (! w_sel1338w[1..1])) & (! w_sel1338w[0..0])) # (w_sel1338w[1..1] & (w_sel1338w[0..0] # w_data1336w[2..2]))) & (w_data1336w[3..3] # (! w_sel1338w[0..0])))))), ((sel_node[2..2] & (((w_data1270w[1..1] & w_sel1271w[0..0]) & (! (((w_data1270w[0..0] & (! w_sel1271w[1..1])) & (! w_sel1271w[0..0])) # (w_sel1271w[1..1] & (w_sel1271w[0..0] # w_data1270w[2..2]))))) # ((((w_data1270w[0..0] & (! w_sel1271w[1..1])) & (! w_sel1271w[0..0])) # (w_sel1271w[1..1] & (w_sel1271w[0..0] # w_data1270w[2..2]))) & (w_data1270w[3..3] # (! w_sel1271w[0..0]))))) # ((! sel_node[2..2]) & (((w_data1269w[1..1] & w_sel1271w[0..0]) & (! (((w_data1269w[0..0] & (! w_sel1271w[1..1])) & (! w_sel1271w[0..0])) # (w_sel1271w[1..1] & (w_sel1271w[0..0] # w_data1269w[2..2]))))) # ((((w_data1269w[0..0] & (! w_sel1271w[1..1])) & (! w_sel1271w[0..0])) # (w_sel1271w[1..1] & (w_sel1271w[0..0] # w_data1269w[2..2]))) & (w_data1269w[3..3] # (! w_sel1271w[0..0])))))), ((sel_node[2..2] & (((w_data1203w[1..1] & w_sel1204w[0..0]) & (! (((w_data1203w[0..0] & (! w_sel1204w[1..1])) & (! w_sel1204w[0..0])) # (w_sel1204w[1..1] & (w_sel1204w[0..0] # w_data1203w[2..2]))))) # ((((w_data1203w[0..0] & (! w_sel1204w[1..1])) & (! w_sel1204w[0..0])) # (w_sel1204w[1..1] & (w_sel1204w[0..0] # w_data1203w[2..2]))) & (w_data1203w[3..3] # (! w_sel1204w[0..0]))))) # ((! sel_node[2..2]) & (((w_data1202w[1..1] & w_sel1204w[0..0]) & (! (((w_data1202w[0..0] & (! w_sel1204w[1..1])) & (! w_sel1204w[0..0])) # (w_sel1204w[1..1] & (w_sel1204w[0..0] # w_data1202w[2..2]))))) # ((((w_data1202w[0..0] & (! w_sel1204w[1..1])) & (! w_sel1204w[0..0])) # (w_sel1204w[1..1] & (w_sel1204w[0..0] # w_data1202w[2..2]))) & (w_data1202w[3..3] # (! w_sel1204w[0..0])))))), ((sel_node[2..2] & (((w_data1136w[1..1] & w_sel1137w[0..0]) & (! (((w_data1136w[0..0] & (! w_sel1137w[1..1])) & (! w_sel1137w[0..0])) # (w_sel1137w[1..1] & (w_sel1137w[0..0] # w_data1136w[2..2]))))) # ((((w_data1136w[0..0] & (! w_sel1137w[1..1])) & (! w_sel1137w[0..0])) # (w_sel1137w[1..1] & (w_sel1137w[0..0] # w_data1136w[2..2]))) & (w_data1136w[3..3] # (! w_sel1137w[0..0]))))) # ((! sel_node[2..2]) & (((w_data1135w[1..1] & w_sel1137w[0..0]) & (! (((w_data1135w[0..0] & (! w_sel1137w[1..1])) & (! w_sel1137w[0..0])) # (w_sel1137w[1..1] & (w_sel1137w[0..0] # w_data1135w[2..2]))))) # ((((w_data1135w[0..0] & (! w_sel1137w[1..1])) & (! w_sel1137w[0..0])) # (w_sel1137w[1..1] & (w_sel1137w[0..0] # w_data1135w[2..2]))) & (w_data1135w[3..3] # (! w_sel1137w[0..0])))))), ((sel_node[2..2] & (((w_data1069w[1..1] & w_sel1070w[0..0]) & (! (((w_data1069w[0..0] & (! w_sel1070w[1..1])) & (! w_sel1070w[0..0])) # (w_sel1070w[1..1] & (w_sel1070w[0..0] # w_data1069w[2..2]))))) # ((((w_data1069w[0..0] & (! w_sel1070w[1..1])) & (! w_sel1070w[0..0])) # (w_sel1070w[1..1] & (w_sel1070w[0..0] # w_data1069w[2..2]))) & (w_data1069w[3..3] # (! w_sel1070w[0..0]))))) # ((! sel_node[2..2]) & (((w_data1068w[1..1] & w_sel1070w[0..0]) & (! (((w_data1068w[0..0] & (! w_sel1070w[1..1])) & (! w_sel1070w[0..0])) # (w_sel1070w[1..1] & (w_sel1070w[0..0] # w_data1068w[2..2]))))) # ((((w_data1068w[0..0] & (! w_sel1070w[1..1])) & (! w_sel1070w[0..0])) # (w_sel1070w[1..1] & (w_sel1070w[0..0] # w_data1068w[2..2]))) & (w_data1068w[3..3] # (! w_sel1070w[0..0])))))), ((sel_node[2..2] & (((w_data1002w[1..1] & w_sel1003w[0..0]) & (! (((w_data1002w[0..0] & (! w_sel1003w[1..1])) & (! w_sel1003w[0..0])) # (w_sel1003w[1..1] & (w_sel1003w[0..0] # w_data1002w[2..2]))))) # ((((w_data1002w[0..0
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sel_ffs_wire[] = ( sel[2..0]);
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sel_node[] = ( sel_ffs_wire[2..2], sel[1..0]);
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w_data1001w[3..0] = w_data981w[3..0];
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w_data1002w[3..0] = w_data981w[7..4];
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w_data1048w[] = ( B"00", data[43..43], data[35..35], data[27..27], data[19..19], data[11..11], data[3..3]);
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w_data1068w[3..0] = w_data1048w[3..0];
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w_data1069w[3..0] = w_data1048w[7..4];
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w_data1115w[] = ( B"00", data[44..44], data[36..36], data[28..28], data[20..20], data[12..12], data[4..4]);
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w_data1135w[3..0] = w_data1115w[3..0];
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w_data1136w[3..0] = w_data1115w[7..4];
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w_data1182w[] = ( B"00", data[45..45], data[37..37], data[29..29], data[21..21], data[13..13], data[5..5]);
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w_data1202w[3..0] = w_data1182w[3..0];
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w_data1203w[3..0] = w_data1182w[7..4];
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w_data1249w[] = ( B"00", data[46..46], data[38..38], data[30..30], data[22..22], data[14..14], data[6..6]);
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w_data1269w[3..0] = w_data1249w[3..0];
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w_data1270w[3..0] = w_data1249w[7..4];
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w_data1316w[] = ( B"00", data[47..47], data[39..39], data[31..31], data[23..23], data[15..15], data[7..7]);
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w_data1336w[3..0] = w_data1316w[3..0];
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w_data1337w[3..0] = w_data1316w[7..4];
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w_data845w[] = ( B"00", data[40..40], data[32..32], data[24..24], data[16..16], data[8..8], data[0..0]);
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w_data865w[3..0] = w_data845w[3..0];
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w_data866w[3..0] = w_data845w[7..4];
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w_data914w[] = ( B"00", data[41..41], data[33..33], data[25..25], data[17..17], data[9..9], data[1..1]);
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w_data934w[3..0] = w_data914w[3..0];
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w_data935w[3..0] = w_data914w[7..4];
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w_data981w[] = ( B"00", data[42..42], data[34..34], data[26..26], data[18..18], data[10..10], data[2..2]);
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w_sel1003w[1..0] = sel_node[1..0];
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w_sel1070w[1..0] = sel_node[1..0];
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w_sel1137w[1..0] = sel_node[1..0];
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w_sel1204w[1..0] = sel_node[1..0];
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w_sel1271w[1..0] = sel_node[1..0];
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w_sel1338w[1..0] = sel_node[1..0];
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w_sel867w[1..0] = sel_node[1..0];
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w_sel936w[1..0] = sel_node[1..0];
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END;
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--VALID FILE
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