55 lines
3.0 KiB
Plaintext
55 lines
3.0 KiB
Plaintext
|
--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_DECODES=6 LPM_WIDTH=3 data eq
|
||
|
|
--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ VERSION_END
|
||
|
|
|
||
|
|
|
||
|
|
-- Copyright (C) 1991-2013 Altera Corporation
|
||
|
|
-- Your use of Altera Corporation's design tools, logic functions
|
||
|
|
-- and other software and tools, and its AMPP partner logic
|
||
|
|
-- functions, and any output files from any of the foregoing
|
||
|
|
-- (including device programming or simulation files), and any
|
||
|
|
-- associated documentation or information are expressly subject
|
||
|
|
-- to the terms and conditions of the Altera Program License
|
||
|
|
-- Subscription Agreement, Altera MegaCore Function License
|
||
|
|
-- Agreement, or other applicable license agreement, including,
|
||
|
|
-- without limitation, that your use is for the sole purpose of
|
||
|
|
-- programming logic devices manufactured by Altera and sold by
|
||
|
|
-- Altera or its authorized distributors. Please refer to the
|
||
|
|
-- applicable agreement for further details.
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
--synthesis_resources = lut 8
|
||
|
|
SUBDESIGN decode_i8a
|
||
|
|
(
|
||
|
|
data[2..0] : input;
|
||
|
|
eq[5..0] : output;
|
||
|
|
)
|
||
|
|
VARIABLE
|
||
|
|
data_wire[2..0] : WIRE;
|
||
|
|
eq_node[5..0] : WIRE;
|
||
|
|
eq_wire[7..0] : WIRE;
|
||
|
|
w_anode741w[3..0] : WIRE;
|
||
|
|
w_anode759w[3..0] : WIRE;
|
||
|
|
w_anode770w[3..0] : WIRE;
|
||
|
|
w_anode781w[3..0] : WIRE;
|
||
|
|
w_anode792w[3..0] : WIRE;
|
||
|
|
w_anode803w[3..0] : WIRE;
|
||
|
|
w_anode814w[3..0] : WIRE;
|
||
|
|
w_anode825w[3..0] : WIRE;
|
||
|
|
|
||
|
|
BEGIN
|
||
|
|
data_wire[] = data[];
|
||
|
|
eq[] = eq_node[];
|
||
|
|
eq_node[5..0] = eq_wire[5..0];
|
||
|
|
eq_wire[] = ( w_anode825w[3..3], w_anode814w[3..3], w_anode803w[3..3], w_anode792w[3..3], w_anode781w[3..3], w_anode770w[3..3], w_anode759w[3..3], w_anode741w[3..3]);
|
||
|
|
w_anode741w[] = ( (w_anode741w[2..2] & (! data_wire[2..2])), (w_anode741w[1..1] & (! data_wire[1..1])), (w_anode741w[0..0] & (! data_wire[0..0])), B"1");
|
||
|
|
w_anode759w[] = ( (w_anode759w[2..2] & (! data_wire[2..2])), (w_anode759w[1..1] & (! data_wire[1..1])), (w_anode759w[0..0] & data_wire[0..0]), B"1");
|
||
|
|
w_anode770w[] = ( (w_anode770w[2..2] & (! data_wire[2..2])), (w_anode770w[1..1] & data_wire[1..1]), (w_anode770w[0..0] & (! data_wire[0..0])), B"1");
|
||
|
|
w_anode781w[] = ( (w_anode781w[2..2] & (! data_wire[2..2])), (w_anode781w[1..1] & data_wire[1..1]), (w_anode781w[0..0] & data_wire[0..0]), B"1");
|
||
|
|
w_anode792w[] = ( (w_anode792w[2..2] & data_wire[2..2]), (w_anode792w[1..1] & (! data_wire[1..1])), (w_anode792w[0..0] & (! data_wire[0..0])), B"1");
|
||
|
|
w_anode803w[] = ( (w_anode803w[2..2] & data_wire[2..2]), (w_anode803w[1..1] & (! data_wire[1..1])), (w_anode803w[0..0] & data_wire[0..0]), B"1");
|
||
|
|
w_anode814w[] = ( (w_anode814w[2..2] & data_wire[2..2]), (w_anode814w[1..1] & data_wire[1..1]), (w_anode814w[0..0] & (! data_wire[0..0])), B"1");
|
||
|
|
w_anode825w[] = ( (w_anode825w[2..2] & data_wire[2..2]), (w_anode825w[1..1] & data_wire[1..1]), (w_anode825w[0..0] & data_wire[0..0]), B"1");
|
||
|
|
END;
|
||
|
|
--VALID FILE
|