42 lines
1.8 KiB
Plaintext
42 lines
1.8 KiB
Plaintext
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--lpm_compare CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_WIDTH=4 ONE_INPUT_IS_CONSTANT="YES" aeb dataa datab
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--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ VERSION_END
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-- Copyright (C) 1991-2013 Altera Corporation
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, Altera MegaCore Function License
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-- Agreement, or other applicable license agreement, including,
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-- without limitation, that your use is for the sole purpose of
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-- programming logic devices manufactured by Altera and sold by
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-- Altera or its authorized distributors. Please refer to the
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-- applicable agreement for further details.
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--synthesis_resources =
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SUBDESIGN cmpr_qgc
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(
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aeb : output;
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dataa[3..0] : input;
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datab[3..0] : input;
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)
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VARIABLE
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aeb_result_wire[0..0] : WIRE;
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aneb_result_wire[0..0] : WIRE;
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data_wire[9..0] : WIRE;
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eq_wire : WIRE;
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BEGIN
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aeb = eq_wire;
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aeb_result_wire[] = (! aneb_result_wire[]);
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aneb_result_wire[] = (data_wire[0..0] # data_wire[1..1]);
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data_wire[] = ( datab[3..3], dataa[3..3], datab[2..2], dataa[2..2], datab[1..1], dataa[1..1], datab[0..0], dataa[0..0], ((data_wire[6..6] $ data_wire[7..7]) # (data_wire[8..8] $ data_wire[9..9])), ((data_wire[2..2] $ data_wire[3..3]) # (data_wire[4..4] $ data_wire[5..5])));
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eq_wire = aeb_result_wire[];
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END;
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--VALID FILE
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