36 lines
1.3 KiB
Systemverilog
36 lines
1.3 KiB
Systemverilog
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//============================================================================
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// Z80 Top level using the interface declaration
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//============================================================================
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`include "z80.svh"
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module z80_top_ifc_n (z80_if.dut z80);
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// Include core A-Z80 level connecting all internal modules
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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`include "core.vh"
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// Address, Data and Control bus drivers connecting to external pins
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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address_pins address_pins_( .*, .abus(z80.A[15:0]) );
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data_pins data_pins_ ( .*, .db(db0[7:0]), .D(z80.D[7:0]) );
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control_pins_n control_pins_( .*,
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.pin_nM1 (z80.nM1),
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.pin_nMREQ (z80.nMREQ),
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.pin_nIORQ (z80.nIORQ),
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.pin_nRD (z80.nRD),
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.pin_nWR (z80.nWR),
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.pin_nRFSH (z80.nRFSH),
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.pin_nHALT (z80.nHALT),
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.pin_nWAIT (z80.nWAIT),
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.pin_nBUSACK (z80.nBUSACK),
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.pin_nINT (z80.nINT),
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.pin_nNMI (z80.nNMI),
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.pin_nRESET (z80.nRESET),
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.pin_nBUSRQ (z80.nBUSRQ),
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.CPUCLK (z80.CLK)
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);
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endmodule
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