304 lines
12 KiB
Python
304 lines
12 KiB
Python
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#!/usr/bin/env python3
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#
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# This script generates a test include file from a set of "Fuse" test vectors.
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#
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# Three common testing configurations are:
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#
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# 1. You want to test a specific instruction only, say 02 LD (BC),A (see Fuse tests.in)
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# start_test = "02"
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# run_tests = 1
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# regress = 0
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#
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# 2. You want to run a smaller subset of 'regression' tests:
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# start_test = "00"
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# run_tests = 1
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# regress = 1
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#
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# 3. You want to run a full Fuse test suite (all instructions!):
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# start_test = "00"
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# run_tests = -1
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# regress = 0
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#
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# Orthogonal to that, set m1wait to a non-zero value to test nWAIT insertion at
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# the first M1 cycle of an instruction. Change it to the number of T-clocks to
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# insert.
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#
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#-------------------------------------------------------------------------------
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# Copyright (C) 2016 Goran Devic
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of the GNU General Public License as published by the Free
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# Software Foundation; either version 2 of the License, or (at your option)
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# any later version.
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#
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# This program is distributed in the hope that it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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# more details.
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#-------------------------------------------------------------------------------
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import os
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# Start with this test name (this is a string; see tests files)
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start_test = "00"
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# Number of tests to run; use -1 to run all tests
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run_tests = 1
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# Set this to 1 to use regression test instead of selected or full 'tests.*'
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# Regression test is a shorter set of tests and ignores start_test and run_tests values
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regress = 1
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# Set this to a number of WAIT cycles to add at M1 clock period or 0 not to test nWAIT
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m1wait = 0
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#------------------------------------------------------------------------------
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# Determine which test files to use
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tests_in = 'fuse/tests.in'
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tests_expected = 'fuse/tests.expected'
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# Regression testing executes all regression tests
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if regress:
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tests_in = 'fuse/regress.in'
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tests_expected = 'fuse/regress.expected'
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start_test = "00"
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run_tests = -1
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with open(tests_in) as f1:
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t1 = f1.read().splitlines()
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# Remove all tests until the one we need to start with. Tests are separated by empty lines.
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while t1[0].split(" ")[0]!=start_test:
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while len(t1.pop(0))>0:
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pass
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t1 = list(filter(None, t1)) # Filter out empty lines
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with open(tests_expected) as f2:
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t2 = f2.read().splitlines()
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while t2[0].split(" ")[0]!=start_test:
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while len(t2.pop(0))>0:
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pass
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# Count total clocks required to run all selected tests
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total_clks = 0
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def RegWrite(reg, hex):
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global total_clks
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ftest.write(" // Preset " + reg + "\n")
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ftest.write(" force dut.reg_file_.b2v_latch_" + reg + "_lo.we=1;\n")
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ftest.write(" force dut.reg_file_.b2v_latch_" + reg + "_hi.we=1;\n")
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ftest.write(" force dut.reg_file_.b2v_latch_" + reg + "_lo.db=8'h" + hex[2:] + ";\n")
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ftest.write(" force dut.reg_file_.b2v_latch_" + reg + "_hi.db=8'h" + hex[0:2] + ";\n")
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ftest.write("#2 release dut.reg_file_.b2v_latch_" + reg + "_lo.we;\n")
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ftest.write(" release dut.reg_file_.b2v_latch_" + reg + "_hi.we;\n")
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ftest.write(" release dut.reg_file_.b2v_latch_" + reg + "_lo.db;\n")
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ftest.write(" release dut.reg_file_.b2v_latch_" + reg + "_hi.db;\n")
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total_clks = total_clks + 2
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def RegRead(reg, hex):
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ftest.write(" if (dut.reg_file_.b2v_latch_" + reg + "_lo.latch!==8'h" + hex[2:] + ") $fdisplay(f,\"* Reg " + reg + " " + reg[1] + "=%h !=" + hex[2:] + "\",dut.reg_file_.b2v_latch_" + reg + "_lo.latch);\n")
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ftest.write(" if (dut.reg_file_.b2v_latch_" + reg + "_hi.latch!==8'h" + hex[0:2] + ") $fdisplay(f,\"* Reg " + reg + " " + reg[0] + "=%h !=" + hex[0:2] + "\",dut.reg_file_.b2v_latch_" + reg + "_hi.latch);\n")
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#---------------------------- START -----------------------------------
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# Create a file that should be included in the test_fuse source
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ftest = open('test_fuse.vh', 'w')
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ftest.write("// Automatically generated by genfuse.py\n\n")
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# Initial pre-test state is reset and control signals asserted
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ftest.write("force dut.resets_.clrpc=0;\n")
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ftest.write("force dut.reg_file_.reg_gp_we=0;\n")
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ftest.write("force dut.reg_control_.ctl_reg_sys_we=0;\n")
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ftest.write("force dut.z80_top_ifc_n.fpga_reset=1;\n")
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ftest.write("#2 // Start test loop\n\n")
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total_clks = total_clks + 2
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# Read each test from the testdat.in file
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while True:
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if len(t1)==0 or run_tests==0:
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break
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run_tests = run_tests-1
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# Clear opcode register before starting a new instruction
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ftest.write(" force dut.ir_.ctl_ir_we=1;\n")
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ftest.write(" force dut.ir_.db=0;\n")
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ftest.write("#2 release dut.ir_.ctl_ir_we;\n")
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ftest.write(" release dut.ir_.db;\n")
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total_clks = total_clks + 2
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# Format of the test.in file:
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# <arbitrary test description>
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# AF BC DE HL AF' BC' DE' HL' IX IY SP PC
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# I R IFF1 IFF2 IM <halted> <tstates>
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name = t1.pop(0)
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ftest.write(" $fdisplay(f,\"Testing opcode " + name + "\");\n")
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name = name.split(" ")[0]
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r = t1.pop(0).split(' ')
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r = list(filter(None, r))
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# 0 1 2 3 4 5 6 7 8 9 10 11 (index)
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# AF BC DE HL AF' BC' DE' HL' IX IY SP PC
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RegWrite("af", r[0])
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RegWrite("bc", r[1])
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RegWrite("de", r[2])
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RegWrite("hl", r[3])
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RegWrite("af2", r[4])
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RegWrite("bc2", r[5])
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RegWrite("de2", r[6])
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RegWrite("hl2", r[7])
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RegWrite("ix", r[8])
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RegWrite("iy", r[9])
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RegWrite("sp", r[10])
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RegWrite("wz", "0000") # Initialize WZ with 0
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RegWrite("pc", r[11])
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s = t1.pop(0).split(' ')
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s = list(filter(None, s))
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# 0 1 2 3 4 5 6 (index)
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# I R IFF1 IFF2 IM <halted> <tstates?>
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RegWrite("ir", s[0]+s[1])
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# TODO: Store IFF1/IFF2, IM, in_halt
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# Read memory configuration from the test.in until the line contains only -1
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while True:
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m = t1.pop(0).split(' ')
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if m[0]=="-1":
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break
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address = int(m.pop(0),16)
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ftest.write(" // Preset memory\n")
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while True:
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d = m.pop(0)
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if d=="-1":
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break
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ftest.write(" ram.Mem[" + str(address) + "] = 8'h" + d + ";\n")
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address = address+1
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# We need to prepare the IO map to be able to handle IN/OUT instructions.
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# Copy tests.out (so we don't modify it just yet), parse all PR and PW (port read, write)
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# statements and then fill in our IO map (for IO reads) or stack the check statements to be
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# used below after the opcode has executed (for IO writes)
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check_io = [] # List of check statements (for OUT instructions)
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t2b = list(t2)
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while True:
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m = t2b.pop(0).split(' ')
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m = list(filter(None, m))
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if len(m)==0 or m[0]=="-1":
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break
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if len(m)==4 and m[1]=="PR":
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address = int(m[2],16)
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ftest.write(" io.IO[" + str(address) + "] = 8'h" + m[3] + ";\n")
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if len(m)==4 and m[1]=="PW":
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address = int(m[2],16)
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check_io.append(" if (io.IO[" + str(address) + "]!==8'h" + m[3] + ") $fdisplay(f,\"* IO[" + hex(address)[2:] + "]=%h !=" + m[3] + "\",io.IO[" + str(address) + "]);\n")
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# Prepare instruction to be run. By releasing the fpga_reset, internal CPU reset will be active for 1T.
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# Due to the instruction execution overlap, first 2T of an instruction may be writing
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# value back to a general purpose register (like AF) and we need to prevent that.
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# Similarly, we let the execution continues 2T into the next instruction but we prevent
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# it from writing to system registers so it cannot update PC and IR.
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ftest.write(" force dut.z80_top_ifc_n.fpga_reset=0;\n")
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ftest.write(" force dut.address_latch_.Q=16'h" + r[11] +";\n") # Force PC into the address latch
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ftest.write(" release dut.reg_control_.ctl_reg_sys_we;\n")
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ftest.write(" release dut.reg_file_.reg_gp_we;\n")
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ftest.write("#2 // Execute: M1/T1 start\n") # 1T (#2) overlaps the reset cycle
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ftest.write("#1 release dut.address_latch_.Q;\n")
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total_clks = total_clks + 3 # We borrow 1T (#2) to to force the PC to be what our test wants...
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ftest.write("#1\n")
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total_clks = total_clks + 1
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# Read and parse the tests expected list which contains the expected results of our run,
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# including the number of clocks for a particular instruction
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xname = t2.pop(0).split()[0]
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if name!=xname:
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print("Test " + name + " does not correspond to test.expected " + xname)
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break
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# Skip the memory access logs; read to the expected register content list
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while True:
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l = t2.pop(0)
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if l[0]!=' ':
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break
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r = l.split(' ')
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r = list(filter(None, r))
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s = t2.pop(0).split(' ')
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s = list(filter(None, s))
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ticks = int(s[6]) * 2 - 2 # We return 1T (#2) that we borrowed to set PC
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total_clks = total_clks + ticks
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# Test WAIT state insertion at the M1 clock cycle
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if m1wait:
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ftest.write(" z.nWAIT <= 0;\n")
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ftest.write("#" + str(m1wait * 2) + " z.nWAIT <= 1; // nWAIT during M1\n")
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total_clks = total_clks + m1wait * 2
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ftest.write("#" + str(ticks) + " // Wait for opcode end\n")
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ftest.write(" force dut.reg_control_.ctl_reg_sys_we=0;\n")
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ftest.write("#2 pc=z.A;\n") # Extra 2T for the next instruction overlap & read PC on the ABus
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ftest.write("#2\n") # Complete this instruction
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ftest.write("#1 force dut.reg_file_.reg_gp_we=0;\n") # Add 1/2 clock for any pending flops to latch (mainly the F register)
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ftest.write(" force dut.z80_top_ifc_n.fpga_reset=1;\n")
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total_clks = total_clks + 5
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# Now we can issue register reading commands
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# We are guided on what to read and check by the content of "test.expected" file
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# Special case are the register exchange instructions and there are 3 of them.
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# The exchange operations are not tested directly; instead, the latches that control register bank access are
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if xname=="08": # EX AF,AF1
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r[0],r[4] = r[4],r[0]
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ftest.write(" if (dut.reg_control_.bank_af!==1) $fdisplay(f,\"* Bank AF!=1\");\n")
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if xname=="eb": # EX DE,HL
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r[2],r[3] = r[3],r[2]
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ftest.write(" if (dut.reg_control_.bank_hl_de1!==1) $fdisplay(f,\"* Bank HL/DE!=1\");\n")
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if xname=="d9": # EXX
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r[1],r[5] = r[5],r[1]
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r[2],r[6] = r[6],r[2]
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r[3],r[7] = r[7],r[3]
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ftest.write(" if (dut.reg_control_.bank_exx!==1) $fdisplay(f,\"* Bank EXX!=1\");\n")
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# Read the result: registers and memory
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# 0 1 2 3 4 5 6 7 8 9 10 11 (index)
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# AF BC DE HL AF' BC' DE' HL' IX IY SP PC
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RegRead("af", r[0])
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RegRead("bc", r[1])
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RegRead("de", r[2])
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RegRead("hl", r[3])
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RegRead("af2", r[4])
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RegRead("bc2", r[5])
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RegRead("de2", r[6])
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RegRead("hl2", r[7])
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RegRead("ix", r[8])
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RegRead("iy", r[9])
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RegRead("sp", r[10])
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#RegRead("pc", r[11]) Instead of PC, we read the address bus of the next instruction
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ftest.write(" if (pc!==16'h" + r[11] + ") $fdisplay(f,\"* PC=%h !=" + r[11] + "\",pc);\n")
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# 0 1 2 3 4 5 6 (index)
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# I R IFF1 IFF2 IM <halted> <tstates?>
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RegRead("ir", s[0]+s[1])
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# Read memory configuration until an empty line or -1 at the end
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while True:
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m = t2.pop(0).split(' ')
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m = list(filter(None, m))
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if len(m)==0 or m[0]=="-1":
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break
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address = int(m.pop(0),16)
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while True:
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d = m.pop(0)
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if d=="-1":
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break
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ftest.write(" if (ram.Mem[" + str(address) + "]!==8'h" + d + ") $fdisplay(f,\"* Mem[" + hex(address)[2:] + "]=%h !=" + d + "\",ram.Mem[" + str(address) + "]);\n")
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address = address+1
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# Read a list of IO checks that was compiled while parsing the initial condition
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while len(check_io)>0:
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ftest.write(check_io.pop(0))
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ftest.write("#1 // End opcode\n\n")
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total_clks = total_clks + 1
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# Write out the total number of clocks that this set of tests takes to execute
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ftest.write("`define TOTAL_CLKS " + str(total_clks) + "\n")
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ftest.write("$fdisplay(f,\"=== Tests completed ===\");\n")
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ftest.close()
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# Touch a file that includes 'test_fuse.vh' to ensure it will recompile correctly
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os.utime("test_fuse.sv", None)
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