90 lines
2.3 KiB
Verilog
90 lines
2.3 KiB
Verilog
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// Copyright (C) 1991-2013 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// CREATED "Sun Nov 16 21:18:37 2014"
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module pin_control(
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fFetch,
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fMRead,
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fMWrite,
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fIORead,
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fIOWrite,
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T1,
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T2,
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T3,
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T4,
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bus_ab_pin_we,
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bus_db_pin_oe,
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bus_db_pin_re
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);
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input wire fFetch;
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input wire fMRead;
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input wire fMWrite;
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input wire fIORead;
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input wire fIOWrite;
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input wire T1;
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input wire T2;
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input wire T3;
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input wire T4;
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output wire bus_ab_pin_we;
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output wire bus_db_pin_oe;
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output wire bus_db_pin_re;
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wire SYNTHESIZED_WIRE_0;
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wire SYNTHESIZED_WIRE_1;
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wire SYNTHESIZED_WIRE_2;
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wire SYNTHESIZED_WIRE_3;
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wire SYNTHESIZED_WIRE_4;
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wire SYNTHESIZED_WIRE_5;
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wire SYNTHESIZED_WIRE_6;
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wire SYNTHESIZED_WIRE_7;
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wire SYNTHESIZED_WIRE_8;
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wire SYNTHESIZED_WIRE_9;
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assign SYNTHESIZED_WIRE_9 = fFetch | fMWrite | fMRead | fIORead | fIOWrite | fIOWrite;
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assign SYNTHESIZED_WIRE_7 = T3 | T2;
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assign bus_db_pin_oe = SYNTHESIZED_WIRE_0 | SYNTHESIZED_WIRE_1;
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assign SYNTHESIZED_WIRE_3 = T3 & fIORead;
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assign bus_db_pin_re = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3 | SYNTHESIZED_WIRE_4;
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assign bus_ab_pin_we = SYNTHESIZED_WIRE_5 | SYNTHESIZED_WIRE_6;
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assign SYNTHESIZED_WIRE_8 = T2 | T3 | T4;
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assign SYNTHESIZED_WIRE_1 = fMWrite & SYNTHESIZED_WIRE_7;
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assign SYNTHESIZED_WIRE_0 = SYNTHESIZED_WIRE_8 & fIOWrite;
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assign SYNTHESIZED_WIRE_4 = T2 & fFetch;
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assign SYNTHESIZED_WIRE_2 = T2 & fMRead;
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assign SYNTHESIZED_WIRE_6 = T3 & fFetch;
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assign SYNTHESIZED_WIRE_5 = T1 & SYNTHESIZED_WIRE_9;
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endmodule
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