113 lines
2.4 KiB
Verilog
113 lines
2.4 KiB
Verilog
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// Copyright (C) 1991-2013 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// CREATED "Sun Nov 16 23:06:14 2014"
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module control_pins_n(
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busack,
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CPUCLK,
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pin_control_oe,
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in_halt,
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pin_nWAIT,
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pin_nBUSRQ,
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pin_nINT,
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pin_nNMI,
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pin_nRESET,
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nM1_out,
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nRFSH_out,
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nRD_out,
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nWR_out,
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nIORQ_out,
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nMREQ_out,
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nmi,
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busrq,
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clk,
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intr,
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mwait,
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reset_in,
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pin_nM1,
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pin_nMREQ,
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pin_nIORQ,
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pin_nRD,
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pin_nWR,
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pin_nRFSH,
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pin_nHALT,
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pin_nBUSACK
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);
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input wire busack;
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input wire CPUCLK;
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input wire pin_control_oe;
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input wire in_halt;
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input wire pin_nWAIT;
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input wire pin_nBUSRQ;
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input wire pin_nINT;
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input wire pin_nNMI;
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input wire pin_nRESET;
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input wire nM1_out;
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input wire nRFSH_out;
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input wire nRD_out;
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input wire nWR_out;
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input wire nIORQ_out;
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input wire nMREQ_out;
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output wire nmi;
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output wire busrq;
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output wire clk;
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output wire intr;
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output wire mwait;
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output wire reset_in;
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output wire pin_nM1;
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output wire pin_nMREQ;
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output wire pin_nIORQ;
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output wire pin_nRD;
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output wire pin_nWR;
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output wire pin_nRFSH;
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output wire pin_nHALT;
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output wire pin_nBUSACK;
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assign clk = CPUCLK;
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assign pin_nM1 = nM1_out;
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assign pin_nRFSH = nRFSH_out;
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assign pin_nMREQ = pin_control_oe ? nMREQ_out : 1'bz;
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assign pin_nIORQ = pin_control_oe ? nIORQ_out : 1'bz;
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assign pin_nRD = pin_control_oe ? nRD_out : 1'bz;
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assign pin_nWR = pin_control_oe ? nWR_out : 1'bz;
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assign busrq = ~pin_nBUSRQ;
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assign pin_nHALT = ~in_halt;
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assign mwait = ~pin_nWAIT;
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assign pin_nBUSACK = ~busack;
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assign intr = ~pin_nINT;
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assign nmi = ~pin_nNMI;
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assign reset_in = ~pin_nRESET;
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endmodule
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