65 lines
2.2 KiB
Verilog
65 lines
2.2 KiB
Verilog
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// Copyright (C) 1991-2013 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// CREATED "Mon Oct 13 12:21:31 2014"
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module alu_bit_select(
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bsel,
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bs_out_high,
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bs_out_low
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);
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input wire [2:0] bsel;
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output wire [3:0] bs_out_high;
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output wire [3:0] bs_out_low;
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wire [3:0] bs_out_high_ALTERA_SYNTHESIZED;
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wire [3:0] bs_out_low_ALTERA_SYNTHESIZED;
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wire SYNTHESIZED_WIRE_12;
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wire SYNTHESIZED_WIRE_13;
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wire SYNTHESIZED_WIRE_14;
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assign bs_out_low_ALTERA_SYNTHESIZED[0] = SYNTHESIZED_WIRE_12 & SYNTHESIZED_WIRE_13 & SYNTHESIZED_WIRE_14;
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assign bs_out_low_ALTERA_SYNTHESIZED[1] = bsel[0] & SYNTHESIZED_WIRE_13 & SYNTHESIZED_WIRE_14;
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assign bs_out_low_ALTERA_SYNTHESIZED[2] = SYNTHESIZED_WIRE_12 & bsel[1] & SYNTHESIZED_WIRE_14;
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assign bs_out_low_ALTERA_SYNTHESIZED[3] = bsel[0] & bsel[1] & SYNTHESIZED_WIRE_14;
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assign bs_out_high_ALTERA_SYNTHESIZED[0] = SYNTHESIZED_WIRE_12 & SYNTHESIZED_WIRE_13 & bsel[2];
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assign bs_out_high_ALTERA_SYNTHESIZED[1] = bsel[0] & SYNTHESIZED_WIRE_13 & bsel[2];
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assign bs_out_high_ALTERA_SYNTHESIZED[2] = SYNTHESIZED_WIRE_12 & bsel[1] & bsel[2];
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assign bs_out_high_ALTERA_SYNTHESIZED[3] = bsel[0] & bsel[1] & bsel[2];
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assign SYNTHESIZED_WIRE_12 = ~bsel[0];
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assign SYNTHESIZED_WIRE_13 = ~bsel[1];
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assign SYNTHESIZED_WIRE_14 = ~bsel[2];
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assign bs_out_high = bs_out_high_ALTERA_SYNTHESIZED;
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assign bs_out_low = bs_out_low_ALTERA_SYNTHESIZED;
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endmodule
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