<session jtag_chain="USB-Blaster [5-4.2]" jtag_device="@1: EP3C25/EP4CE22 (0x020F30DD)" sof_file="">
  <display_tree gui_logging_enabled="0">
    <display_branch instance="auto_signaltap_0" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
  </display_tree>
  <instance entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
    <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="6"/>
    <signal_set global_temp="1" is_expanded="true" name="signal_set: 2022/04/05 10:32:38  #0">
      <clock name="auto_stp_external_clock_0" polarity="posedge" tap_mode="classic"/>
      <config ram_type="AUTO" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="128" trigger_in_enable="no" trigger_out_enable="no"/>
      <top_entity/>
      <signal_vec>
        <trigger_input_vec>
          <wire name="current_state.state_init" tap_mode="classic"/>
          <wire name="current_state.state_read" tap_mode="classic"/>
          <wire name="current_state.state_read_idle" tap_mode="classic"/>
          <wire name="current_state.state_write" tap_mode="classic"/>
          <wire name="current_state.state_write_idle" tap_mode="classic"/>
          <wire name="next_state.state_init" tap_mode="classic"/>
          <wire name="next_state.state_read" tap_mode="classic"/>
          <wire name="next_state.state_read_idle" tap_mode="classic"/>
          <wire name="next_state.state_write" tap_mode="classic"/>
          <wire name="next_state.state_write_idle" tap_mode="classic"/>
          <wire name="CLOCK_50" tap_mode="probeonly"/>
          <wire name="sdram_write_request~1" tap_mode="probeonly"/>
        </trigger_input_vec>
        <data_input_vec>
          <wire name="current_state.state_init" tap_mode="classic"/>
          <wire name="current_state.state_read" tap_mode="classic"/>
          <wire name="current_state.state_read_idle" tap_mode="classic"/>
          <wire name="current_state.state_write" tap_mode="classic"/>
          <wire name="current_state.state_write_idle" tap_mode="classic"/>
          <wire name="next_state.state_init" tap_mode="classic"/>
          <wire name="next_state.state_read" tap_mode="classic"/>
          <wire name="next_state.state_read_idle" tap_mode="classic"/>
          <wire name="next_state.state_write" tap_mode="classic"/>
          <wire name="next_state.state_write_idle" tap_mode="classic"/>
          <wire name="CLOCK_50" tap_mode="probeonly"/>
          <wire name="sdram_write_request~1" tap_mode="probeonly"/>
        </data_input_vec>
        <storage_qualifier_input_vec>
          <wire name="current_state.state_init" tap_mode="classic"/>
          <wire name="current_state.state_read" tap_mode="classic"/>
          <wire name="current_state.state_read_idle" tap_mode="classic"/>
          <wire name="current_state.state_write" tap_mode="classic"/>
          <wire name="current_state.state_write_idle" tap_mode="classic"/>
          <wire name="next_state.state_init" tap_mode="classic"/>
          <wire name="next_state.state_read" tap_mode="classic"/>
          <wire name="next_state.state_read_idle" tap_mode="classic"/>
          <wire name="next_state.state_write" tap_mode="classic"/>
          <wire name="next_state.state_write_idle" tap_mode="classic"/>
          <wire name="CLOCK_50" tap_mode="probeonly"/>
          <wire name="sdram_write_request~1" tap_mode="probeonly"/>
        </storage_qualifier_input_vec>
      </signal_vec>
      <presentation>
        <unified_setup_data_view>
          <node data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="CLOCK_50" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="probeonly" trigger_index="10" type="unknown"/>
          <node data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="sdram_write_request~1" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="probeonly" trigger_index="11" type="unknown"/>
          <node mnemonics="current_state_table" name="current_state" order="lsb_to_msb" radix="mnemonics" type="state machine">
            <node data_index="0" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_init" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/>
            <node data_index="1" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_read" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/>
            <node data_index="2" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_read_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/>
            <node data_index="3" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_write" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/>
            <node data_index="4" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_write_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/>
          </node>
          <node mnemonics="next_state_table" name="next_state" order="lsb_to_msb" radix="mnemonics" type="state machine">
            <node data_index="5" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_init" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/>
            <node data_index="6" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_read" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/>
            <node data_index="7" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_read_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/>
            <node data_index="8" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_write" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/>
            <node data_index="9" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_write_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/>
          </node>
        </unified_setup_data_view>
        <data_view>
          <net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="CLOCK_50" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="probeonly" trigger_index="10" type="unknown"/>
          <net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="sdram_write_request~1" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="probeonly" trigger_index="11" type="unknown"/>
          <bus mnemonics="current_state_table" name="current_state" order="lsb_to_msb" radix="mnemonics" type="state machine">
            <net data_index="0" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_init" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/>
            <net data_index="1" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_read" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/>
            <net data_index="2" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_read_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/>
            <net data_index="3" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_write" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/>
            <net data_index="4" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_write_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/>
          </bus>
          <bus mnemonics="next_state_table" name="next_state" order="lsb_to_msb" radix="mnemonics" type="state machine">
            <net data_index="5" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_init" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/>
            <net data_index="6" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_read" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/>
            <net data_index="7" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_read_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/>
            <net data_index="8" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_write" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/>
            <net data_index="9" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_write_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/>
          </bus>
        </data_view>
        <setup_view>
          <net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="CLOCK_50" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="probeonly" trigger_index="10" type="unknown"/>
          <net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="sdram_write_request~1" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="probeonly" trigger_index="11" type="unknown"/>
          <bus mnemonics="current_state_table" name="current_state" order="lsb_to_msb" radix="mnemonics" type="state machine">
            <net data_index="0" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_init" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/>
            <net data_index="1" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_read" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/>
            <net data_index="2" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_read_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/>
            <net data_index="3" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_write" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/>
            <net data_index="4" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="current_state.state_write_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/>
          </bus>
          <bus mnemonics="next_state_table" name="next_state" order="lsb_to_msb" radix="mnemonics" type="state machine">
            <net data_index="5" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_init" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/>
            <net data_index="6" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_read" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/>
            <net data_index="7" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_read_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/>
            <net data_index="8" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_write" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/>
            <net data_index="9" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="next_state.state_write_idle" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/>
          </bus>
        </setup_view>
        <trigger_in_editor/>
        <trigger_out_editor/>
      </presentation>
      <trigger CRC="60744367" attribute_mem_mode="false" gap_record="true" global_temp="1" is_expanded="true" name="trigger: 2022/04/05 10:37:05  #0" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="1" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="false" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_type="circular">
        <power_up_trigger position="pre" storage_qualifier_disabled="no"/>
        <events use_custom_flow_control="no">
          <level editor="basic_or" enabled="yes" name="condition1" type="advanced">
            <power_up enabled="yes">
              <power_up_expression><![CDATA[(mbpm('X',{'CLOCK_50'}) && variable(1)) || (mbpm('X',{'sdram_write_request~1'}) && variable(1)) || (('current_state':({'current_state.state_init','current_state.state_read','current_state.state_read_idle','current_state.state_write','current_state.state_write_idle'}) == variable(b00000)) && variable(0)) || (mbpm('X',{'current_state.state_init'}) && variable(1)) || (mbpm('X',{'current_state.state_read'}) && variable(1)) || (mbpm('X',{'current_state.state_read_idle'}) && variable(1)) || (mbpm('X',{'current_state.state_write'}) && variable(1)) || (mbpm('X',{'current_state.state_write_idle'}) && variable(1)) || (('next_state':({'next_state.state_init','next_state.state_read','next_state.state_read_idle','next_state.state_write','next_state.state_write_idle'}) == variable(b00000)) && variable(0)) || (mbpm('X',{'next_state.state_init'}) && variable(1)) || (mbpm('X',{'next_state.state_read'}) && variable(1)) || (mbpm('X',{'next_state.state_read_idle'}) && variable(1)) || (mbpm('X',{'next_state.state_write'}) && variable(1)) || (mbpm('X',{'next_state.state_write_idle'}) && variable(1))]]>
              </power_up_expression>
            </power_up>
            <expression><![CDATA[(mbpm('X',{'CLOCK_50'}) && variable(1)) || (mbpm('X',{'sdram_write_request~1'}) && variable(1)) || (('current_state':({'current_state.state_init','current_state.state_read','current_state.state_read_idle','current_state.state_write','current_state.state_write_idle'}) == variable(b00000)) && variable(0)) || (mbpm('X',{'current_state.state_init'}) && variable(1)) || (mbpm('X',{'current_state.state_read'}) && variable(1)) || (mbpm('X',{'current_state.state_read_idle'}) && variable(1)) || (mbpm('X',{'current_state.state_write'}) && variable(1)) || (mbpm('X',{'current_state.state_write_idle'}) && variable(1)) || (('next_state':({'next_state.state_init','next_state.state_read','next_state.state_read_idle','next_state.state_write','next_state.state_write_idle'}) == variable(b00000)) && variable(0)) || (mbpm('X',{'next_state.state_init'}) && variable(1)) || (mbpm('X',{'next_state.state_read'}) && variable(1)) || (mbpm('X',{'next_state.state_read_idle'}) && variable(1)) || (mbpm('X',{'next_state.state_write'}) && variable(1)) || (mbpm('X',{'next_state.state_write_idle'}) && variable(1))]]>
            </expression>
            <op_node/>
          </level>
        </events>
        <storage_qualifier_events>
          <transitional>111111111111
            <pwr_up_transitional>111111111111</pwr_up_transitional>
          </transitional>
          <storage_qualifier_level type="basic">
            <power_up>
            </power_up>
            <op_node/>
          </storage_qualifier_level>
          <storage_qualifier_level type="basic">
            <power_up>
            </power_up>
            <op_node/>
          </storage_qualifier_level>
          <storage_qualifier_level type="basic">
            <power_up>
            </power_up>
            <op_node/>
          </storage_qualifier_level>
        </storage_qualifier_events>
      </trigger>
    </signal_set>
    <position_info>
      <single attribute="active tab" value="0"/>
    </position_info>
  </instance>
  <mnemonics>
    <table name="current_state_table" width="5">
      <symbol name="state_init" value="00001"/>
      <symbol name="state_read" value="00010"/>
      <symbol name="state_read_idle" value="00100"/>
      <symbol name="state_write" value="01000"/>
      <symbol name="state_write_idle" value="10000"/>
    </table>
    <table name="next_state_table" width="5">
      <symbol name="state_init" value="00001"/>
      <symbol name="state_read" value="00010"/>
      <symbol name="state_read_idle" value="00100"/>
      <symbol name="state_write" value="01000"/>
      <symbol name="state_write_idle" value="10000"/>
    </table>
  </mnemonics>
  <static_plugin_mnemonics/>
  <global_info>
    <single attribute="active instance" value="0"/>
    <single attribute="config widget visible" value="1"/>
    <single attribute="data log widget visible" value="1"/>
    <single attribute="hierarchy widget visible" value="1"/>
    <single attribute="instance widget visible" value="1"/>
    <single attribute="jtag widget visible" value="1"/>
    <multi attribute="column width" size="23" value="34,34,200,74,68,70,88,88,98,98,88,88,643,101,101,101,101,101,101,101,101,107,78"/>
    <multi attribute="frame size" size="2" value="3840,2032"/>
    <multi attribute="jtag widget size" size="2" value="715,200"/>
  </global_info>
</session>
