Analysis & Synthesis report for spectrum
Sat Apr  2 18:53:05 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Messages
  6. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                    ;
+------------------------------------+--------------------------------------------+
; Analysis & Synthesis Status        ; Failed - Sat Apr  2 18:53:05 2022          ;
; Quartus II 32-bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name                      ; spectrum                                   ;
; Top-level Entity Name              ; spectrum                                   ;
; Family                             ; Cyclone IV E                               ;
; Total logic elements               ; N/A until Partition Merge                  ;
;     Total combinational functions  ; N/A until Partition Merge                  ;
;     Dedicated logic registers      ; N/A until Partition Merge                  ;
; Total registers                    ; N/A until Partition Merge                  ;
; Total pins                         ; N/A until Partition Merge                  ;
; Total virtual pins                 ; N/A until Partition Merge                  ;
; Total memory bits                  ; N/A until Partition Merge                  ;
; Embedded Multiplier 9-bit elements ; N/A until Partition Merge                  ;
; Total PLLs                         ; N/A until Partition Merge                  ;
+------------------------------------+--------------------------------------------+


+--------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                  ;
+--------------------------------------------------------------------------------+
Option        : Device
Setting       : EP4CE22F17C6
Default Value : 

Option        : Top-level entity name
Setting       : spectrum
Default Value : spectrum

Option        : Family name
Setting       : Cyclone IV E
Default Value : Cyclone IV GX

Option        : Use smart compilation
Setting       : Off
Default Value : Off

Option        : Enable parallel Assembler and TimeQuest Timing Analyzer during compilation
Setting       : On
Default Value : On

Option        : Enable compact report table
Setting       : Off
Default Value : Off

Option        : Restructure Multiplexers
Setting       : Auto
Default Value : Auto

Option        : Create Debugging Nodes for IP Cores
Setting       : Off
Default Value : Off

Option        : Preserve fewer node names
Setting       : On
Default Value : On

Option        : Disable OpenCore Plus hardware evaluation
Setting       : Off
Default Value : Off

Option        : Verilog Version
Setting       : Verilog_2001
Default Value : Verilog_2001

Option        : VHDL Version
Setting       : VHDL_1993
Default Value : VHDL_1993

Option        : State Machine Processing
Setting       : Auto
Default Value : Auto

Option        : Safe State Machine
Setting       : Off
Default Value : Off

Option        : Extract Verilog State Machines
Setting       : On
Default Value : On

Option        : Extract VHDL State Machines
Setting       : On
Default Value : On

Option        : Ignore Verilog initial constructs
Setting       : Off
Default Value : Off

Option        : Iteration limit for constant Verilog loops
Setting       : 5000
Default Value : 5000

Option        : Iteration limit for non-constant Verilog loops
Setting       : 250
Default Value : 250

Option        : Add Pass-Through Logic to Inferred RAMs
Setting       : On
Default Value : On

Option        : Infer RAMs from Raw Logic
Setting       : On
Default Value : On

Option        : Parallel Synthesis
Setting       : On
Default Value : On

Option        : DSP Block Balancing
Setting       : Auto
Default Value : Auto

Option        : NOT Gate Push-Back
Setting       : On
Default Value : On

Option        : Power-Up Don't Care
Setting       : On
Default Value : On

Option        : Remove Redundant Logic Cells
Setting       : Off
Default Value : Off

Option        : Remove Duplicate Registers
Setting       : On
Default Value : On

Option        : Ignore CARRY Buffers
Setting       : Off
Default Value : Off

Option        : Ignore CASCADE Buffers
Setting       : Off
Default Value : Off

Option        : Ignore GLOBAL Buffers
Setting       : Off
Default Value : Off

Option        : Ignore ROW GLOBAL Buffers
Setting       : Off
Default Value : Off

Option        : Ignore LCELL Buffers
Setting       : Off
Default Value : Off

Option        : Ignore SOFT Buffers
Setting       : On
Default Value : On

Option        : Limit AHDL Integers to 32 Bits
Setting       : Off
Default Value : Off

Option        : Optimization Technique
Setting       : Balanced
Default Value : Balanced

Option        : Carry Chain Length
Setting       : 70
Default Value : 70

Option        : Auto Carry Chains
Setting       : On
Default Value : On

Option        : Auto Open-Drain Pins
Setting       : On
Default Value : On

Option        : Perform WYSIWYG Primitive Resynthesis
Setting       : Off
Default Value : Off

Option        : Auto ROM Replacement
Setting       : On
Default Value : On

Option        : Auto RAM Replacement
Setting       : On
Default Value : On

Option        : Auto DSP Block Replacement
Setting       : On
Default Value : On

Option        : Auto Shift Register Replacement
Setting       : Auto
Default Value : Auto

Option        : Allow Shift Register Merging across Hierarchies
Setting       : Auto
Default Value : Auto

Option        : Auto Clock Enable Replacement
Setting       : On
Default Value : On

Option        : Strict RAM Replacement
Setting       : Off
Default Value : Off

Option        : Allow Synchronous Control Signals
Setting       : On
Default Value : On

Option        : Force Use of Synchronous Clear Signals
Setting       : Off
Default Value : Off

Option        : Auto RAM Block Balancing
Setting       : On
Default Value : On

Option        : Auto RAM to Logic Cell Conversion
Setting       : Off
Default Value : Off

Option        : Auto Resource Sharing
Setting       : Off
Default Value : Off

Option        : Allow Any RAM Size For Recognition
Setting       : Off
Default Value : Off

Option        : Allow Any ROM Size For Recognition
Setting       : Off
Default Value : Off

Option        : Allow Any Shift Register Size For Recognition
Setting       : Off
Default Value : Off

Option        : Use LogicLock Constraints during Resource Balancing
Setting       : On
Default Value : On

Option        : Ignore translate_off and synthesis_off directives
Setting       : Off
Default Value : Off

Option        : Timing-Driven Synthesis
Setting       : On
Default Value : On

Option        : Report Parameter Settings
Setting       : On
Default Value : On

Option        : Report Source Assignments
Setting       : On
Default Value : On

Option        : Report Connectivity Checks
Setting       : On
Default Value : On

Option        : Ignore Maximum Fan-Out Assignments
Setting       : Off
Default Value : Off

Option        : Synchronization Register Chain Length
Setting       : 2
Default Value : 2

Option        : PowerPlay Power Optimization
Setting       : Normal compilation
Default Value : Normal compilation

Option        : HDL message level
Setting       : Level2
Default Value : Level2

Option        : Suppress Register Optimization Related Messages
Setting       : Off
Default Value : Off

Option        : Number of Removed Registers Reported in Synthesis Report
Setting       : 5000
Default Value : 5000

Option        : Number of Swept Nodes Reported in Synthesis Report
Setting       : 5000
Default Value : 5000

Option        : Number of Inverted Registers Reported in Synthesis Report
Setting       : 100
Default Value : 100

Option        : Clock MUX Protection
Setting       : On
Default Value : On

Option        : Auto Gated Clock Conversion
Setting       : Off
Default Value : Off

Option        : Block Design Naming
Setting       : Auto
Default Value : Auto

Option        : SDC constraint protection
Setting       : Off
Default Value : Off

Option        : Synthesis Effort
Setting       : Auto
Default Value : Auto

Option        : Shift Register Replacement - Allow Asynchronous Clear Signal
Setting       : On
Default Value : On

Option        : Pre-Mapping Resynthesis Optimization
Setting       : Off
Default Value : Off

Option        : Analysis & Synthesis Message Level
Setting       : Medium
Default Value : Medium

Option        : Disable Register Merging Across Hierarchies
Setting       : Auto
Default Value : Auto

Option        : Resource Aware Inference For Block RAM
Setting       : On
Default Value : On

Option        : Synthesis Seed
Setting       : 1
Default Value : 1
+--------------------------------------------------------------------------------+



Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 12     ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis
    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
    Info: Processing started: Sat Apr  2 18:53:04 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file spectrum.sv
    Info (12023): Found entity 1: spectrum
Info (12021): Found 1 design units, including 1 entities, in source file rom0.v
    Info (12023): Found entity 1: rom0
Info (12021): Found 1 design units, including 1 entities, in source file ram16.v
    Info (12023): Found entity 1: ram16
Info (12021): Found 1 design units, including 1 entities, in source file ram32.v
    Info (12023): Found entity 1: ram32
Info (12021): Found 1 design units, including 1 entities, in source file pll.v
    Info (12023): Found entity 1: pll
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu.v
    Info (12023): Found entity 1: alu
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_bit_select.v
    Info (12023): Found entity 1: alu_bit_select
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_control.v
    Info (12023): Found entity 1: alu_control
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_core.v
    Info (12023): Found entity 1: alu_core
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_flags.v
    Info (12023): Found entity 1: alu_flags
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2.v
    Info (12023): Found entity 1: alu_mux_2
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2z.v
    Info (12023): Found entity 1: alu_mux_2z
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_3z.v
    Info (12023): Found entity 1: alu_mux_3z
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_4.v
    Info (12023): Found entity 1: alu_mux_4
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_8.v
    Info (12023): Found entity 1: alu_mux_8
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_prep_daa.v
    Info (12023): Found entity 1: alu_prep_daa
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_select.v
    Info (12023): Found entity 1: alu_select
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_shifter_core.v
    Info (12023): Found entity 1: alu_shifter_core
Info (12021): Found 1 design units, including 1 entities, in source file cpu/alu/alu_slice.v
    Info (12023): Found entity 1: alu_slice
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/clk_delay.v
    Info (12023): Found entity 1: clk_delay
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/decode_state.v
    Info (12023): Found entity 1: decode_state
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/execute.v
    Info (12023): Found entity 1: execute
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/interrupts.v
    Info (12023): Found entity 1: interrupts
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/ir.v
    Info (12023): Found entity 1: ir
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/memory_ifc.v
    Info (12023): Found entity 1: memory_ifc
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/pin_control.v
    Info (12023): Found entity 1: pin_control
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/pla_decode.v
    Info (12023): Found entity 1: pla_decode
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/resets.v
    Info (12023): Found entity 1: resets
Info (12021): Found 1 design units, including 1 entities, in source file cpu/control/sequencer.v
    Info (12023): Found entity 1: sequencer
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/address_latch.v
    Info (12023): Found entity 1: address_latch
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/address_mux.v
    Info (12023): Found entity 1: address_mux
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/address_pins.v
    Info (12023): Found entity 1: address_pins
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/bus_control.v
    Info (12023): Found entity 1: bus_control
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/bus_switch.v
    Info (12023): Found entity 1: bus_switch
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/control_pins_n.v
    Info (12023): Found entity 1: control_pins_n
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/data_pins.v
    Info (12023): Found entity 1: data_pins
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/data_switch.v
    Info (12023): Found entity 1: data_switch
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/data_switch_mask.v
    Info (12023): Found entity 1: data_switch_mask
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec.v
    Info (12023): Found entity 1: inc_dec
Info (12021): Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec_2bit.v
    Info (12023): Found entity 1: inc_dec_2bit
Info (12021): Found 1 design units, including 1 entities, in source file cpu/toplevel/z80_top_direct_n.v
    Info (12023): Found entity 1: z80_top_direct_n
Info (12021): Found 1 design units, including 1 entities, in source file cpu/registers/reg_control.v
    Info (12023): Found entity 1: reg_control
Info (12021): Found 1 design units, including 1 entities, in source file cpu/registers/reg_file.v
    Info (12023): Found entity 1: reg_file
Info (12021): Found 1 design units, including 1 entities, in source file cpu/registers/reg_latch.v
    Info (12023): Found entity 1: reg_latch
Info (12021): Found 1 design units, including 1 entities, in source file ula/clocks.sv
    Info (12023): Found entity 1: clocks
Info (12021): Found 1 design units, including 1 entities, in source file ula/zx_kbd.sv
    Info (12023): Found entity 1: zx_keyboard
Info (12021): Found 1 design units, including 1 entities, in source file ula/video.sv
    Info (12023): Found entity 1: video
Info (12021): Found 1 design units, including 1 entities, in source file ula/ula.sv
    Info (12023): Found entity 1: ula
Info (12021): Found 1 design units, including 1 entities, in source file ula/ps2_kbd.sv
    Info (12023): Found entity 1: ps2_keyboard
Info (12021): Found 2 design units, including 1 entities, in source file ula/i2c_loader.vhd
    Info (12022): Found design unit 1: i2c_loader-i2c_loader_arch
    Info (12023): Found entity 1: i2c_loader
Info (12021): Found 2 design units, including 1 entities, in source file ula/i2s_intf.vhd
    Info (12022): Found design unit 1: i2s_intf-i2s_intf_arch
    Info (12023): Found entity 1: i2s_intf
Info (12021): Found 1 design units, including 1 entities, in source file rom_scr.v
    Info (12023): Found entity 1: rom_scr
Info (12021): Found 1 design units, including 1 entities, in source file pll_video.v
    Info (12023): Found entity 1: pll_video
Info (12021): Found 1 design units, including 1 entities, in source file ram_video.v
    Info (12023): Found entity 1: ram_video
Info (12021): Found 2 design units, including 1 entities, in source file sdram.vhdl
    Info (12022): Found design unit 1: sdram_controller-rtl
    Info (12023): Found entity 1: sdram_controller
Info (12021): Found 1 design units, including 1 entities, in source file sdram_clk_gen.v
    Info (12023): Found entity 1: sdram_clk_gen
Warning (10335): Unrecognized synthesis attribute "IOB" at output_files/output_files/sdram.v(118)
Warning (10335): Unrecognized synthesis attribute "IOB" at output_files/output_files/sdram.v(120)
Warning (10335): Unrecognized synthesis attribute "IOB" at output_files/output_files/sdram.v(122)
Warning (10335): Unrecognized synthesis attribute "IOB" at output_files/output_files/sdram.v(124)
Warning (10335): Unrecognized synthesis attribute "IOB" at output_files/output_files/sdram.v(126)
Warning (10335): Unrecognized synthesis attribute "IOB" at output_files/output_files/sdram.v(128)
Info (12021): Found 1 design units, including 1 entities, in source file output_files/output_files/sdram.v
    Info (12023): Found entity 1: sdram
Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(118)
Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(120)
Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(122)
Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(124)
Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(126)
Warning (10335): Unrecognized synthesis attribute "IOB" at sdram.v(128)
Error (10228): Verilog HDL error at sdram.v(12): module "sdram" cannot be declared more than once File: /home/benny/work/fpga/spectrum/sdram.v Line: 12
Info (10499): HDL info at sdram.v(12): see declaration for object "sdram"
Info (12021): Found 0 design units, including 0 entities, in source file sdram.v
Info (144001): Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg
Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 1 error, 13 warnings
    Error: Peak virtual memory: 397 megabytes
    Error: Processing ended: Sat Apr  2 18:53:05 2022
    Error: Elapsed time: 00:00:01
    Error: Total CPU time (on all processors): 00:00:01


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg.


