|spectrum
LED[0] << SW[1].DB_MAX_OUTPUT_PORT_TYPE
LED[1] << raw_loader_in.DB_MAX_OUTPUT_PORT_TYPE
LED[2] << turbo.DB_MAX_OUTPUT_PORT_TYPE
LED[3] << kempston[0].DB_MAX_OUTPUT_PORT_TYPE
LED[4] << kempston[1].DB_MAX_OUTPUT_PORT_TYPE
LED[5] << kempston[2].DB_MAX_OUTPUT_PORT_TYPE
LED[6] << kempston[3].DB_MAX_OUTPUT_PORT_TYPE
LED[7] << LED.DB_MAX_OUTPUT_PORT_TYPE
CLOCK_50 => CLOCK_50.IN6
KEY[0] => reset.IN1
KEY[1] => nNMI.IN1
PS2_CLK => PS2_CLK.IN1
PS2_DAT => PS2_DAT.IN1
I2C_SCLK <> ula:ula_.I2C_SCLK
I2C_SDAT <> ula:ula_.I2C_SDAT
AUD_XCK << ula:ula_.AUD_XCK
AUD_ADCLRCK << ula:ula_.AUD_ADCLRCK
AUD_DACLRCK << ula:ula_.AUD_DACLRCK
AUD_BCLK << ula:ula_.AUD_BCLK
AUD_DACDAT << ula:ula_.AUD_DACDAT
AUD_ADCDAT => AUD_ADCDAT.IN1
VGA_R[0] << ula:ula_.VGA_R
VGA_R[1] << ula:ula_.VGA_R
VGA_R[2] << ula:ula_.VGA_R
VGA_R[3] << ula:ula_.VGA_R
VGA_G[0] << ula:ula_.VGA_G
VGA_G[1] << ula:ula_.VGA_G
VGA_G[2] << ula:ula_.VGA_G
VGA_G[3] << ula:ula_.VGA_G
VGA_B[0] << ula:ula_.VGA_B
VGA_B[1] << ula:ula_.VGA_B
VGA_B[2] << ula:ula_.VGA_B
VGA_B[3] << ula:ula_.VGA_B
VGA_HS << ula:ula_.VGA_HS
VGA_VS << ula:ula_.VGA_VS
SW[0] => ~NO_FANOUT~
SW[1] => LED[0].DATAIN
SW[1] => comb.OUTPUTSELECT
SW[2] => ~NO_FANOUT~
SW[3] => ~NO_FANOUT~
GPIO_1[0] << A[0].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[1] << A[1].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[2] << A[2].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[3] << A[3].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[4] << A[4].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[5] << A[5].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[6] << A[6].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[7] << A[7].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[8] << A[8].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[9] << A[9].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[10] << A[10].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[11] << A[11].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[12] << A[12].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[13] << A[13].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[14] << A[14].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[15] << A[15].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[16] << D[0].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[17] << D[1].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[18] << D[2].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[19] << D[3].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[20] << D[4].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[21] << D[5].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[22] << D[6].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[23] << D[7].DB_MAX_OUTPUT_PORT_TYPE
GPIO_1[24] << z80_top_direct_n:z80_.nBUSACK
GPIO_1[25] << z80_top_direct_n:z80_.nHALT
GPIO_1[26] << z80_top_direct_n:z80_.nRFSH
GPIO_1[27] << z80_top_direct_n:z80_.nWR
GPIO_1[28] << z80_top_direct_n:z80_.nRD
GPIO_1[29] << z80_top_direct_n:z80_.nIORQ
GPIO_1[30] << z80_top_direct_n:z80_.nMREQ
GPIO_1[31] << z80_top_direct_n:z80_.nM1
buzzer_out << ula:ula_.beep
raw_loader_in => raw_loader_in.IN1
DRAM_BA[0] << sdram_controller:sdram_.DRAM_BA
DRAM_BA[1] << sdram_controller:sdram_.DRAM_BA
DRAM_DQM[0] << sdram_controller:sdram_.DRAM_DQM
DRAM_DQM[1] << sdram_controller:sdram_.DRAM_DQM
DRAM_RAS_N << sdram_controller:sdram_.DRAM_RAS_N
DRAM_CAS_N << sdram_controller:sdram_.DRAM_CAS_N
DRAM_CKE << sdram_controller:sdram_.DRAM_CKE
DRAM_CLK << sdram_controller:sdram_.DRAM_CLK
DRAM_WE_N << sdram_controller:sdram_.DRAM_WE_N
DRAM_CS_N << sdram_controller:sdram_.DRAM_CS_N
DRAM_DQ[0] <> sdram_controller:sdram_.DRAM_DQ
DRAM_DQ[1] <> sdram_controller:sdram_.DRAM_DQ
DRAM_DQ[2] <> sdram_controller:sdram_.DRAM_DQ
DRAM_DQ[3] <> sdram_controller:sdram_.DRAM_DQ
DRAM_DQ[4] <> sdram_controller:sdram_.DRAM_DQ
DRAM_DQ[5] <> sdram_controller:sdram_.DRAM_DQ
DRAM_DQ[6] <> sdram_controller:sdram_.DRAM_DQ
DRAM_DQ[7] <> sdram_controller:sdram_.DRAM_DQ
DRAM_DQ[8] <> sdram_controller:sdram_.DRAM_DQ
DRAM_DQ[9] <> sdram_controller:sdram_.DRAM_DQ
DRAM_DQ[10] <> sdram_controller:sdram_.DRAM_DQ
DRAM_DQ[11] <> sdram_controller:sdram_.DRAM_DQ
DRAM_DQ[12] <> sdram_controller:sdram_.DRAM_DQ
DRAM_DQ[13] <> sdram_controller:sdram_.DRAM_DQ
DRAM_DQ[14] <> sdram_controller:sdram_.DRAM_DQ
DRAM_DQ[15] <> sdram_controller:sdram_.DRAM_DQ
DRAM_ADDR[0] << sdram_controller:sdram_.DRAM_ADDR
DRAM_ADDR[1] << sdram_controller:sdram_.DRAM_ADDR
DRAM_ADDR[2] << sdram_controller:sdram_.DRAM_ADDR
DRAM_ADDR[3] << sdram_controller:sdram_.DRAM_ADDR
DRAM_ADDR[4] << sdram_controller:sdram_.DRAM_ADDR
DRAM_ADDR[5] << sdram_controller:sdram_.DRAM_ADDR
DRAM_ADDR[6] << sdram_controller:sdram_.DRAM_ADDR
DRAM_ADDR[7] << sdram_controller:sdram_.DRAM_ADDR
DRAM_ADDR[8] << sdram_controller:sdram_.DRAM_ADDR
DRAM_ADDR[9] << sdram_controller:sdram_.DRAM_ADDR
DRAM_ADDR[10] << sdram_controller:sdram_.DRAM_ADDR
DRAM_ADDR[11] << sdram_controller:sdram_.DRAM_ADDR
DRAM_ADDR[12] << sdram_controller:sdram_.DRAM_ADDR
kempston[0] => LED[3].DATAIN
kempston[0] => D.DATAB
kempston[1] => LED[4].DATAIN
kempston[1] => D.DATAB
kempston[2] => LED[5].DATAIN
kempston[2] => D.DATAB
kempston[3] => LED[6].DATAIN
kempston[3] => D.DATAB
kempston[4] => LED.IN1
kempston[4] => D.IN1
kempston_gnd << <GND>
turbo_button => turbo_button.IN1
kempston_autofire_button => kempston_autofire_button.IN1


|spectrum|debouncer:debounce_turbo
i_Clk => r_State.CLK
i_Clk => r_Count[0].CLK
i_Clk => r_Count[1].CLK
i_Clk => r_Count[2].CLK
i_Clk => r_Count[3].CLK
i_Clk => r_Count[4].CLK
i_Clk => r_Count[5].CLK
i_Clk => r_Count[6].CLK
i_Clk => r_Count[7].CLK
i_Clk => r_Count[8].CLK
i_Clk => r_Count[9].CLK
i_Clk => r_Count[10].CLK
i_Clk => r_Count[11].CLK
i_Clk => r_Count[12].CLK
i_Clk => r_Count[13].CLK
i_Clk => r_Count[14].CLK
i_Clk => r_Count[15].CLK
i_Clk => r_Count[16].CLK
i_Clk => r_Count[17].CLK
i_Clk => r_Count[18].CLK
i_Clk => r_Count[19].CLK
i_Clk => r_Count[20].CLK
i_Switch => always0.IN1
i_Switch => r_State.DATAB
o_Switch <= r_State.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|debouncer:debounce_autofire
i_Clk => r_State.CLK
i_Clk => r_Count[0].CLK
i_Clk => r_Count[1].CLK
i_Clk => r_Count[2].CLK
i_Clk => r_Count[3].CLK
i_Clk => r_Count[4].CLK
i_Clk => r_Count[5].CLK
i_Clk => r_Count[6].CLK
i_Clk => r_Count[7].CLK
i_Clk => r_Count[8].CLK
i_Clk => r_Count[9].CLK
i_Clk => r_Count[10].CLK
i_Clk => r_Count[11].CLK
i_Clk => r_Count[12].CLK
i_Clk => r_Count[13].CLK
i_Clk => r_Count[14].CLK
i_Clk => r_Count[15].CLK
i_Clk => r_Count[16].CLK
i_Clk => r_Count[17].CLK
i_Clk => r_Count[18].CLK
i_Clk => r_Count[19].CLK
i_Clk => r_Count[20].CLK
i_Switch => always0.IN1
i_Switch => r_State.DATAB
o_Switch <= r_State.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|rom0:rom
address[0] => address[0].IN1
address[1] => address[1].IN1
address[2] => address[2].IN1
address[3] => address[3].IN1
address[4] => address[4].IN1
address[5] => address[5].IN1
address[6] => address[6].IN1
address[7] => address[7].IN1
address[8] => address[8].IN1
address[9] => address[9].IN1
address[10] => address[10].IN1
address[11] => address[11].IN1
address[12] => address[12].IN1
address[13] => address[13].IN1
clock => clock.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a


|spectrum|rom0:rom|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_qh91:auto_generated.address_a[0]
address_a[1] => altsyncram_qh91:auto_generated.address_a[1]
address_a[2] => altsyncram_qh91:auto_generated.address_a[2]
address_a[3] => altsyncram_qh91:auto_generated.address_a[3]
address_a[4] => altsyncram_qh91:auto_generated.address_a[4]
address_a[5] => altsyncram_qh91:auto_generated.address_a[5]
address_a[6] => altsyncram_qh91:auto_generated.address_a[6]
address_a[7] => altsyncram_qh91:auto_generated.address_a[7]
address_a[8] => altsyncram_qh91:auto_generated.address_a[8]
address_a[9] => altsyncram_qh91:auto_generated.address_a[9]
address_a[10] => altsyncram_qh91:auto_generated.address_a[10]
address_a[11] => altsyncram_qh91:auto_generated.address_a[11]
address_a[12] => altsyncram_qh91:auto_generated.address_a[12]
address_a[13] => altsyncram_qh91:auto_generated.address_a[13]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_qh91:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_qh91:auto_generated.q_a[0]
q_a[1] <= altsyncram_qh91:auto_generated.q_a[1]
q_a[2] <= altsyncram_qh91:auto_generated.q_a[2]
q_a[3] <= altsyncram_qh91:auto_generated.q_a[3]
q_a[4] <= altsyncram_qh91:auto_generated.q_a[4]
q_a[5] <= altsyncram_qh91:auto_generated.q_a[5]
q_a[6] <= altsyncram_qh91:auto_generated.q_a[6]
q_a[7] <= altsyncram_qh91:auto_generated.q_a[7]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[5] => ram_block1a12.PORTAADDR5
address_a[5] => ram_block1a13.PORTAADDR5
address_a[5] => ram_block1a14.PORTAADDR5
address_a[5] => ram_block1a15.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[6] => ram_block1a10.PORTAADDR6
address_a[6] => ram_block1a11.PORTAADDR6
address_a[6] => ram_block1a12.PORTAADDR6
address_a[6] => ram_block1a13.PORTAADDR6
address_a[6] => ram_block1a14.PORTAADDR6
address_a[6] => ram_block1a15.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[7] => ram_block1a10.PORTAADDR7
address_a[7] => ram_block1a11.PORTAADDR7
address_a[7] => ram_block1a12.PORTAADDR7
address_a[7] => ram_block1a13.PORTAADDR7
address_a[7] => ram_block1a14.PORTAADDR7
address_a[7] => ram_block1a15.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[8] => ram_block1a8.PORTAADDR8
address_a[8] => ram_block1a9.PORTAADDR8
address_a[8] => ram_block1a10.PORTAADDR8
address_a[8] => ram_block1a11.PORTAADDR8
address_a[8] => ram_block1a12.PORTAADDR8
address_a[8] => ram_block1a13.PORTAADDR8
address_a[8] => ram_block1a14.PORTAADDR8
address_a[8] => ram_block1a15.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_a[9] => ram_block1a8.PORTAADDR9
address_a[9] => ram_block1a9.PORTAADDR9
address_a[9] => ram_block1a10.PORTAADDR9
address_a[9] => ram_block1a11.PORTAADDR9
address_a[9] => ram_block1a12.PORTAADDR9
address_a[9] => ram_block1a13.PORTAADDR9
address_a[9] => ram_block1a14.PORTAADDR9
address_a[9] => ram_block1a15.PORTAADDR9
address_a[10] => ram_block1a0.PORTAADDR10
address_a[10] => ram_block1a1.PORTAADDR10
address_a[10] => ram_block1a2.PORTAADDR10
address_a[10] => ram_block1a3.PORTAADDR10
address_a[10] => ram_block1a4.PORTAADDR10
address_a[10] => ram_block1a5.PORTAADDR10
address_a[10] => ram_block1a6.PORTAADDR10
address_a[10] => ram_block1a7.PORTAADDR10
address_a[10] => ram_block1a8.PORTAADDR10
address_a[10] => ram_block1a9.PORTAADDR10
address_a[10] => ram_block1a10.PORTAADDR10
address_a[10] => ram_block1a11.PORTAADDR10
address_a[10] => ram_block1a12.PORTAADDR10
address_a[10] => ram_block1a13.PORTAADDR10
address_a[10] => ram_block1a14.PORTAADDR10
address_a[10] => ram_block1a15.PORTAADDR10
address_a[11] => ram_block1a0.PORTAADDR11
address_a[11] => ram_block1a1.PORTAADDR11
address_a[11] => ram_block1a2.PORTAADDR11
address_a[11] => ram_block1a3.PORTAADDR11
address_a[11] => ram_block1a4.PORTAADDR11
address_a[11] => ram_block1a5.PORTAADDR11
address_a[11] => ram_block1a6.PORTAADDR11
address_a[11] => ram_block1a7.PORTAADDR11
address_a[11] => ram_block1a8.PORTAADDR11
address_a[11] => ram_block1a9.PORTAADDR11
address_a[11] => ram_block1a10.PORTAADDR11
address_a[11] => ram_block1a11.PORTAADDR11
address_a[11] => ram_block1a12.PORTAADDR11
address_a[11] => ram_block1a13.PORTAADDR11
address_a[11] => ram_block1a14.PORTAADDR11
address_a[11] => ram_block1a15.PORTAADDR11
address_a[12] => ram_block1a0.PORTAADDR12
address_a[12] => ram_block1a1.PORTAADDR12
address_a[12] => ram_block1a2.PORTAADDR12
address_a[12] => ram_block1a3.PORTAADDR12
address_a[12] => ram_block1a4.PORTAADDR12
address_a[12] => ram_block1a5.PORTAADDR12
address_a[12] => ram_block1a6.PORTAADDR12
address_a[12] => ram_block1a7.PORTAADDR12
address_a[12] => ram_block1a8.PORTAADDR12
address_a[12] => ram_block1a9.PORTAADDR12
address_a[12] => ram_block1a10.PORTAADDR12
address_a[12] => ram_block1a11.PORTAADDR12
address_a[12] => ram_block1a12.PORTAADDR12
address_a[12] => ram_block1a13.PORTAADDR12
address_a[12] => ram_block1a14.PORTAADDR12
address_a[12] => ram_block1a15.PORTAADDR12
address_a[13] => address_reg_a[0].DATAIN
address_a[13] => decode_c8a:rden_decode.data[0]
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
clock0 => address_reg_a[0].CLK
clock0 => out_address_reg_a[0].CLK
q_a[0] <= mux_3nb:mux2.result[0]
q_a[1] <= mux_3nb:mux2.result[1]
q_a[2] <= mux_3nb:mux2.result[2]
q_a[3] <= mux_3nb:mux2.result[3]
q_a[4] <= mux_3nb:mux2.result[4]
q_a[5] <= mux_3nb:mux2.result[5]
q_a[6] <= mux_3nb:mux2.result[6]
q_a[7] <= mux_3nb:mux2.result[7]


|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|decode_c8a:rden_decode
data[0] => eq_node[1].IN0
data[0] => eq_node[0].IN0
eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE


|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2
data[0] => result_node[0].IN1
data[1] => result_node[1].IN1
data[2] => result_node[2].IN1
data[3] => result_node[3].IN1
data[4] => result_node[4].IN1
data[5] => result_node[5].IN1
data[6] => result_node[6].IN1
data[7] => result_node[7].IN1
data[8] => result_node[0].IN1
data[9] => result_node[1].IN1
data[10] => result_node[2].IN1
data[11] => result_node[3].IN1
data[12] => result_node[4].IN1
data[13] => result_node[5].IN1
data[14] => result_node[6].IN1
data[15] => result_node[7].IN1
result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE
sel[0] => result_node[7].IN0
sel[0] => _.IN0
sel[0] => result_node[6].IN0
sel[0] => _.IN0
sel[0] => result_node[5].IN0
sel[0] => _.IN0
sel[0] => result_node[4].IN0
sel[0] => _.IN0
sel[0] => result_node[3].IN0
sel[0] => _.IN0
sel[0] => result_node[2].IN0
sel[0] => _.IN0
sel[0] => result_node[1].IN0
sel[0] => _.IN0
sel[0] => result_node[0].IN0
sel[0] => _.IN0


|spectrum|ram16:ram0
address_a[0] => address_a[0].IN1
address_a[1] => address_a[1].IN1
address_a[2] => address_a[2].IN1
address_a[3] => address_a[3].IN1
address_a[4] => address_a[4].IN1
address_a[5] => address_a[5].IN1
address_a[6] => address_a[6].IN1
address_a[7] => address_a[7].IN1
address_a[8] => address_a[8].IN1
address_a[9] => address_a[9].IN1
address_a[10] => address_a[10].IN1
address_a[11] => address_a[11].IN1
address_a[12] => address_a[12].IN1
address_a[13] => address_a[13].IN1
address_b[0] => address_b[0].IN1
address_b[1] => address_b[1].IN1
address_b[2] => address_b[2].IN1
address_b[3] => address_b[3].IN1
address_b[4] => address_b[4].IN1
address_b[5] => address_b[5].IN1
address_b[6] => address_b[6].IN1
address_b[7] => address_b[7].IN1
address_b[8] => address_b[8].IN1
address_b[9] => address_b[9].IN1
address_b[10] => address_b[10].IN1
address_b[11] => address_b[11].IN1
address_b[12] => address_b[12].IN1
address_b[13] => address_b[13].IN1
clock => clock.IN1
data_a[0] => data_a[0].IN1
data_a[1] => data_a[1].IN1
data_a[2] => data_a[2].IN1
data_a[3] => data_a[3].IN1
data_a[4] => data_a[4].IN1
data_a[5] => data_a[5].IN1
data_a[6] => data_a[6].IN1
data_a[7] => data_a[7].IN1
data_b[0] => data_b[0].IN1
data_b[1] => data_b[1].IN1
data_b[2] => data_b[2].IN1
data_b[3] => data_b[3].IN1
data_b[4] => data_b[4].IN1
data_b[5] => data_b[5].IN1
data_b[6] => data_b[6].IN1
data_b[7] => data_b[7].IN1
wren_a => wren_a.IN1
wren_b => wren_b.IN1
q_a[0] <= altsyncram:altsyncram_component.q_a
q_a[1] <= altsyncram:altsyncram_component.q_a
q_a[2] <= altsyncram:altsyncram_component.q_a
q_a[3] <= altsyncram:altsyncram_component.q_a
q_a[4] <= altsyncram:altsyncram_component.q_a
q_a[5] <= altsyncram:altsyncram_component.q_a
q_a[6] <= altsyncram:altsyncram_component.q_a
q_a[7] <= altsyncram:altsyncram_component.q_a
q_b[0] <= altsyncram:altsyncram_component.q_b
q_b[1] <= altsyncram:altsyncram_component.q_b
q_b[2] <= altsyncram:altsyncram_component.q_b
q_b[3] <= altsyncram:altsyncram_component.q_b
q_b[4] <= altsyncram:altsyncram_component.q_b
q_b[5] <= altsyncram:altsyncram_component.q_b
q_b[6] <= altsyncram:altsyncram_component.q_b
q_b[7] <= altsyncram:altsyncram_component.q_b


|spectrum|ram16:ram0|altsyncram:altsyncram_component
wren_a => altsyncram_7ti2:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => altsyncram_7ti2:auto_generated.wren_b
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_7ti2:auto_generated.data_a[0]
data_a[1] => altsyncram_7ti2:auto_generated.data_a[1]
data_a[2] => altsyncram_7ti2:auto_generated.data_a[2]
data_a[3] => altsyncram_7ti2:auto_generated.data_a[3]
data_a[4] => altsyncram_7ti2:auto_generated.data_a[4]
data_a[5] => altsyncram_7ti2:auto_generated.data_a[5]
data_a[6] => altsyncram_7ti2:auto_generated.data_a[6]
data_a[7] => altsyncram_7ti2:auto_generated.data_a[7]
data_b[0] => altsyncram_7ti2:auto_generated.data_b[0]
data_b[1] => altsyncram_7ti2:auto_generated.data_b[1]
data_b[2] => altsyncram_7ti2:auto_generated.data_b[2]
data_b[3] => altsyncram_7ti2:auto_generated.data_b[3]
data_b[4] => altsyncram_7ti2:auto_generated.data_b[4]
data_b[5] => altsyncram_7ti2:auto_generated.data_b[5]
data_b[6] => altsyncram_7ti2:auto_generated.data_b[6]
data_b[7] => altsyncram_7ti2:auto_generated.data_b[7]
address_a[0] => altsyncram_7ti2:auto_generated.address_a[0]
address_a[1] => altsyncram_7ti2:auto_generated.address_a[1]
address_a[2] => altsyncram_7ti2:auto_generated.address_a[2]
address_a[3] => altsyncram_7ti2:auto_generated.address_a[3]
address_a[4] => altsyncram_7ti2:auto_generated.address_a[4]
address_a[5] => altsyncram_7ti2:auto_generated.address_a[5]
address_a[6] => altsyncram_7ti2:auto_generated.address_a[6]
address_a[7] => altsyncram_7ti2:auto_generated.address_a[7]
address_a[8] => altsyncram_7ti2:auto_generated.address_a[8]
address_a[9] => altsyncram_7ti2:auto_generated.address_a[9]
address_a[10] => altsyncram_7ti2:auto_generated.address_a[10]
address_a[11] => altsyncram_7ti2:auto_generated.address_a[11]
address_a[12] => altsyncram_7ti2:auto_generated.address_a[12]
address_a[13] => altsyncram_7ti2:auto_generated.address_a[13]
address_b[0] => altsyncram_7ti2:auto_generated.address_b[0]
address_b[1] => altsyncram_7ti2:auto_generated.address_b[1]
address_b[2] => altsyncram_7ti2:auto_generated.address_b[2]
address_b[3] => altsyncram_7ti2:auto_generated.address_b[3]
address_b[4] => altsyncram_7ti2:auto_generated.address_b[4]
address_b[5] => altsyncram_7ti2:auto_generated.address_b[5]
address_b[6] => altsyncram_7ti2:auto_generated.address_b[6]
address_b[7] => altsyncram_7ti2:auto_generated.address_b[7]
address_b[8] => altsyncram_7ti2:auto_generated.address_b[8]
address_b[9] => altsyncram_7ti2:auto_generated.address_b[9]
address_b[10] => altsyncram_7ti2:auto_generated.address_b[10]
address_b[11] => altsyncram_7ti2:auto_generated.address_b[11]
address_b[12] => altsyncram_7ti2:auto_generated.address_b[12]
address_b[13] => altsyncram_7ti2:auto_generated.address_b[13]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_7ti2:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_7ti2:auto_generated.q_a[0]
q_a[1] <= altsyncram_7ti2:auto_generated.q_a[1]
q_a[2] <= altsyncram_7ti2:auto_generated.q_a[2]
q_a[3] <= altsyncram_7ti2:auto_generated.q_a[3]
q_a[4] <= altsyncram_7ti2:auto_generated.q_a[4]
q_a[5] <= altsyncram_7ti2:auto_generated.q_a[5]
q_a[6] <= altsyncram_7ti2:auto_generated.q_a[6]
q_a[7] <= altsyncram_7ti2:auto_generated.q_a[7]
q_b[0] <= altsyncram_7ti2:auto_generated.q_b[0]
q_b[1] <= altsyncram_7ti2:auto_generated.q_b[1]
q_b[2] <= altsyncram_7ti2:auto_generated.q_b[2]
q_b[3] <= altsyncram_7ti2:auto_generated.q_b[3]
q_b[4] <= altsyncram_7ti2:auto_generated.q_b[4]
q_b[5] <= altsyncram_7ti2:auto_generated.q_b[5]
q_b[6] <= altsyncram_7ti2:auto_generated.q_b[6]
q_b[7] <= altsyncram_7ti2:auto_generated.q_b[7]
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[5] => ram_block1a12.PORTAADDR5
address_a[5] => ram_block1a13.PORTAADDR5
address_a[5] => ram_block1a14.PORTAADDR5
address_a[5] => ram_block1a15.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[6] => ram_block1a10.PORTAADDR6
address_a[6] => ram_block1a11.PORTAADDR6
address_a[6] => ram_block1a12.PORTAADDR6
address_a[6] => ram_block1a13.PORTAADDR6
address_a[6] => ram_block1a14.PORTAADDR6
address_a[6] => ram_block1a15.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[7] => ram_block1a10.PORTAADDR7
address_a[7] => ram_block1a11.PORTAADDR7
address_a[7] => ram_block1a12.PORTAADDR7
address_a[7] => ram_block1a13.PORTAADDR7
address_a[7] => ram_block1a14.PORTAADDR7
address_a[7] => ram_block1a15.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[8] => ram_block1a8.PORTAADDR8
address_a[8] => ram_block1a9.PORTAADDR8
address_a[8] => ram_block1a10.PORTAADDR8
address_a[8] => ram_block1a11.PORTAADDR8
address_a[8] => ram_block1a12.PORTAADDR8
address_a[8] => ram_block1a13.PORTAADDR8
address_a[8] => ram_block1a14.PORTAADDR8
address_a[8] => ram_block1a15.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_a[9] => ram_block1a8.PORTAADDR9
address_a[9] => ram_block1a9.PORTAADDR9
address_a[9] => ram_block1a10.PORTAADDR9
address_a[9] => ram_block1a11.PORTAADDR9
address_a[9] => ram_block1a12.PORTAADDR9
address_a[9] => ram_block1a13.PORTAADDR9
address_a[9] => ram_block1a14.PORTAADDR9
address_a[9] => ram_block1a15.PORTAADDR9
address_a[10] => ram_block1a0.PORTAADDR10
address_a[10] => ram_block1a1.PORTAADDR10
address_a[10] => ram_block1a2.PORTAADDR10
address_a[10] => ram_block1a3.PORTAADDR10
address_a[10] => ram_block1a4.PORTAADDR10
address_a[10] => ram_block1a5.PORTAADDR10
address_a[10] => ram_block1a6.PORTAADDR10
address_a[10] => ram_block1a7.PORTAADDR10
address_a[10] => ram_block1a8.PORTAADDR10
address_a[10] => ram_block1a9.PORTAADDR10
address_a[10] => ram_block1a10.PORTAADDR10
address_a[10] => ram_block1a11.PORTAADDR10
address_a[10] => ram_block1a12.PORTAADDR10
address_a[10] => ram_block1a13.PORTAADDR10
address_a[10] => ram_block1a14.PORTAADDR10
address_a[10] => ram_block1a15.PORTAADDR10
address_a[11] => ram_block1a0.PORTAADDR11
address_a[11] => ram_block1a1.PORTAADDR11
address_a[11] => ram_block1a2.PORTAADDR11
address_a[11] => ram_block1a3.PORTAADDR11
address_a[11] => ram_block1a4.PORTAADDR11
address_a[11] => ram_block1a5.PORTAADDR11
address_a[11] => ram_block1a6.PORTAADDR11
address_a[11] => ram_block1a7.PORTAADDR11
address_a[11] => ram_block1a8.PORTAADDR11
address_a[11] => ram_block1a9.PORTAADDR11
address_a[11] => ram_block1a10.PORTAADDR11
address_a[11] => ram_block1a11.PORTAADDR11
address_a[11] => ram_block1a12.PORTAADDR11
address_a[11] => ram_block1a13.PORTAADDR11
address_a[11] => ram_block1a14.PORTAADDR11
address_a[11] => ram_block1a15.PORTAADDR11
address_a[12] => ram_block1a0.PORTAADDR12
address_a[12] => ram_block1a1.PORTAADDR12
address_a[12] => ram_block1a2.PORTAADDR12
address_a[12] => ram_block1a3.PORTAADDR12
address_a[12] => ram_block1a4.PORTAADDR12
address_a[12] => ram_block1a5.PORTAADDR12
address_a[12] => ram_block1a6.PORTAADDR12
address_a[12] => ram_block1a7.PORTAADDR12
address_a[12] => ram_block1a8.PORTAADDR12
address_a[12] => ram_block1a9.PORTAADDR12
address_a[12] => ram_block1a10.PORTAADDR12
address_a[12] => ram_block1a11.PORTAADDR12
address_a[12] => ram_block1a12.PORTAADDR12
address_a[12] => ram_block1a13.PORTAADDR12
address_a[12] => ram_block1a14.PORTAADDR12
address_a[12] => ram_block1a15.PORTAADDR12
address_a[13] => address_reg_a[0].DATAIN
address_a[13] => decode_jsa:decode2.data[0]
address_a[13] => decode_c8a:rden_decode_a.data[0]
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[0] => ram_block1a5.PORTBADDR
address_b[0] => ram_block1a6.PORTBADDR
address_b[0] => ram_block1a7.PORTBADDR
address_b[0] => ram_block1a8.PORTBADDR
address_b[0] => ram_block1a9.PORTBADDR
address_b[0] => ram_block1a10.PORTBADDR
address_b[0] => ram_block1a11.PORTBADDR
address_b[0] => ram_block1a12.PORTBADDR
address_b[0] => ram_block1a13.PORTBADDR
address_b[0] => ram_block1a14.PORTBADDR
address_b[0] => ram_block1a15.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[1] => ram_block1a4.PORTBADDR1
address_b[1] => ram_block1a5.PORTBADDR1
address_b[1] => ram_block1a6.PORTBADDR1
address_b[1] => ram_block1a7.PORTBADDR1
address_b[1] => ram_block1a8.PORTBADDR1
address_b[1] => ram_block1a9.PORTBADDR1
address_b[1] => ram_block1a10.PORTBADDR1
address_b[1] => ram_block1a11.PORTBADDR1
address_b[1] => ram_block1a12.PORTBADDR1
address_b[1] => ram_block1a13.PORTBADDR1
address_b[1] => ram_block1a14.PORTBADDR1
address_b[1] => ram_block1a15.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[2] => ram_block1a4.PORTBADDR2
address_b[2] => ram_block1a5.PORTBADDR2
address_b[2] => ram_block1a6.PORTBADDR2
address_b[2] => ram_block1a7.PORTBADDR2
address_b[2] => ram_block1a8.PORTBADDR2
address_b[2] => ram_block1a9.PORTBADDR2
address_b[2] => ram_block1a10.PORTBADDR2
address_b[2] => ram_block1a11.PORTBADDR2
address_b[2] => ram_block1a12.PORTBADDR2
address_b[2] => ram_block1a13.PORTBADDR2
address_b[2] => ram_block1a14.PORTBADDR2
address_b[2] => ram_block1a15.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[3] => ram_block1a2.PORTBADDR3
address_b[3] => ram_block1a3.PORTBADDR3
address_b[3] => ram_block1a4.PORTBADDR3
address_b[3] => ram_block1a5.PORTBADDR3
address_b[3] => ram_block1a6.PORTBADDR3
address_b[3] => ram_block1a7.PORTBADDR3
address_b[3] => ram_block1a8.PORTBADDR3
address_b[3] => ram_block1a9.PORTBADDR3
address_b[3] => ram_block1a10.PORTBADDR3
address_b[3] => ram_block1a11.PORTBADDR3
address_b[3] => ram_block1a12.PORTBADDR3
address_b[3] => ram_block1a13.PORTBADDR3
address_b[3] => ram_block1a14.PORTBADDR3
address_b[3] => ram_block1a15.PORTBADDR3
address_b[4] => ram_block1a0.PORTBADDR4
address_b[4] => ram_block1a1.PORTBADDR4
address_b[4] => ram_block1a2.PORTBADDR4
address_b[4] => ram_block1a3.PORTBADDR4
address_b[4] => ram_block1a4.PORTBADDR4
address_b[4] => ram_block1a5.PORTBADDR4
address_b[4] => ram_block1a6.PORTBADDR4
address_b[4] => ram_block1a7.PORTBADDR4
address_b[4] => ram_block1a8.PORTBADDR4
address_b[4] => ram_block1a9.PORTBADDR4
address_b[4] => ram_block1a10.PORTBADDR4
address_b[4] => ram_block1a11.PORTBADDR4
address_b[4] => ram_block1a12.PORTBADDR4
address_b[4] => ram_block1a13.PORTBADDR4
address_b[4] => ram_block1a14.PORTBADDR4
address_b[4] => ram_block1a15.PORTBADDR4
address_b[5] => ram_block1a0.PORTBADDR5
address_b[5] => ram_block1a1.PORTBADDR5
address_b[5] => ram_block1a2.PORTBADDR5
address_b[5] => ram_block1a3.PORTBADDR5
address_b[5] => ram_block1a4.PORTBADDR5
address_b[5] => ram_block1a5.PORTBADDR5
address_b[5] => ram_block1a6.PORTBADDR5
address_b[5] => ram_block1a7.PORTBADDR5
address_b[5] => ram_block1a8.PORTBADDR5
address_b[5] => ram_block1a9.PORTBADDR5
address_b[5] => ram_block1a10.PORTBADDR5
address_b[5] => ram_block1a11.PORTBADDR5
address_b[5] => ram_block1a12.PORTBADDR5
address_b[5] => ram_block1a13.PORTBADDR5
address_b[5] => ram_block1a14.PORTBADDR5
address_b[5] => ram_block1a15.PORTBADDR5
address_b[6] => ram_block1a0.PORTBADDR6
address_b[6] => ram_block1a1.PORTBADDR6
address_b[6] => ram_block1a2.PORTBADDR6
address_b[6] => ram_block1a3.PORTBADDR6
address_b[6] => ram_block1a4.PORTBADDR6
address_b[6] => ram_block1a5.PORTBADDR6
address_b[6] => ram_block1a6.PORTBADDR6
address_b[6] => ram_block1a7.PORTBADDR6
address_b[6] => ram_block1a8.PORTBADDR6
address_b[6] => ram_block1a9.PORTBADDR6
address_b[6] => ram_block1a10.PORTBADDR6
address_b[6] => ram_block1a11.PORTBADDR6
address_b[6] => ram_block1a12.PORTBADDR6
address_b[6] => ram_block1a13.PORTBADDR6
address_b[6] => ram_block1a14.PORTBADDR6
address_b[6] => ram_block1a15.PORTBADDR6
address_b[7] => ram_block1a0.PORTBADDR7
address_b[7] => ram_block1a1.PORTBADDR7
address_b[7] => ram_block1a2.PORTBADDR7
address_b[7] => ram_block1a3.PORTBADDR7
address_b[7] => ram_block1a4.PORTBADDR7
address_b[7] => ram_block1a5.PORTBADDR7
address_b[7] => ram_block1a6.PORTBADDR7
address_b[7] => ram_block1a7.PORTBADDR7
address_b[7] => ram_block1a8.PORTBADDR7
address_b[7] => ram_block1a9.PORTBADDR7
address_b[7] => ram_block1a10.PORTBADDR7
address_b[7] => ram_block1a11.PORTBADDR7
address_b[7] => ram_block1a12.PORTBADDR7
address_b[7] => ram_block1a13.PORTBADDR7
address_b[7] => ram_block1a14.PORTBADDR7
address_b[7] => ram_block1a15.PORTBADDR7
address_b[8] => ram_block1a0.PORTBADDR8
address_b[8] => ram_block1a1.PORTBADDR8
address_b[8] => ram_block1a2.PORTBADDR8
address_b[8] => ram_block1a3.PORTBADDR8
address_b[8] => ram_block1a4.PORTBADDR8
address_b[8] => ram_block1a5.PORTBADDR8
address_b[8] => ram_block1a6.PORTBADDR8
address_b[8] => ram_block1a7.PORTBADDR8
address_b[8] => ram_block1a8.PORTBADDR8
address_b[8] => ram_block1a9.PORTBADDR8
address_b[8] => ram_block1a10.PORTBADDR8
address_b[8] => ram_block1a11.PORTBADDR8
address_b[8] => ram_block1a12.PORTBADDR8
address_b[8] => ram_block1a13.PORTBADDR8
address_b[8] => ram_block1a14.PORTBADDR8
address_b[8] => ram_block1a15.PORTBADDR8
address_b[9] => ram_block1a0.PORTBADDR9
address_b[9] => ram_block1a1.PORTBADDR9
address_b[9] => ram_block1a2.PORTBADDR9
address_b[9] => ram_block1a3.PORTBADDR9
address_b[9] => ram_block1a4.PORTBADDR9
address_b[9] => ram_block1a5.PORTBADDR9
address_b[9] => ram_block1a6.PORTBADDR9
address_b[9] => ram_block1a7.PORTBADDR9
address_b[9] => ram_block1a8.PORTBADDR9
address_b[9] => ram_block1a9.PORTBADDR9
address_b[9] => ram_block1a10.PORTBADDR9
address_b[9] => ram_block1a11.PORTBADDR9
address_b[9] => ram_block1a12.PORTBADDR9
address_b[9] => ram_block1a13.PORTBADDR9
address_b[9] => ram_block1a14.PORTBADDR9
address_b[9] => ram_block1a15.PORTBADDR9
address_b[10] => ram_block1a0.PORTBADDR10
address_b[10] => ram_block1a1.PORTBADDR10
address_b[10] => ram_block1a2.PORTBADDR10
address_b[10] => ram_block1a3.PORTBADDR10
address_b[10] => ram_block1a4.PORTBADDR10
address_b[10] => ram_block1a5.PORTBADDR10
address_b[10] => ram_block1a6.PORTBADDR10
address_b[10] => ram_block1a7.PORTBADDR10
address_b[10] => ram_block1a8.PORTBADDR10
address_b[10] => ram_block1a9.PORTBADDR10
address_b[10] => ram_block1a10.PORTBADDR10
address_b[10] => ram_block1a11.PORTBADDR10
address_b[10] => ram_block1a12.PORTBADDR10
address_b[10] => ram_block1a13.PORTBADDR10
address_b[10] => ram_block1a14.PORTBADDR10
address_b[10] => ram_block1a15.PORTBADDR10
address_b[11] => ram_block1a0.PORTBADDR11
address_b[11] => ram_block1a1.PORTBADDR11
address_b[11] => ram_block1a2.PORTBADDR11
address_b[11] => ram_block1a3.PORTBADDR11
address_b[11] => ram_block1a4.PORTBADDR11
address_b[11] => ram_block1a5.PORTBADDR11
address_b[11] => ram_block1a6.PORTBADDR11
address_b[11] => ram_block1a7.PORTBADDR11
address_b[11] => ram_block1a8.PORTBADDR11
address_b[11] => ram_block1a9.PORTBADDR11
address_b[11] => ram_block1a10.PORTBADDR11
address_b[11] => ram_block1a11.PORTBADDR11
address_b[11] => ram_block1a12.PORTBADDR11
address_b[11] => ram_block1a13.PORTBADDR11
address_b[11] => ram_block1a14.PORTBADDR11
address_b[11] => ram_block1a15.PORTBADDR11
address_b[12] => ram_block1a0.PORTBADDR12
address_b[12] => ram_block1a1.PORTBADDR12
address_b[12] => ram_block1a2.PORTBADDR12
address_b[12] => ram_block1a3.PORTBADDR12
address_b[12] => ram_block1a4.PORTBADDR12
address_b[12] => ram_block1a5.PORTBADDR12
address_b[12] => ram_block1a6.PORTBADDR12
address_b[12] => ram_block1a7.PORTBADDR12
address_b[12] => ram_block1a8.PORTBADDR12
address_b[12] => ram_block1a9.PORTBADDR12
address_b[12] => ram_block1a10.PORTBADDR12
address_b[12] => ram_block1a11.PORTBADDR12
address_b[12] => ram_block1a12.PORTBADDR12
address_b[12] => ram_block1a13.PORTBADDR12
address_b[12] => ram_block1a14.PORTBADDR12
address_b[12] => ram_block1a15.PORTBADDR12
address_b[13] => address_reg_b[0].DATAIN
address_b[13] => decode_jsa:decode3.data[0]
address_b[13] => decode_c8a:rden_decode_b.data[0]
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a0.CLK1
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a1.CLK1
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a2.CLK1
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a3.CLK1
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a4.CLK1
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a5.CLK1
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a6.CLK1
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a7.CLK1
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a8.CLK1
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a9.CLK1
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a10.CLK1
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a11.CLK1
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a12.CLK1
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a13.CLK1
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a14.CLK1
clock0 => ram_block1a15.CLK0
clock0 => ram_block1a15.CLK1
clock0 => address_reg_a[0].CLK
clock0 => address_reg_b[0].CLK
clock0 => out_address_reg_a[0].CLK
clock0 => out_address_reg_b[0].CLK
data_a[0] => ram_block1a0.PORTADATAIN
data_a[0] => ram_block1a8.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[1] => ram_block1a9.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[2] => ram_block1a10.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[3] => ram_block1a11.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[4] => ram_block1a12.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[5] => ram_block1a13.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[6] => ram_block1a14.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
data_a[7] => ram_block1a15.PORTADATAIN
data_b[0] => ram_block1a0.PORTBDATAIN
data_b[0] => ram_block1a8.PORTBDATAIN
data_b[1] => ram_block1a1.PORTBDATAIN
data_b[1] => ram_block1a9.PORTBDATAIN
data_b[2] => ram_block1a2.PORTBDATAIN
data_b[2] => ram_block1a10.PORTBDATAIN
data_b[3] => ram_block1a3.PORTBDATAIN
data_b[3] => ram_block1a11.PORTBDATAIN
data_b[4] => ram_block1a4.PORTBDATAIN
data_b[4] => ram_block1a12.PORTBDATAIN
data_b[5] => ram_block1a5.PORTBDATAIN
data_b[5] => ram_block1a13.PORTBDATAIN
data_b[6] => ram_block1a6.PORTBDATAIN
data_b[6] => ram_block1a14.PORTBDATAIN
data_b[7] => ram_block1a7.PORTBDATAIN
data_b[7] => ram_block1a15.PORTBDATAIN
q_a[0] <= mux_3nb:mux4.result[0]
q_a[1] <= mux_3nb:mux4.result[1]
q_a[2] <= mux_3nb:mux4.result[2]
q_a[3] <= mux_3nb:mux4.result[3]
q_a[4] <= mux_3nb:mux4.result[4]
q_a[5] <= mux_3nb:mux4.result[5]
q_a[6] <= mux_3nb:mux4.result[6]
q_a[7] <= mux_3nb:mux4.result[7]
q_b[0] <= mux_3nb:mux5.result[0]
q_b[1] <= mux_3nb:mux5.result[1]
q_b[2] <= mux_3nb:mux5.result[2]
q_b[3] <= mux_3nb:mux5.result[3]
q_b[4] <= mux_3nb:mux5.result[4]
q_b[5] <= mux_3nb:mux5.result[5]
q_b[6] <= mux_3nb:mux5.result[6]
q_b[7] <= mux_3nb:mux5.result[7]
wren_a => decode_jsa:decode2.enable
wren_b => decode_jsa:decode3.enable


|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2
data[0] => eq_node[1].IN0
data[0] => eq_node[0].IN0
enable => eq_node[1].IN1
enable => eq_node[0].IN1
eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE


|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode3
data[0] => eq_node[1].IN0
data[0] => eq_node[0].IN0
enable => eq_node[1].IN1
enable => eq_node[0].IN1
eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE


|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_c8a:rden_decode_a
data[0] => eq_node[1].IN0
data[0] => eq_node[0].IN0
eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE


|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_c8a:rden_decode_b
data[0] => eq_node[1].IN0
data[0] => eq_node[0].IN0
eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE


|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|mux_3nb:mux4
data[0] => result_node[0].IN1
data[1] => result_node[1].IN1
data[2] => result_node[2].IN1
data[3] => result_node[3].IN1
data[4] => result_node[4].IN1
data[5] => result_node[5].IN1
data[6] => result_node[6].IN1
data[7] => result_node[7].IN1
data[8] => result_node[0].IN1
data[9] => result_node[1].IN1
data[10] => result_node[2].IN1
data[11] => result_node[3].IN1
data[12] => result_node[4].IN1
data[13] => result_node[5].IN1
data[14] => result_node[6].IN1
data[15] => result_node[7].IN1
result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE
sel[0] => result_node[7].IN0
sel[0] => _.IN0
sel[0] => result_node[6].IN0
sel[0] => _.IN0
sel[0] => result_node[5].IN0
sel[0] => _.IN0
sel[0] => result_node[4].IN0
sel[0] => _.IN0
sel[0] => result_node[3].IN0
sel[0] => _.IN0
sel[0] => result_node[2].IN0
sel[0] => _.IN0
sel[0] => result_node[1].IN0
sel[0] => _.IN0
sel[0] => result_node[0].IN0
sel[0] => _.IN0


|spectrum|ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|mux_3nb:mux5
data[0] => result_node[0].IN1
data[1] => result_node[1].IN1
data[2] => result_node[2].IN1
data[3] => result_node[3].IN1
data[4] => result_node[4].IN1
data[5] => result_node[5].IN1
data[6] => result_node[6].IN1
data[7] => result_node[7].IN1
data[8] => result_node[0].IN1
data[9] => result_node[1].IN1
data[10] => result_node[2].IN1
data[11] => result_node[3].IN1
data[12] => result_node[4].IN1
data[13] => result_node[5].IN1
data[14] => result_node[6].IN1
data[15] => result_node[7].IN1
result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE
sel[0] => result_node[7].IN0
sel[0] => _.IN0
sel[0] => result_node[6].IN0
sel[0] => _.IN0
sel[0] => result_node[5].IN0
sel[0] => _.IN0
sel[0] => result_node[4].IN0
sel[0] => _.IN0
sel[0] => result_node[3].IN0
sel[0] => _.IN0
sel[0] => result_node[2].IN0
sel[0] => _.IN0
sel[0] => result_node[1].IN0
sel[0] => _.IN0
sel[0] => result_node[0].IN0
sel[0] => _.IN0


|spectrum|ram32:ram1
address[0] => address[0].IN1
address[1] => address[1].IN1
address[2] => address[2].IN1
address[3] => address[3].IN1
address[4] => address[4].IN1
address[5] => address[5].IN1
address[6] => address[6].IN1
address[7] => address[7].IN1
address[8] => address[8].IN1
address[9] => address[9].IN1
address[10] => address[10].IN1
address[11] => address[11].IN1
address[12] => address[12].IN1
address[13] => address[13].IN1
address[14] => address[14].IN1
clock => clock.IN1
data[0] => data[0].IN1
data[1] => data[1].IN1
data[2] => data[2].IN1
data[3] => data[3].IN1
data[4] => data[4].IN1
data[5] => data[5].IN1
data[6] => data[6].IN1
data[7] => data[7].IN1
wren => wren.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a


|spectrum|ram32:ram1|altsyncram:altsyncram_component
wren_a => altsyncram_g9i1:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_g9i1:auto_generated.data_a[0]
data_a[1] => altsyncram_g9i1:auto_generated.data_a[1]
data_a[2] => altsyncram_g9i1:auto_generated.data_a[2]
data_a[3] => altsyncram_g9i1:auto_generated.data_a[3]
data_a[4] => altsyncram_g9i1:auto_generated.data_a[4]
data_a[5] => altsyncram_g9i1:auto_generated.data_a[5]
data_a[6] => altsyncram_g9i1:auto_generated.data_a[6]
data_a[7] => altsyncram_g9i1:auto_generated.data_a[7]
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_g9i1:auto_generated.address_a[0]
address_a[1] => altsyncram_g9i1:auto_generated.address_a[1]
address_a[2] => altsyncram_g9i1:auto_generated.address_a[2]
address_a[3] => altsyncram_g9i1:auto_generated.address_a[3]
address_a[4] => altsyncram_g9i1:auto_generated.address_a[4]
address_a[5] => altsyncram_g9i1:auto_generated.address_a[5]
address_a[6] => altsyncram_g9i1:auto_generated.address_a[6]
address_a[7] => altsyncram_g9i1:auto_generated.address_a[7]
address_a[8] => altsyncram_g9i1:auto_generated.address_a[8]
address_a[9] => altsyncram_g9i1:auto_generated.address_a[9]
address_a[10] => altsyncram_g9i1:auto_generated.address_a[10]
address_a[11] => altsyncram_g9i1:auto_generated.address_a[11]
address_a[12] => altsyncram_g9i1:auto_generated.address_a[12]
address_a[13] => altsyncram_g9i1:auto_generated.address_a[13]
address_a[14] => altsyncram_g9i1:auto_generated.address_a[14]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_g9i1:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_g9i1:auto_generated.q_a[0]
q_a[1] <= altsyncram_g9i1:auto_generated.q_a[1]
q_a[2] <= altsyncram_g9i1:auto_generated.q_a[2]
q_a[3] <= altsyncram_g9i1:auto_generated.q_a[3]
q_a[4] <= altsyncram_g9i1:auto_generated.q_a[4]
q_a[5] <= altsyncram_g9i1:auto_generated.q_a[5]
q_a[6] <= altsyncram_g9i1:auto_generated.q_a[6]
q_a[7] <= altsyncram_g9i1:auto_generated.q_a[7]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[0] => ram_block1a16.PORTAADDR
address_a[0] => ram_block1a17.PORTAADDR
address_a[0] => ram_block1a18.PORTAADDR
address_a[0] => ram_block1a19.PORTAADDR
address_a[0] => ram_block1a20.PORTAADDR
address_a[0] => ram_block1a21.PORTAADDR
address_a[0] => ram_block1a22.PORTAADDR
address_a[0] => ram_block1a23.PORTAADDR
address_a[0] => ram_block1a24.PORTAADDR
address_a[0] => ram_block1a25.PORTAADDR
address_a[0] => ram_block1a26.PORTAADDR
address_a[0] => ram_block1a27.PORTAADDR
address_a[0] => ram_block1a28.PORTAADDR
address_a[0] => ram_block1a29.PORTAADDR
address_a[0] => ram_block1a30.PORTAADDR
address_a[0] => ram_block1a31.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[1] => ram_block1a16.PORTAADDR1
address_a[1] => ram_block1a17.PORTAADDR1
address_a[1] => ram_block1a18.PORTAADDR1
address_a[1] => ram_block1a19.PORTAADDR1
address_a[1] => ram_block1a20.PORTAADDR1
address_a[1] => ram_block1a21.PORTAADDR1
address_a[1] => ram_block1a22.PORTAADDR1
address_a[1] => ram_block1a23.PORTAADDR1
address_a[1] => ram_block1a24.PORTAADDR1
address_a[1] => ram_block1a25.PORTAADDR1
address_a[1] => ram_block1a26.PORTAADDR1
address_a[1] => ram_block1a27.PORTAADDR1
address_a[1] => ram_block1a28.PORTAADDR1
address_a[1] => ram_block1a29.PORTAADDR1
address_a[1] => ram_block1a30.PORTAADDR1
address_a[1] => ram_block1a31.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[2] => ram_block1a16.PORTAADDR2
address_a[2] => ram_block1a17.PORTAADDR2
address_a[2] => ram_block1a18.PORTAADDR2
address_a[2] => ram_block1a19.PORTAADDR2
address_a[2] => ram_block1a20.PORTAADDR2
address_a[2] => ram_block1a21.PORTAADDR2
address_a[2] => ram_block1a22.PORTAADDR2
address_a[2] => ram_block1a23.PORTAADDR2
address_a[2] => ram_block1a24.PORTAADDR2
address_a[2] => ram_block1a25.PORTAADDR2
address_a[2] => ram_block1a26.PORTAADDR2
address_a[2] => ram_block1a27.PORTAADDR2
address_a[2] => ram_block1a28.PORTAADDR2
address_a[2] => ram_block1a29.PORTAADDR2
address_a[2] => ram_block1a30.PORTAADDR2
address_a[2] => ram_block1a31.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[3] => ram_block1a16.PORTAADDR3
address_a[3] => ram_block1a17.PORTAADDR3
address_a[3] => ram_block1a18.PORTAADDR3
address_a[3] => ram_block1a19.PORTAADDR3
address_a[3] => ram_block1a20.PORTAADDR3
address_a[3] => ram_block1a21.PORTAADDR3
address_a[3] => ram_block1a22.PORTAADDR3
address_a[3] => ram_block1a23.PORTAADDR3
address_a[3] => ram_block1a24.PORTAADDR3
address_a[3] => ram_block1a25.PORTAADDR3
address_a[3] => ram_block1a26.PORTAADDR3
address_a[3] => ram_block1a27.PORTAADDR3
address_a[3] => ram_block1a28.PORTAADDR3
address_a[3] => ram_block1a29.PORTAADDR3
address_a[3] => ram_block1a30.PORTAADDR3
address_a[3] => ram_block1a31.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
address_a[4] => ram_block1a16.PORTAADDR4
address_a[4] => ram_block1a17.PORTAADDR4
address_a[4] => ram_block1a18.PORTAADDR4
address_a[4] => ram_block1a19.PORTAADDR4
address_a[4] => ram_block1a20.PORTAADDR4
address_a[4] => ram_block1a21.PORTAADDR4
address_a[4] => ram_block1a22.PORTAADDR4
address_a[4] => ram_block1a23.PORTAADDR4
address_a[4] => ram_block1a24.PORTAADDR4
address_a[4] => ram_block1a25.PORTAADDR4
address_a[4] => ram_block1a26.PORTAADDR4
address_a[4] => ram_block1a27.PORTAADDR4
address_a[4] => ram_block1a28.PORTAADDR4
address_a[4] => ram_block1a29.PORTAADDR4
address_a[4] => ram_block1a30.PORTAADDR4
address_a[4] => ram_block1a31.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[5] => ram_block1a12.PORTAADDR5
address_a[5] => ram_block1a13.PORTAADDR5
address_a[5] => ram_block1a14.PORTAADDR5
address_a[5] => ram_block1a15.PORTAADDR5
address_a[5] => ram_block1a16.PORTAADDR5
address_a[5] => ram_block1a17.PORTAADDR5
address_a[5] => ram_block1a18.PORTAADDR5
address_a[5] => ram_block1a19.PORTAADDR5
address_a[5] => ram_block1a20.PORTAADDR5
address_a[5] => ram_block1a21.PORTAADDR5
address_a[5] => ram_block1a22.PORTAADDR5
address_a[5] => ram_block1a23.PORTAADDR5
address_a[5] => ram_block1a24.PORTAADDR5
address_a[5] => ram_block1a25.PORTAADDR5
address_a[5] => ram_block1a26.PORTAADDR5
address_a[5] => ram_block1a27.PORTAADDR5
address_a[5] => ram_block1a28.PORTAADDR5
address_a[5] => ram_block1a29.PORTAADDR5
address_a[5] => ram_block1a30.PORTAADDR5
address_a[5] => ram_block1a31.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[6] => ram_block1a10.PORTAADDR6
address_a[6] => ram_block1a11.PORTAADDR6
address_a[6] => ram_block1a12.PORTAADDR6
address_a[6] => ram_block1a13.PORTAADDR6
address_a[6] => ram_block1a14.PORTAADDR6
address_a[6] => ram_block1a15.PORTAADDR6
address_a[6] => ram_block1a16.PORTAADDR6
address_a[6] => ram_block1a17.PORTAADDR6
address_a[6] => ram_block1a18.PORTAADDR6
address_a[6] => ram_block1a19.PORTAADDR6
address_a[6] => ram_block1a20.PORTAADDR6
address_a[6] => ram_block1a21.PORTAADDR6
address_a[6] => ram_block1a22.PORTAADDR6
address_a[6] => ram_block1a23.PORTAADDR6
address_a[6] => ram_block1a24.PORTAADDR6
address_a[6] => ram_block1a25.PORTAADDR6
address_a[6] => ram_block1a26.PORTAADDR6
address_a[6] => ram_block1a27.PORTAADDR6
address_a[6] => ram_block1a28.PORTAADDR6
address_a[6] => ram_block1a29.PORTAADDR6
address_a[6] => ram_block1a30.PORTAADDR6
address_a[6] => ram_block1a31.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[7] => ram_block1a10.PORTAADDR7
address_a[7] => ram_block1a11.PORTAADDR7
address_a[7] => ram_block1a12.PORTAADDR7
address_a[7] => ram_block1a13.PORTAADDR7
address_a[7] => ram_block1a14.PORTAADDR7
address_a[7] => ram_block1a15.PORTAADDR7
address_a[7] => ram_block1a16.PORTAADDR7
address_a[7] => ram_block1a17.PORTAADDR7
address_a[7] => ram_block1a18.PORTAADDR7
address_a[7] => ram_block1a19.PORTAADDR7
address_a[7] => ram_block1a20.PORTAADDR7
address_a[7] => ram_block1a21.PORTAADDR7
address_a[7] => ram_block1a22.PORTAADDR7
address_a[7] => ram_block1a23.PORTAADDR7
address_a[7] => ram_block1a24.PORTAADDR7
address_a[7] => ram_block1a25.PORTAADDR7
address_a[7] => ram_block1a26.PORTAADDR7
address_a[7] => ram_block1a27.PORTAADDR7
address_a[7] => ram_block1a28.PORTAADDR7
address_a[7] => ram_block1a29.PORTAADDR7
address_a[7] => ram_block1a30.PORTAADDR7
address_a[7] => ram_block1a31.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[8] => ram_block1a8.PORTAADDR8
address_a[8] => ram_block1a9.PORTAADDR8
address_a[8] => ram_block1a10.PORTAADDR8
address_a[8] => ram_block1a11.PORTAADDR8
address_a[8] => ram_block1a12.PORTAADDR8
address_a[8] => ram_block1a13.PORTAADDR8
address_a[8] => ram_block1a14.PORTAADDR8
address_a[8] => ram_block1a15.PORTAADDR8
address_a[8] => ram_block1a16.PORTAADDR8
address_a[8] => ram_block1a17.PORTAADDR8
address_a[8] => ram_block1a18.PORTAADDR8
address_a[8] => ram_block1a19.PORTAADDR8
address_a[8] => ram_block1a20.PORTAADDR8
address_a[8] => ram_block1a21.PORTAADDR8
address_a[8] => ram_block1a22.PORTAADDR8
address_a[8] => ram_block1a23.PORTAADDR8
address_a[8] => ram_block1a24.PORTAADDR8
address_a[8] => ram_block1a25.PORTAADDR8
address_a[8] => ram_block1a26.PORTAADDR8
address_a[8] => ram_block1a27.PORTAADDR8
address_a[8] => ram_block1a28.PORTAADDR8
address_a[8] => ram_block1a29.PORTAADDR8
address_a[8] => ram_block1a30.PORTAADDR8
address_a[8] => ram_block1a31.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_a[9] => ram_block1a8.PORTAADDR9
address_a[9] => ram_block1a9.PORTAADDR9
address_a[9] => ram_block1a10.PORTAADDR9
address_a[9] => ram_block1a11.PORTAADDR9
address_a[9] => ram_block1a12.PORTAADDR9
address_a[9] => ram_block1a13.PORTAADDR9
address_a[9] => ram_block1a14.PORTAADDR9
address_a[9] => ram_block1a15.PORTAADDR9
address_a[9] => ram_block1a16.PORTAADDR9
address_a[9] => ram_block1a17.PORTAADDR9
address_a[9] => ram_block1a18.PORTAADDR9
address_a[9] => ram_block1a19.PORTAADDR9
address_a[9] => ram_block1a20.PORTAADDR9
address_a[9] => ram_block1a21.PORTAADDR9
address_a[9] => ram_block1a22.PORTAADDR9
address_a[9] => ram_block1a23.PORTAADDR9
address_a[9] => ram_block1a24.PORTAADDR9
address_a[9] => ram_block1a25.PORTAADDR9
address_a[9] => ram_block1a26.PORTAADDR9
address_a[9] => ram_block1a27.PORTAADDR9
address_a[9] => ram_block1a28.PORTAADDR9
address_a[9] => ram_block1a29.PORTAADDR9
address_a[9] => ram_block1a30.PORTAADDR9
address_a[9] => ram_block1a31.PORTAADDR9
address_a[10] => ram_block1a0.PORTAADDR10
address_a[10] => ram_block1a1.PORTAADDR10
address_a[10] => ram_block1a2.PORTAADDR10
address_a[10] => ram_block1a3.PORTAADDR10
address_a[10] => ram_block1a4.PORTAADDR10
address_a[10] => ram_block1a5.PORTAADDR10
address_a[10] => ram_block1a6.PORTAADDR10
address_a[10] => ram_block1a7.PORTAADDR10
address_a[10] => ram_block1a8.PORTAADDR10
address_a[10] => ram_block1a9.PORTAADDR10
address_a[10] => ram_block1a10.PORTAADDR10
address_a[10] => ram_block1a11.PORTAADDR10
address_a[10] => ram_block1a12.PORTAADDR10
address_a[10] => ram_block1a13.PORTAADDR10
address_a[10] => ram_block1a14.PORTAADDR10
address_a[10] => ram_block1a15.PORTAADDR10
address_a[10] => ram_block1a16.PORTAADDR10
address_a[10] => ram_block1a17.PORTAADDR10
address_a[10] => ram_block1a18.PORTAADDR10
address_a[10] => ram_block1a19.PORTAADDR10
address_a[10] => ram_block1a20.PORTAADDR10
address_a[10] => ram_block1a21.PORTAADDR10
address_a[10] => ram_block1a22.PORTAADDR10
address_a[10] => ram_block1a23.PORTAADDR10
address_a[10] => ram_block1a24.PORTAADDR10
address_a[10] => ram_block1a25.PORTAADDR10
address_a[10] => ram_block1a26.PORTAADDR10
address_a[10] => ram_block1a27.PORTAADDR10
address_a[10] => ram_block1a28.PORTAADDR10
address_a[10] => ram_block1a29.PORTAADDR10
address_a[10] => ram_block1a30.PORTAADDR10
address_a[10] => ram_block1a31.PORTAADDR10
address_a[11] => ram_block1a0.PORTAADDR11
address_a[11] => ram_block1a1.PORTAADDR11
address_a[11] => ram_block1a2.PORTAADDR11
address_a[11] => ram_block1a3.PORTAADDR11
address_a[11] => ram_block1a4.PORTAADDR11
address_a[11] => ram_block1a5.PORTAADDR11
address_a[11] => ram_block1a6.PORTAADDR11
address_a[11] => ram_block1a7.PORTAADDR11
address_a[11] => ram_block1a8.PORTAADDR11
address_a[11] => ram_block1a9.PORTAADDR11
address_a[11] => ram_block1a10.PORTAADDR11
address_a[11] => ram_block1a11.PORTAADDR11
address_a[11] => ram_block1a12.PORTAADDR11
address_a[11] => ram_block1a13.PORTAADDR11
address_a[11] => ram_block1a14.PORTAADDR11
address_a[11] => ram_block1a15.PORTAADDR11
address_a[11] => ram_block1a16.PORTAADDR11
address_a[11] => ram_block1a17.PORTAADDR11
address_a[11] => ram_block1a18.PORTAADDR11
address_a[11] => ram_block1a19.PORTAADDR11
address_a[11] => ram_block1a20.PORTAADDR11
address_a[11] => ram_block1a21.PORTAADDR11
address_a[11] => ram_block1a22.PORTAADDR11
address_a[11] => ram_block1a23.PORTAADDR11
address_a[11] => ram_block1a24.PORTAADDR11
address_a[11] => ram_block1a25.PORTAADDR11
address_a[11] => ram_block1a26.PORTAADDR11
address_a[11] => ram_block1a27.PORTAADDR11
address_a[11] => ram_block1a28.PORTAADDR11
address_a[11] => ram_block1a29.PORTAADDR11
address_a[11] => ram_block1a30.PORTAADDR11
address_a[11] => ram_block1a31.PORTAADDR11
address_a[12] => ram_block1a0.PORTAADDR12
address_a[12] => ram_block1a1.PORTAADDR12
address_a[12] => ram_block1a2.PORTAADDR12
address_a[12] => ram_block1a3.PORTAADDR12
address_a[12] => ram_block1a4.PORTAADDR12
address_a[12] => ram_block1a5.PORTAADDR12
address_a[12] => ram_block1a6.PORTAADDR12
address_a[12] => ram_block1a7.PORTAADDR12
address_a[12] => ram_block1a8.PORTAADDR12
address_a[12] => ram_block1a9.PORTAADDR12
address_a[12] => ram_block1a10.PORTAADDR12
address_a[12] => ram_block1a11.PORTAADDR12
address_a[12] => ram_block1a12.PORTAADDR12
address_a[12] => ram_block1a13.PORTAADDR12
address_a[12] => ram_block1a14.PORTAADDR12
address_a[12] => ram_block1a15.PORTAADDR12
address_a[12] => ram_block1a16.PORTAADDR12
address_a[12] => ram_block1a17.PORTAADDR12
address_a[12] => ram_block1a18.PORTAADDR12
address_a[12] => ram_block1a19.PORTAADDR12
address_a[12] => ram_block1a20.PORTAADDR12
address_a[12] => ram_block1a21.PORTAADDR12
address_a[12] => ram_block1a22.PORTAADDR12
address_a[12] => ram_block1a23.PORTAADDR12
address_a[12] => ram_block1a24.PORTAADDR12
address_a[12] => ram_block1a25.PORTAADDR12
address_a[12] => ram_block1a26.PORTAADDR12
address_a[12] => ram_block1a27.PORTAADDR12
address_a[12] => ram_block1a28.PORTAADDR12
address_a[12] => ram_block1a29.PORTAADDR12
address_a[12] => ram_block1a30.PORTAADDR12
address_a[12] => ram_block1a31.PORTAADDR12
address_a[13] => address_reg_a[0].DATAIN
address_a[13] => decode_msa:decode3.data[0]
address_a[13] => decode_f8a:rden_decode.data[0]
address_a[14] => address_reg_a[1].DATAIN
address_a[14] => decode_msa:decode3.data[1]
address_a[14] => decode_f8a:rden_decode.data[1]
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
clock0 => ram_block1a16.CLK0
clock0 => ram_block1a17.CLK0
clock0 => ram_block1a18.CLK0
clock0 => ram_block1a19.CLK0
clock0 => ram_block1a20.CLK0
clock0 => ram_block1a21.CLK0
clock0 => ram_block1a22.CLK0
clock0 => ram_block1a23.CLK0
clock0 => ram_block1a24.CLK0
clock0 => ram_block1a25.CLK0
clock0 => ram_block1a26.CLK0
clock0 => ram_block1a27.CLK0
clock0 => ram_block1a28.CLK0
clock0 => ram_block1a29.CLK0
clock0 => ram_block1a30.CLK0
clock0 => ram_block1a31.CLK0
clock0 => address_reg_a[1].CLK
clock0 => address_reg_a[0].CLK
clock0 => out_address_reg_a[1].CLK
clock0 => out_address_reg_a[0].CLK
data_a[0] => ram_block1a0.PORTADATAIN
data_a[0] => ram_block1a8.PORTADATAIN
data_a[0] => ram_block1a16.PORTADATAIN
data_a[0] => ram_block1a24.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[1] => ram_block1a9.PORTADATAIN
data_a[1] => ram_block1a17.PORTADATAIN
data_a[1] => ram_block1a25.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[2] => ram_block1a10.PORTADATAIN
data_a[2] => ram_block1a18.PORTADATAIN
data_a[2] => ram_block1a26.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[3] => ram_block1a11.PORTADATAIN
data_a[3] => ram_block1a19.PORTADATAIN
data_a[3] => ram_block1a27.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[4] => ram_block1a12.PORTADATAIN
data_a[4] => ram_block1a20.PORTADATAIN
data_a[4] => ram_block1a28.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[5] => ram_block1a13.PORTADATAIN
data_a[5] => ram_block1a21.PORTADATAIN
data_a[5] => ram_block1a29.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[6] => ram_block1a14.PORTADATAIN
data_a[6] => ram_block1a22.PORTADATAIN
data_a[6] => ram_block1a30.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
data_a[7] => ram_block1a15.PORTADATAIN
data_a[7] => ram_block1a23.PORTADATAIN
data_a[7] => ram_block1a31.PORTADATAIN
q_a[0] <= mux_6nb:mux2.result[0]
q_a[1] <= mux_6nb:mux2.result[1]
q_a[2] <= mux_6nb:mux2.result[2]
q_a[3] <= mux_6nb:mux2.result[3]
q_a[4] <= mux_6nb:mux2.result[4]
q_a[5] <= mux_6nb:mux2.result[5]
q_a[6] <= mux_6nb:mux2.result[6]
q_a[7] <= mux_6nb:mux2.result[7]
wren_a => decode_msa:decode3.enable


|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3
data[0] => w_anode223w[1].IN0
data[0] => w_anode236w[1].IN1
data[0] => w_anode244w[1].IN0
data[0] => w_anode252w[1].IN1
data[1] => w_anode223w[2].IN0
data[1] => w_anode236w[2].IN0
data[1] => w_anode244w[2].IN1
data[1] => w_anode252w[2].IN1
enable => w_anode223w[1].IN0
enable => w_anode236w[1].IN0
enable => w_anode244w[1].IN0
enable => w_anode252w[1].IN0
eq[0] <= w_anode223w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= w_anode236w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[2] <= w_anode244w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[3] <= w_anode252w[2].DB_MAX_OUTPUT_PORT_TYPE


|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_f8a:rden_decode
data[0] => w_anode261w[1].IN0
data[0] => w_anode275w[1].IN1
data[0] => w_anode284w[1].IN0
data[0] => w_anode293w[1].IN1
data[1] => w_anode261w[2].IN0
data[1] => w_anode275w[2].IN0
data[1] => w_anode284w[2].IN1
data[1] => w_anode293w[2].IN1
eq[0] <= w_anode261w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= w_anode275w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[2] <= w_anode284w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[3] <= w_anode293w[2].DB_MAX_OUTPUT_PORT_TYPE


|spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|mux_6nb:mux2
data[0] => _.IN0
data[0] => _.IN0
data[1] => _.IN0
data[1] => _.IN0
data[2] => _.IN0
data[2] => _.IN0
data[3] => _.IN0
data[3] => _.IN0
data[4] => _.IN0
data[4] => _.IN0
data[5] => _.IN0
data[5] => _.IN0
data[6] => _.IN0
data[6] => _.IN0
data[7] => _.IN0
data[7] => _.IN0
data[8] => _.IN0
data[9] => _.IN0
data[10] => _.IN0
data[11] => _.IN0
data[12] => _.IN0
data[13] => _.IN0
data[14] => _.IN0
data[15] => _.IN0
data[16] => _.IN1
data[16] => _.IN1
data[17] => _.IN1
data[17] => _.IN1
data[18] => _.IN1
data[18] => _.IN1
data[19] => _.IN1
data[19] => _.IN1
data[20] => _.IN1
data[20] => _.IN1
data[21] => _.IN1
data[21] => _.IN1
data[22] => _.IN1
data[22] => _.IN1
data[23] => _.IN1
data[23] => _.IN1
data[24] => _.IN0
data[25] => _.IN0
data[26] => _.IN0
data[27] => _.IN0
data[28] => _.IN0
data[29] => _.IN0
data[30] => _.IN0
data[31] => _.IN0
result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0


|spectrum|sdram_controller:sdram_
CLOCK_50 => sdram_clk_gen:sdram_clk_pll.inclk0
DRAM_ADDR[0] <= r.address[0].DB_MAX_OUTPUT_PORT_TYPE
DRAM_ADDR[1] <= r.address[1].DB_MAX_OUTPUT_PORT_TYPE
DRAM_ADDR[2] <= r.address[2].DB_MAX_OUTPUT_PORT_TYPE
DRAM_ADDR[3] <= r.address[3].DB_MAX_OUTPUT_PORT_TYPE
DRAM_ADDR[4] <= r.address[4].DB_MAX_OUTPUT_PORT_TYPE
DRAM_ADDR[5] <= r.address[5].DB_MAX_OUTPUT_PORT_TYPE
DRAM_ADDR[6] <= r.address[6].DB_MAX_OUTPUT_PORT_TYPE
DRAM_ADDR[7] <= r.address[7].DB_MAX_OUTPUT_PORT_TYPE
DRAM_ADDR[8] <= r.address[8].DB_MAX_OUTPUT_PORT_TYPE
DRAM_ADDR[9] <= r.address[9].DB_MAX_OUTPUT_PORT_TYPE
DRAM_ADDR[10] <= r.address[10].DB_MAX_OUTPUT_PORT_TYPE
DRAM_ADDR[11] <= r.address[11].DB_MAX_OUTPUT_PORT_TYPE
DRAM_ADDR[12] <= r.address[12].DB_MAX_OUTPUT_PORT_TYPE
DRAM_BA[0] <= r.bank[0].DB_MAX_OUTPUT_PORT_TYPE
DRAM_BA[1] <= r.bank[1].DB_MAX_OUTPUT_PORT_TYPE
DRAM_CAS_N <= r.state[1].DB_MAX_OUTPUT_PORT_TYPE
DRAM_CKE <= <VCC>
DRAM_CLK <= sdram_clk_gen:sdram_clk_pll.c1
DRAM_CS_N <= r.state[3].DB_MAX_OUTPUT_PORT_TYPE
DRAM_DQ[0] <> DRAM_DQ[0]
DRAM_DQ[1] <> DRAM_DQ[1]
DRAM_DQ[2] <> DRAM_DQ[2]
DRAM_DQ[3] <> DRAM_DQ[3]
DRAM_DQ[4] <> DRAM_DQ[4]
DRAM_DQ[5] <> DRAM_DQ[5]
DRAM_DQ[6] <> DRAM_DQ[6]
DRAM_DQ[7] <> DRAM_DQ[7]
DRAM_DQ[8] <> DRAM_DQ[8]
DRAM_DQ[9] <> DRAM_DQ[9]
DRAM_DQ[10] <> DRAM_DQ[10]
DRAM_DQ[11] <> DRAM_DQ[11]
DRAM_DQ[12] <> DRAM_DQ[12]
DRAM_DQ[13] <> DRAM_DQ[13]
DRAM_DQ[14] <> DRAM_DQ[14]
DRAM_DQ[15] <> DRAM_DQ[15]
DRAM_DQM[0] <= r.dq_masks[0].DB_MAX_OUTPUT_PORT_TYPE
DRAM_DQM[1] <= r.dq_masks[1].DB_MAX_OUTPUT_PORT_TYPE
DRAM_RAS_N <= r.state[2].DB_MAX_OUTPUT_PORT_TYPE
DRAM_WE_N <= r.state[0].DB_MAX_OUTPUT_PORT_TYPE
address[0] => ~NO_FANOUT~
address[1] => n.DATAB
address[1] => n.DATAB
address[1] => Mux22.IN36
address[2] => n.DATAB
address[2] => n.DATAB
address[2] => Mux21.IN36
address[3] => n.DATAB
address[3] => n.DATAB
address[3] => Mux20.IN36
address[4] => n.DATAB
address[4] => n.DATAB
address[4] => Mux19.IN36
address[5] => n.DATAB
address[5] => n.DATAB
address[5] => Mux18.IN36
address[6] => n.DATAB
address[6] => n.DATAB
address[6] => Mux17.IN36
address[7] => n.DATAB
address[7] => n.DATAB
address[7] => Mux16.IN36
address[8] => n.DATAB
address[8] => n.DATAB
address[8] => Mux15.IN36
address[9] => n.DATAB
address[9] => n.DATAB
address[9] => n.DATAB
address[9] => Mux26.IN36
address[10] => n.DATAB
address[10] => n.DATAB
address[10] => n.DATAB
address[10] => Mux25.IN36
address[11] => Equal7.IN25
address[11] => n.DATAB
address[11] => n.DATAB
address[12] => Equal7.IN24
address[12] => n.DATAB
address[12] => n.DATAB
address[13] => Equal7.IN23
address[13] => n.DATAB
address[13] => n.DATAB
address[14] => Equal7.IN22
address[14] => n.DATAB
address[14] => n.DATAB
address[15] => Equal7.IN21
address[15] => n.DATAB
address[15] => n.DATAB
address[16] => Equal7.IN20
address[16] => n.DATAB
address[16] => n.DATAB
address[17] => Equal7.IN19
address[17] => n.DATAB
address[17] => n.DATAB
address[18] => Equal7.IN18
address[18] => n.DATAB
address[18] => n.DATAB
address[19] => Equal7.IN17
address[19] => n.DATAB
address[19] => n.DATAB
address[20] => Equal7.IN16
address[20] => n.DATAB
address[20] => n.DATAB
address[21] => Equal7.IN15
address[21] => n.DATAB
address[21] => n.DATAB
address[22] => Equal7.IN14
address[22] => n.DATAB
address[22] => n.DATAB
address[23] => Equal7.IN13
address[23] => n.DATAB
address[23] => n.DATAB
req_read => n.OUTPUTSELECT
req_read => n.OUTPUTSELECT
req_write => n.OUTPUTSELECT
req_write => n.OUTPUTSELECT
data_out[0] <= r.data_out_low[0].DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= r.data_out_low[1].DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= r.data_out_low[2].DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= r.data_out_low[3].DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= r.data_out_low[4].DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= r.data_out_low[5].DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= r.data_out_low[6].DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= r.data_out_low[7].DB_MAX_OUTPUT_PORT_TYPE
data_out[8] <= r.data_out_low[8].DB_MAX_OUTPUT_PORT_TYPE
data_out[9] <= r.data_out_low[9].DB_MAX_OUTPUT_PORT_TYPE
data_out[10] <= r.data_out_low[10].DB_MAX_OUTPUT_PORT_TYPE
data_out[11] <= r.data_out_low[11].DB_MAX_OUTPUT_PORT_TYPE
data_out[12] <= r.data_out_low[12].DB_MAX_OUTPUT_PORT_TYPE
data_out[13] <= r.data_out_low[13].DB_MAX_OUTPUT_PORT_TYPE
data_out[14] <= r.data_out_low[14].DB_MAX_OUTPUT_PORT_TYPE
data_out[15] <= r.data_out_low[15].DB_MAX_OUTPUT_PORT_TYPE
data_out[16] <= captured[0].DB_MAX_OUTPUT_PORT_TYPE
data_out[17] <= captured[1].DB_MAX_OUTPUT_PORT_TYPE
data_out[18] <= captured[2].DB_MAX_OUTPUT_PORT_TYPE
data_out[19] <= captured[3].DB_MAX_OUTPUT_PORT_TYPE
data_out[20] <= captured[4].DB_MAX_OUTPUT_PORT_TYPE
data_out[21] <= captured[5].DB_MAX_OUTPUT_PORT_TYPE
data_out[22] <= captured[6].DB_MAX_OUTPUT_PORT_TYPE
data_out[23] <= captured[7].DB_MAX_OUTPUT_PORT_TYPE
data_out[24] <= captured[8].DB_MAX_OUTPUT_PORT_TYPE
data_out[25] <= captured[9].DB_MAX_OUTPUT_PORT_TYPE
data_out[26] <= captured[10].DB_MAX_OUTPUT_PORT_TYPE
data_out[27] <= captured[11].DB_MAX_OUTPUT_PORT_TYPE
data_out[28] <= captured[12].DB_MAX_OUTPUT_PORT_TYPE
data_out[29] <= captured[13].DB_MAX_OUTPUT_PORT_TYPE
data_out[30] <= captured[14].DB_MAX_OUTPUT_PORT_TYPE
data_out[31] <= captured[15].DB_MAX_OUTPUT_PORT_TYPE
data_out_valid <= r.data_out_valid.DB_MAX_OUTPUT_PORT_TYPE
data_in[0] => Mux72.IN30
data_in[0] => Mux72.IN31
data_in[1] => Mux3.IN30
data_in[1] => Mux3.IN31
data_in[2] => Mux2.IN30
data_in[2] => Mux2.IN31
data_in[3] => Mux1.IN30
data_in[3] => Mux1.IN31
data_in[4] => Mux0.IN30
data_in[4] => Mux0.IN31
data_in[5] => Mux73.IN30
data_in[5] => Mux73.IN31
data_in[6] => Mux74.IN30
data_in[6] => Mux74.IN31
data_in[7] => Mux75.IN30
data_in[7] => Mux75.IN31
data_in[8] => Mux76.IN30
data_in[8] => Mux76.IN31
data_in[9] => Mux77.IN30
data_in[9] => Mux77.IN31
data_in[10] => Mux78.IN30
data_in[10] => Mux78.IN31
data_in[11] => Mux79.IN30
data_in[11] => Mux79.IN31
data_in[12] => Mux80.IN30
data_in[12] => Mux80.IN31
data_in[13] => Mux81.IN30
data_in[13] => Mux81.IN31
data_in[14] => Mux82.IN30
data_in[14] => Mux82.IN31
data_in[15] => Mux83.IN30
data_in[15] => Mux83.IN31
data_in[16] => Mux72.IN28
data_in[16] => Mux72.IN29
data_in[17] => Mux3.IN28
data_in[17] => Mux3.IN29
data_in[18] => Mux2.IN28
data_in[18] => Mux2.IN29
data_in[19] => Mux1.IN28
data_in[19] => Mux1.IN29
data_in[20] => Mux0.IN28
data_in[20] => Mux0.IN29
data_in[21] => Mux73.IN28
data_in[21] => Mux73.IN29
data_in[22] => Mux74.IN28
data_in[22] => Mux74.IN29
data_in[23] => Mux75.IN28
data_in[23] => Mux75.IN29
data_in[24] => Mux76.IN28
data_in[24] => Mux76.IN29
data_in[25] => Mux77.IN28
data_in[25] => Mux77.IN29
data_in[26] => Mux78.IN28
data_in[26] => Mux78.IN29
data_in[27] => Mux79.IN28
data_in[27] => Mux79.IN29
data_in[28] => Mux80.IN28
data_in[28] => Mux80.IN29
data_in[29] => Mux81.IN28
data_in[29] => Mux81.IN29
data_in[30] => Mux82.IN28
data_in[30] => Mux82.IN29
data_in[31] => Mux83.IN28
data_in[31] => Mux83.IN29


|spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll
inclk0 => sub_wire4[0].IN1
c0 <= altpll:altpll_component.clk
c1 <= altpll:altpll_component.clk


|spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component
inclk[0] => sdram_clk_gen_altpll:auto_generated.inclk[0]
inclk[1] => sdram_clk_gen_altpll:auto_generated.inclk[1]
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phasecounterselect[3] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
fbmimicbidir <> <GND>
clk[0] <= clk[0].DB_MAX_OUTPUT_PORT_TYPE
clk[1] <= clk[1].DB_MAX_OUTPUT_PORT_TYPE
clk[2] <= clk[2].DB_MAX_OUTPUT_PORT_TYPE
clk[3] <= clk[3].DB_MAX_OUTPUT_PORT_TYPE
clk[4] <= clk[4].DB_MAX_OUTPUT_PORT_TYPE
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= <GND>
phasedone <= <GND>
vcooverrange <= <GND>
vcounderrange <= <GND>
fbout <= <GND>
fref <= <GND>
icdrclk <= <GND>


|spectrum|sdram_controller:sdram_|sdram_clk_gen:sdram_clk_pll|altpll:altpll_component|sdram_clk_gen_altpll:auto_generated
clk[0] <= pll1.CLK
clk[1] <= pll1.CLK1
clk[2] <= pll1.CLK2
clk[3] <= pll1.CLK3
clk[4] <= pll1.CLK4
inclk[0] => pll1.CLK
inclk[1] => pll1.CLK1


|spectrum|ula:ula_
CLOCK_50 => CLOCK_50.IN1
turbo => clocks:clocks_.turbo
clk_vram <= pll:pll_.c0
nreset => nreset.IN2
locked <= pll:pll_.locked
clk_cpu <= clocks:clocks_.clk_cpu
vs_nintr <= video:video_.vs_nintr
A[0] => zx_keyboard:zx_keyboard_.A[0]
A[0] => ula_data.OUTPUTSELECT
A[0] => ula_data.OUTPUTSELECT
A[0] => ula_data.OUTPUTSELECT
A[0] => ula_data.OUTPUTSELECT
A[0] => ula_data.OUTPUTSELECT
A[0] => ula_data.OUTPUTSELECT
A[0] => always0.IN0
A[1] => zx_keyboard:zx_keyboard_.A[1]
A[2] => zx_keyboard:zx_keyboard_.A[2]
A[3] => zx_keyboard:zx_keyboard_.A[3]
A[4] => zx_keyboard:zx_keyboard_.A[4]
A[5] => zx_keyboard:zx_keyboard_.A[5]
A[6] => zx_keyboard:zx_keyboard_.A[6]
A[7] => zx_keyboard:zx_keyboard_.A[7]
A[8] => zx_keyboard:zx_keyboard_.A[8]
A[9] => zx_keyboard:zx_keyboard_.A[9]
A[10] => zx_keyboard:zx_keyboard_.A[10]
A[11] => zx_keyboard:zx_keyboard_.A[11]
A[12] => zx_keyboard:zx_keyboard_.A[12]
A[13] => zx_keyboard:zx_keyboard_.A[13]
A[14] => zx_keyboard:zx_keyboard_.A[14]
A[15] => zx_keyboard:zx_keyboard_.A[15]
D[0] => border[0].DATAIN
D[1] => border[1].DATAIN
D[2] => border[2].DATAIN
D[3] => beep.IN1
D[3] => pcm_outl.DATAB
D[3] => pcm_outr.DATAB
D[4] => beep.IN0
D[4] => pcm_outl.DATAB
D[4] => pcm_outr.DATAB
D[5] => ~NO_FANOUT~
D[6] => ~NO_FANOUT~
D[7] => ~NO_FANOUT~
ula_data[0] <= ula_data.DB_MAX_OUTPUT_PORT_TYPE
ula_data[1] <= ula_data.DB_MAX_OUTPUT_PORT_TYPE
ula_data[2] <= ula_data.DB_MAX_OUTPUT_PORT_TYPE
ula_data[3] <= ula_data.DB_MAX_OUTPUT_PORT_TYPE
ula_data[4] <= ula_data.DB_MAX_OUTPUT_PORT_TYPE
ula_data[5] <= <VCC>
ula_data[6] <= ula_data.DB_MAX_OUTPUT_PORT_TYPE
ula_data[7] <= <VCC>
io_we => always0.IN1
vram_address[0] <= video:video_.vram_address[0]
vram_address[1] <= video:video_.vram_address[1]
vram_address[2] <= video:video_.vram_address[2]
vram_address[3] <= video:video_.vram_address[3]
vram_address[4] <= video:video_.vram_address[4]
vram_address[5] <= video:video_.vram_address[5]
vram_address[6] <= video:video_.vram_address[6]
vram_address[7] <= video:video_.vram_address[7]
vram_address[8] <= video:video_.vram_address[8]
vram_address[9] <= video:video_.vram_address[9]
vram_address[10] <= video:video_.vram_address[10]
vram_address[11] <= video:video_.vram_address[11]
vram_address[12] <= video:video_.vram_address[12]
vram_data[0] => video:video_.vram_data[0]
vram_data[1] => video:video_.vram_data[1]
vram_data[2] => video:video_.vram_data[2]
vram_data[3] => video:video_.vram_data[3]
vram_data[4] => video:video_.vram_data[4]
vram_data[5] => video:video_.vram_data[5]
vram_data[6] => video:video_.vram_data[6]
vram_data[7] => video:video_.vram_data[7]
PS2_CLK => ps2_keyboard:ps2_keyboard_.PS2_CLK
PS2_DAT => ps2_keyboard:ps2_keyboard_.PS2_DAT
pressed <= zx_keyboard:zx_keyboard_.pressed
I2C_SCLK <> i2c_loader:i2c_loader_.I2C_SCL
I2C_SDAT <> i2c_loader:i2c_loader_.I2C_SDA
AUD_XCK <= i2s_intf:i2s_intf_.I2S_MCLK
AUD_ADCLRCK <= i2s_intf:i2s_intf_.I2S_LRCLK
AUD_DACLRCK <= i2s_intf:i2s_intf_.I2S_LRCLK
AUD_BCLK <= i2s_intf:i2s_intf_.I2S_BCLK
AUD_DACDAT <= i2s_intf:i2s_intf_.I2S_DOUT
AUD_ADCDAT => AUD_ADCDAT.IN1
beeper <= beeper~reg0.DB_MAX_OUTPUT_PORT_TYPE
beep <= beep~reg0.DB_MAX_OUTPUT_PORT_TYPE
raw_loader_in => beep.IN1
raw_loader_in => ula_data.DATAB
VGA_R[0] <= video:video_.VGA_R[0]
VGA_R[1] <= video:video_.VGA_R[1]
VGA_R[2] <= video:video_.VGA_R[2]
VGA_R[3] <= video:video_.VGA_R[3]
VGA_G[0] <= video:video_.VGA_G[0]
VGA_G[1] <= video:video_.VGA_G[1]
VGA_G[2] <= video:video_.VGA_G[2]
VGA_G[3] <= video:video_.VGA_G[3]
VGA_B[0] <= video:video_.VGA_B[0]
VGA_B[1] <= video:video_.VGA_B[1]
VGA_B[2] <= video:video_.VGA_B[2]
VGA_B[3] <= video:video_.VGA_B[3]
VGA_HS <= video:video_.VGA_HS
VGA_VS <= video:video_.VGA_VS


|spectrum|ula:ula_|pll:pll_
inclk0 => sub_wire6[0].IN1
c0 <= altpll:altpll_component.clk
c1 <= altpll:altpll_component.clk
c2 <= altpll:altpll_component.clk
locked <= altpll:altpll_component.locked


|spectrum|ula:ula_|pll:pll_|altpll:altpll_component
inclk[0] => pll_altpll:auto_generated.inclk[0]
inclk[1] => pll_altpll:auto_generated.inclk[1]
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phasecounterselect[3] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
fbmimicbidir <> <GND>
clk[0] <= clk[0].DB_MAX_OUTPUT_PORT_TYPE
clk[1] <= clk[1].DB_MAX_OUTPUT_PORT_TYPE
clk[2] <= clk[2].DB_MAX_OUTPUT_PORT_TYPE
clk[3] <= clk[3].DB_MAX_OUTPUT_PORT_TYPE
clk[4] <= clk[4].DB_MAX_OUTPUT_PORT_TYPE
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= pll_altpll:auto_generated.locked
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= <GND>
phasedone <= <GND>
vcooverrange <= <GND>
vcounderrange <= <GND>
fbout <= <GND>
fref <= <GND>
icdrclk <= <GND>


|spectrum|ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated
clk[0] <= pll1.CLK
clk[1] <= pll1.CLK1
clk[2] <= pll1.CLK2
clk[3] <= pll1.CLK3
clk[4] <= pll1.CLK4
inclk[0] => pll1.CLK
inclk[1] => pll1.CLK1
locked <= pll1.LOCKED


|spectrum|ula:ula_|clocks:clocks_
clk_ula => counter[0].CLK
clk_ula => clk_cpu~reg0.CLK
turbo => always0.IN1
clk_cpu <= clk_cpu~reg0.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|ula:ula_|i2c_loader:i2c_loader_
CLK => retries.CLK
CLK => nak.CLK
CLK => shiftreg[0].CLK
CLK => shiftreg[1].CLK
CLK => shiftreg[2].CLK
CLK => shiftreg[3].CLK
CLK => shiftreg[4].CLK
CLK => shiftreg[5].CLK
CLK => shiftreg[6].CLK
CLK => shiftreg[7].CLK
CLK => thisbyte[0].CLK
CLK => thisbyte[1].CLK
CLK => thisbyte[2].CLK
CLK => thisbyte[3].CLK
CLK => thisbyte[4].CLK
CLK => nbyte[0].CLK
CLK => nbyte[1].CLK
CLK => nbit[0].CLK
CLK => nbit[1].CLK
CLK => nbit[2].CLK
CLK => phase[0].CLK
CLK => phase[1].CLK
CLK => sda_out.CLK
CLK => scl_out.CLK
CLK => state~6.DATAIN
CLK => divider[0].CLK
CLK => divider[1].CLK
CLK => divider[2].CLK
CLK => divider[3].CLK
CLK => divider[4].CLK
CLK => divider[5].CLK
nRESET => retries.ACLR
nRESET => nak.ACLR
nRESET => shiftreg[0].ACLR
nRESET => shiftreg[1].ACLR
nRESET => shiftreg[2].ACLR
nRESET => shiftreg[3].ACLR
nRESET => shiftreg[4].ACLR
nRESET => shiftreg[5].ACLR
nRESET => shiftreg[6].ACLR
nRESET => shiftreg[7].ACLR
nRESET => thisbyte[0].ACLR
nRESET => thisbyte[1].ACLR
nRESET => thisbyte[2].ACLR
nRESET => thisbyte[3].ACLR
nRESET => thisbyte[4].ACLR
nRESET => nbyte[0].ACLR
nRESET => nbyte[1].ACLR
nRESET => nbit[0].ACLR
nRESET => nbit[1].ACLR
nRESET => nbit[2].ACLR
nRESET => phase[0].ACLR
nRESET => phase[1].ACLR
nRESET => sda_out.PRESET
nRESET => scl_out.PRESET
nRESET => divider[0].ACLR
nRESET => divider[1].ACLR
nRESET => divider[2].ACLR
nRESET => divider[3].ACLR
nRESET => divider[4].ACLR
nRESET => divider[5].ACLR
nRESET => state~8.DATAIN
I2C_SCL <> I2C_SCL
I2C_SDA <> I2C_SDA
IS_DONE <= IS_DONE.DB_MAX_OUTPUT_PORT_TYPE
IS_ERROR <= nak.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|ula:ula_|i2s_intf:i2s_intf_
CLK => shiftreg[0].CLK
CLK => shiftreg[1].CLK
CLK => shiftreg[2].CLK
CLK => shiftreg[3].CLK
CLK => shiftreg[4].CLK
CLK => shiftreg[5].CLK
CLK => shiftreg[6].CLK
CLK => shiftreg[7].CLK
CLK => shiftreg[8].CLK
CLK => shiftreg[9].CLK
CLK => shiftreg[10].CLK
CLK => shiftreg[11].CLK
CLK => shiftreg[12].CLK
CLK => shiftreg[13].CLK
CLK => shiftreg[14].CLK
CLK => shiftreg[15].CLK
CLK => shiftreg[16].CLK
CLK => shiftreg[17].CLK
CLK => bclk_r.CLK
CLK => lrclk_r.CLK
CLK => mclk_r.CLK
CLK => bitcount[0].CLK
CLK => bitcount[1].CLK
CLK => bitcount[2].CLK
CLK => bitcount[3].CLK
CLK => bitcount[4].CLK
CLK => bdivider[0].CLK
CLK => bdivider[1].CLK
CLK => bdivider[2].CLK
CLK => bdivider[3].CLK
CLK => bdivider[4].CLK
CLK => lrdivider[0].CLK
CLK => lrdivider[1].CLK
CLK => lrdivider[2].CLK
CLK => lrdivider[3].CLK
CLK => lrdivider[4].CLK
CLK => lrdivider[5].CLK
CLK => lrdivider[6].CLK
CLK => lrdivider[7].CLK
CLK => lrdivider[8].CLK
CLK => lrdivider[9].CLK
CLK => PCM_INR[0]~reg0.CLK
CLK => PCM_INR[1]~reg0.CLK
CLK => PCM_INR[2]~reg0.CLK
CLK => PCM_INR[3]~reg0.CLK
CLK => PCM_INR[4]~reg0.CLK
CLK => PCM_INR[5]~reg0.CLK
CLK => PCM_INR[6]~reg0.CLK
CLK => PCM_INR[7]~reg0.CLK
CLK => PCM_INR[8]~reg0.CLK
CLK => PCM_INR[9]~reg0.CLK
CLK => PCM_INR[10]~reg0.CLK
CLK => PCM_INR[11]~reg0.CLK
CLK => PCM_INR[12]~reg0.CLK
CLK => PCM_INR[13]~reg0.CLK
CLK => PCM_INR[14]~reg0.CLK
CLK => PCM_INR[15]~reg0.CLK
CLK => PCM_INL[0]~reg0.CLK
CLK => PCM_INL[1]~reg0.CLK
CLK => PCM_INL[2]~reg0.CLK
CLK => PCM_INL[3]~reg0.CLK
CLK => PCM_INL[4]~reg0.CLK
CLK => PCM_INL[5]~reg0.CLK
CLK => PCM_INL[6]~reg0.CLK
CLK => PCM_INL[7]~reg0.CLK
CLK => PCM_INL[8]~reg0.CLK
CLK => PCM_INL[9]~reg0.CLK
CLK => PCM_INL[10]~reg0.CLK
CLK => PCM_INL[11]~reg0.CLK
CLK => PCM_INL[12]~reg0.CLK
CLK => PCM_INL[13]~reg0.CLK
CLK => PCM_INL[14]~reg0.CLK
CLK => PCM_INL[15]~reg0.CLK
nRESET => shiftreg[0].ACLR
nRESET => shiftreg[1].ACLR
nRESET => shiftreg[2].ACLR
nRESET => shiftreg[3].ACLR
nRESET => shiftreg[4].ACLR
nRESET => shiftreg[5].ACLR
nRESET => shiftreg[6].ACLR
nRESET => shiftreg[7].ACLR
nRESET => shiftreg[8].ACLR
nRESET => shiftreg[9].ACLR
nRESET => shiftreg[10].ACLR
nRESET => shiftreg[11].ACLR
nRESET => shiftreg[12].ACLR
nRESET => shiftreg[13].ACLR
nRESET => shiftreg[14].ACLR
nRESET => shiftreg[15].ACLR
nRESET => shiftreg[16].ACLR
nRESET => shiftreg[17].ACLR
nRESET => bclk_r.ACLR
nRESET => lrclk_r.ACLR
nRESET => mclk_r.ACLR
nRESET => bitcount[0].PRESET
nRESET => bitcount[1].ACLR
nRESET => bitcount[2].ACLR
nRESET => bitcount[3].ACLR
nRESET => bitcount[4].PRESET
nRESET => bdivider[0].PRESET
nRESET => bdivider[1].ACLR
nRESET => bdivider[2].PRESET
nRESET => bdivider[3].ACLR
nRESET => bdivider[4].PRESET
nRESET => lrdivider[0].PRESET
nRESET => lrdivider[1].ACLR
nRESET => lrdivider[2].PRESET
nRESET => lrdivider[3].PRESET
nRESET => lrdivider[4].ACLR
nRESET => lrdivider[5].PRESET
nRESET => lrdivider[6].PRESET
nRESET => lrdivider[7].PRESET
nRESET => lrdivider[8].ACLR
nRESET => lrdivider[9].PRESET
nRESET => PCM_INR[0]~reg0.ACLR
nRESET => PCM_INR[1]~reg0.ACLR
nRESET => PCM_INR[2]~reg0.ACLR
nRESET => PCM_INR[3]~reg0.ACLR
nRESET => PCM_INR[4]~reg0.ACLR
nRESET => PCM_INR[5]~reg0.ACLR
nRESET => PCM_INR[6]~reg0.ACLR
nRESET => PCM_INR[7]~reg0.ACLR
nRESET => PCM_INR[8]~reg0.ACLR
nRESET => PCM_INR[9]~reg0.ACLR
nRESET => PCM_INR[10]~reg0.ACLR
nRESET => PCM_INR[11]~reg0.ACLR
nRESET => PCM_INR[12]~reg0.ACLR
nRESET => PCM_INR[13]~reg0.ACLR
nRESET => PCM_INR[14]~reg0.ACLR
nRESET => PCM_INR[15]~reg0.ACLR
nRESET => PCM_INL[0]~reg0.ACLR
nRESET => PCM_INL[1]~reg0.ACLR
nRESET => PCM_INL[2]~reg0.ACLR
nRESET => PCM_INL[3]~reg0.ACLR
nRESET => PCM_INL[4]~reg0.ACLR
nRESET => PCM_INL[5]~reg0.ACLR
nRESET => PCM_INL[6]~reg0.ACLR
nRESET => PCM_INL[7]~reg0.ACLR
nRESET => PCM_INL[8]~reg0.ACLR
nRESET => PCM_INL[9]~reg0.ACLR
nRESET => PCM_INL[10]~reg0.ACLR
nRESET => PCM_INL[11]~reg0.ACLR
nRESET => PCM_INL[12]~reg0.ACLR
nRESET => PCM_INL[13]~reg0.ACLR
nRESET => PCM_INL[14]~reg0.ACLR
nRESET => PCM_INL[15]~reg0.ACLR
PCM_INL[0] <= PCM_INL[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INL[1] <= PCM_INL[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INL[2] <= PCM_INL[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INL[3] <= PCM_INL[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INL[4] <= PCM_INL[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INL[5] <= PCM_INL[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INL[6] <= PCM_INL[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INL[7] <= PCM_INL[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INL[8] <= PCM_INL[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INL[9] <= PCM_INL[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INL[10] <= PCM_INL[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INL[11] <= PCM_INL[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INL[12] <= PCM_INL[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INL[13] <= PCM_INL[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INL[14] <= PCM_INL[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INL[15] <= PCM_INL[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INR[0] <= PCM_INR[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INR[1] <= PCM_INR[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INR[2] <= PCM_INR[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INR[3] <= PCM_INR[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INR[4] <= PCM_INR[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INR[5] <= PCM_INR[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INR[6] <= PCM_INR[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INR[7] <= PCM_INR[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INR[8] <= PCM_INR[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INR[9] <= PCM_INR[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INR[10] <= PCM_INR[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INR[11] <= PCM_INR[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INR[12] <= PCM_INR[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INR[13] <= PCM_INR[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INR[14] <= PCM_INR[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_INR[15] <= PCM_INR[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PCM_OUTL[0] => shiftreg.DATAA
PCM_OUTL[1] => shiftreg.DATAA
PCM_OUTL[2] => shiftreg.DATAA
PCM_OUTL[3] => shiftreg.DATAA
PCM_OUTL[4] => shiftreg.DATAA
PCM_OUTL[5] => shiftreg.DATAA
PCM_OUTL[6] => shiftreg.DATAA
PCM_OUTL[7] => shiftreg.DATAA
PCM_OUTL[8] => shiftreg.DATAA
PCM_OUTL[9] => shiftreg.DATAA
PCM_OUTL[10] => shiftreg.DATAA
PCM_OUTL[11] => shiftreg.DATAA
PCM_OUTL[12] => shiftreg.DATAA
PCM_OUTL[13] => shiftreg.DATAA
PCM_OUTL[14] => shiftreg.DATAA
PCM_OUTL[15] => shiftreg.DATAA
PCM_OUTR[0] => shiftreg.DATAB
PCM_OUTR[1] => shiftreg.DATAB
PCM_OUTR[2] => shiftreg.DATAB
PCM_OUTR[3] => shiftreg.DATAB
PCM_OUTR[4] => shiftreg.DATAB
PCM_OUTR[5] => shiftreg.DATAB
PCM_OUTR[6] => shiftreg.DATAB
PCM_OUTR[7] => shiftreg.DATAB
PCM_OUTR[8] => shiftreg.DATAB
PCM_OUTR[9] => shiftreg.DATAB
PCM_OUTR[10] => shiftreg.DATAB
PCM_OUTR[11] => shiftreg.DATAB
PCM_OUTR[12] => shiftreg.DATAB
PCM_OUTR[13] => shiftreg.DATAB
PCM_OUTR[14] => shiftreg.DATAB
PCM_OUTR[15] => shiftreg.DATAB
I2S_MCLK <= mclk_r.DB_MAX_OUTPUT_PORT_TYPE
I2S_LRCLK <= lrclk_r.DB_MAX_OUTPUT_PORT_TYPE
I2S_BCLK <= bclk_r.DB_MAX_OUTPUT_PORT_TYPE
I2S_DOUT <= shiftreg[17].DB_MAX_OUTPUT_PORT_TYPE
I2S_DIN => shiftreg.DATAB


|spectrum|ula:ula_|video:video_
clk_pix => vram_address[0]~reg0.CLK
clk_pix => vram_address[1]~reg0.CLK
clk_pix => vram_address[2]~reg0.CLK
clk_pix => vram_address[3]~reg0.CLK
clk_pix => vram_address[4]~reg0.CLK
clk_pix => vram_address[5]~reg0.CLK
clk_pix => vram_address[6]~reg0.CLK
clk_pix => vram_address[7]~reg0.CLK
clk_pix => vram_address[8]~reg0.CLK
clk_pix => vram_address[9]~reg0.CLK
clk_pix => vram_address[10]~reg0.CLK
clk_pix => vram_address[11]~reg0.CLK
clk_pix => vram_address[12]~reg0.CLK
clk_pix => bits_prefetch[0].CLK
clk_pix => bits_prefetch[1].CLK
clk_pix => bits_prefetch[2].CLK
clk_pix => bits_prefetch[3].CLK
clk_pix => bits_prefetch[4].CLK
clk_pix => bits_prefetch[5].CLK
clk_pix => bits_prefetch[6].CLK
clk_pix => bits_prefetch[7].CLK
clk_pix => attr_prefetch[0].CLK
clk_pix => attr_prefetch[1].CLK
clk_pix => attr_prefetch[2].CLK
clk_pix => attr_prefetch[3].CLK
clk_pix => attr_prefetch[4].CLK
clk_pix => attr_prefetch[5].CLK
clk_pix => attr_prefetch[6].CLK
clk_pix => attr_prefetch[7].CLK
clk_pix => bits[0].CLK
clk_pix => bits[1].CLK
clk_pix => bits[2].CLK
clk_pix => bits[3].CLK
clk_pix => bits[4].CLK
clk_pix => bits[5].CLK
clk_pix => bits[6].CLK
clk_pix => bits[7].CLK
clk_pix => attr[0].CLK
clk_pix => attr[1].CLK
clk_pix => attr[2].CLK
clk_pix => attr[3].CLK
clk_pix => attr[4].CLK
clk_pix => attr[5].CLK
clk_pix => attr[6].CLK
clk_pix => attr[7].CLK
clk_pix => frame[0].CLK
clk_pix => frame[1].CLK
clk_pix => frame[2].CLK
clk_pix => frame[3].CLK
clk_pix => frame[4].CLK
clk_pix => VGA_VS~reg0.CLK
clk_pix => vga_vc[0].CLK
clk_pix => vga_vc[1].CLK
clk_pix => vga_vc[2].CLK
clk_pix => vga_vc[3].CLK
clk_pix => vga_vc[4].CLK
clk_pix => vga_vc[5].CLK
clk_pix => vga_vc[6].CLK
clk_pix => vga_vc[7].CLK
clk_pix => vga_vc[8].CLK
clk_pix => vga_vc[9].CLK
clk_pix => VGA_HS~reg0.CLK
clk_pix => vga_hc[0].CLK
clk_pix => vga_hc[1].CLK
clk_pix => vga_hc[2].CLK
clk_pix => vga_hc[3].CLK
clk_pix => vga_hc[4].CLK
clk_pix => vga_hc[5].CLK
clk_pix => vga_hc[6].CLK
clk_pix => vga_hc[7].CLK
clk_pix => vga_hc[8].CLK
clk_pix => vga_hc[9].CLK
VGA_R[0] <= VGA_R.DB_MAX_OUTPUT_PORT_TYPE
VGA_R[1] <= VGA_R.DB_MAX_OUTPUT_PORT_TYPE
VGA_R[2] <= VGA_R.DB_MAX_OUTPUT_PORT_TYPE
VGA_R[3] <= VGA_R.DB_MAX_OUTPUT_PORT_TYPE
VGA_G[0] <= VGA_G.DB_MAX_OUTPUT_PORT_TYPE
VGA_G[1] <= VGA_G.DB_MAX_OUTPUT_PORT_TYPE
VGA_G[2] <= VGA_G.DB_MAX_OUTPUT_PORT_TYPE
VGA_G[3] <= VGA_G.DB_MAX_OUTPUT_PORT_TYPE
VGA_B[0] <= VGA_B.DB_MAX_OUTPUT_PORT_TYPE
VGA_B[1] <= VGA_B.DB_MAX_OUTPUT_PORT_TYPE
VGA_B[2] <= VGA_B.DB_MAX_OUTPUT_PORT_TYPE
VGA_B[3] <= VGA_B.DB_MAX_OUTPUT_PORT_TYPE
VGA_HS <= VGA_HS~reg0.DB_MAX_OUTPUT_PORT_TYPE
VGA_VS <= VGA_VS~reg0.DB_MAX_OUTPUT_PORT_TYPE
vs_nintr <= vs_nintr.DB_MAX_OUTPUT_PORT_TYPE
vram_address[0] <= vram_address[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
vram_address[1] <= vram_address[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
vram_address[2] <= vram_address[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
vram_address[3] <= vram_address[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
vram_address[4] <= vram_address[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
vram_address[5] <= vram_address[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
vram_address[6] <= vram_address[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
vram_address[7] <= vram_address[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
vram_address[8] <= vram_address[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
vram_address[9] <= vram_address[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
vram_address[10] <= vram_address[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
vram_address[11] <= vram_address[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
vram_address[12] <= vram_address[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
vram_data[0] => attr_prefetch[0].DATAIN
vram_data[0] => bits_prefetch[0].DATAIN
vram_data[1] => bits_prefetch[1].DATAIN
vram_data[1] => attr_prefetch[1].DATAIN
vram_data[2] => bits_prefetch[2].DATAIN
vram_data[2] => attr_prefetch[2].DATAIN
vram_data[3] => bits_prefetch[3].DATAIN
vram_data[3] => attr_prefetch[3].DATAIN
vram_data[4] => bits_prefetch[4].DATAIN
vram_data[4] => attr_prefetch[4].DATAIN
vram_data[5] => bits_prefetch[5].DATAIN
vram_data[5] => attr_prefetch[5].DATAIN
vram_data[6] => bits_prefetch[6].DATAIN
vram_data[6] => attr_prefetch[6].DATAIN
vram_data[7] => bits_prefetch[7].DATAIN
vram_data[7] => attr_prefetch[7].DATAIN
border[0] => cindex[0].DATAA
border[1] => cindex[1].DATAA
border[2] => cindex[2].DATAA


|spectrum|ula:ula_|ps2_keyboard:ps2_keyboard_
clk => scan_code_error~reg0.CLK
clk => scan_code_ready~reg0.CLK
clk => shiftreg[0].CLK
clk => shiftreg[1].CLK
clk => shiftreg[2].CLK
clk => shiftreg[3].CLK
clk => shiftreg[4].CLK
clk => shiftreg[5].CLK
clk => shiftreg[6].CLK
clk => shiftreg[7].CLK
clk => shiftreg[8].CLK
clk => bit_count[0].CLK
clk => bit_count[1].CLK
clk => bit_count[2].CLK
clk => bit_count[3].CLK
clk => clk_edge.CLK
clk => clk_filter[0].CLK
clk => clk_filter[1].CLK
clk => clk_filter[2].CLK
clk => clk_filter[3].CLK
clk => clk_filter[4].CLK
clk => clk_filter[5].CLK
clk => clk_filter[6].CLK
clk => clk_filter[7].CLK
clk => ps2_clk_in.CLK
nreset => scan_code_error~reg0.ACLR
nreset => scan_code_ready~reg0.ACLR
nreset => shiftreg[0].ACLR
nreset => shiftreg[1].ACLR
nreset => shiftreg[2].ACLR
nreset => shiftreg[3].ACLR
nreset => shiftreg[4].ACLR
nreset => shiftreg[5].ACLR
nreset => shiftreg[6].ACLR
nreset => shiftreg[7].ACLR
nreset => shiftreg[8].ACLR
nreset => bit_count[0].ACLR
nreset => bit_count[1].ACLR
nreset => bit_count[2].ACLR
nreset => bit_count[3].ACLR
nreset => clk_edge.ACLR
nreset => clk_filter[0].PRESET
nreset => clk_filter[1].ACLR
nreset => clk_filter[2].ACLR
nreset => clk_filter[3].ACLR
nreset => clk_filter[4].ACLR
nreset => clk_filter[5].ACLR
nreset => clk_filter[6].ACLR
nreset => clk_filter[7].ACLR
nreset => ps2_clk_in.PRESET
PS2_CLK => clk_filter[7].DATAIN
PS2_DAT => shiftreg.DATAB
PS2_DAT => always1.IN1
PS2_DAT => Equal3.IN0
scan_code[0] <= shiftreg[0].DB_MAX_OUTPUT_PORT_TYPE
scan_code[1] <= shiftreg[1].DB_MAX_OUTPUT_PORT_TYPE
scan_code[2] <= shiftreg[2].DB_MAX_OUTPUT_PORT_TYPE
scan_code[3] <= shiftreg[3].DB_MAX_OUTPUT_PORT_TYPE
scan_code[4] <= shiftreg[4].DB_MAX_OUTPUT_PORT_TYPE
scan_code[5] <= shiftreg[5].DB_MAX_OUTPUT_PORT_TYPE
scan_code[6] <= shiftreg[6].DB_MAX_OUTPUT_PORT_TYPE
scan_code[7] <= shiftreg[7].DB_MAX_OUTPUT_PORT_TYPE
scan_code_ready <= scan_code_ready~reg0.DB_MAX_OUTPUT_PORT_TYPE
scan_code_error <= scan_code_error~reg0.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|ula:ula_|zx_keyboard:zx_keyboard_
clk => keys[7][0].CLK
clk => keys[7][1].CLK
clk => keys[7][2].CLK
clk => keys[7][3].CLK
clk => keys[7][4].CLK
clk => keys[6][0].CLK
clk => keys[6][1].CLK
clk => keys[6][2].CLK
clk => keys[6][3].CLK
clk => keys[6][4].CLK
clk => keys[5][0].CLK
clk => keys[5][1].CLK
clk => keys[5][2].CLK
clk => keys[5][3].CLK
clk => keys[5][4].CLK
clk => keys[4][0].CLK
clk => keys[4][1].CLK
clk => keys[4][2].CLK
clk => keys[4][3].CLK
clk => keys[4][4].CLK
clk => keys[3][0].CLK
clk => keys[3][1].CLK
clk => keys[3][2].CLK
clk => keys[3][3].CLK
clk => keys[3][4].CLK
clk => keys[2][0].CLK
clk => keys[2][1].CLK
clk => keys[2][2].CLK
clk => keys[2][3].CLK
clk => keys[2][4].CLK
clk => keys[1][0].CLK
clk => keys[1][1].CLK
clk => keys[1][2].CLK
clk => keys[1][3].CLK
clk => keys[1][4].CLK
clk => keys[0][0].CLK
clk => keys[0][1].CLK
clk => keys[0][2].CLK
clk => keys[0][3].CLK
clk => keys[0][4].CLK
clk => shifted.CLK
clk => extended.CLK
clk => released.CLK
nreset => keys[7][0].PRESET
nreset => keys[7][1].PRESET
nreset => keys[7][2].PRESET
nreset => keys[7][3].PRESET
nreset => keys[7][4].PRESET
nreset => keys[6][0].PRESET
nreset => keys[6][1].PRESET
nreset => keys[6][2].PRESET
nreset => keys[6][3].PRESET
nreset => keys[6][4].PRESET
nreset => keys[5][0].PRESET
nreset => keys[5][1].PRESET
nreset => keys[5][2].PRESET
nreset => keys[5][3].PRESET
nreset => keys[5][4].PRESET
nreset => keys[4][0].PRESET
nreset => keys[4][1].PRESET
nreset => keys[4][2].PRESET
nreset => keys[4][3].PRESET
nreset => keys[4][4].PRESET
nreset => keys[3][0].PRESET
nreset => keys[3][1].PRESET
nreset => keys[3][2].PRESET
nreset => keys[3][3].PRESET
nreset => keys[3][4].PRESET
nreset => keys[2][0].PRESET
nreset => keys[2][1].PRESET
nreset => keys[2][2].PRESET
nreset => keys[2][3].PRESET
nreset => keys[2][4].PRESET
nreset => keys[1][0].PRESET
nreset => keys[1][1].PRESET
nreset => keys[1][2].PRESET
nreset => keys[1][3].PRESET
nreset => keys[1][4].PRESET
nreset => keys[0][0].PRESET
nreset => keys[0][1].PRESET
nreset => keys[0][2].PRESET
nreset => keys[0][3].PRESET
nreset => keys[0][4].PRESET
nreset => shifted.ACLR
nreset => extended.ACLR
nreset => released.ACLR
A[0] => ~NO_FANOUT~
A[1] => ~NO_FANOUT~
A[2] => ~NO_FANOUT~
A[3] => ~NO_FANOUT~
A[4] => ~NO_FANOUT~
A[5] => ~NO_FANOUT~
A[6] => ~NO_FANOUT~
A[7] => ~NO_FANOUT~
A[8] => key_row.OUTPUTSELECT
A[8] => key_row.OUTPUTSELECT
A[8] => key_row.OUTPUTSELECT
A[8] => key_row.OUTPUTSELECT
A[8] => key_row.OUTPUTSELECT
A[9] => key_row.OUTPUTSELECT
A[9] => key_row.OUTPUTSELECT
A[9] => key_row.OUTPUTSELECT
A[9] => key_row.OUTPUTSELECT
A[9] => key_row.OUTPUTSELECT
A[10] => key_row.OUTPUTSELECT
A[10] => key_row.OUTPUTSELECT
A[10] => key_row.OUTPUTSELECT
A[10] => key_row.OUTPUTSELECT
A[10] => key_row.OUTPUTSELECT
A[11] => key_row.OUTPUTSELECT
A[11] => key_row.OUTPUTSELECT
A[11] => key_row.OUTPUTSELECT
A[11] => key_row.OUTPUTSELECT
A[11] => key_row.OUTPUTSELECT
A[12] => key_row.OUTPUTSELECT
A[12] => key_row.OUTPUTSELECT
A[12] => key_row.OUTPUTSELECT
A[12] => key_row.OUTPUTSELECT
A[12] => key_row.OUTPUTSELECT
A[13] => key_row.OUTPUTSELECT
A[13] => key_row.OUTPUTSELECT
A[13] => key_row.OUTPUTSELECT
A[13] => key_row.OUTPUTSELECT
A[13] => key_row.OUTPUTSELECT
A[14] => key_row.OUTPUTSELECT
A[14] => key_row.OUTPUTSELECT
A[14] => key_row.OUTPUTSELECT
A[14] => key_row.OUTPUTSELECT
A[14] => key_row.OUTPUTSELECT
A[15] => key_row.OUTPUTSELECT
A[15] => key_row.OUTPUTSELECT
A[15] => key_row.OUTPUTSELECT
A[15] => key_row.OUTPUTSELECT
A[15] => key_row.OUTPUTSELECT
key_row[0] <= key_row.DB_MAX_OUTPUT_PORT_TYPE
key_row[1] <= key_row.DB_MAX_OUTPUT_PORT_TYPE
key_row[2] <= key_row.DB_MAX_OUTPUT_PORT_TYPE
key_row[3] <= key_row.DB_MAX_OUTPUT_PORT_TYPE
key_row[4] <= key_row.DB_MAX_OUTPUT_PORT_TYPE
scan_code[0] => Decoder0.IN7
scan_code[0] => Equal0.IN7
scan_code[0] => Equal1.IN7
scan_code[1] => Decoder0.IN6
scan_code[1] => Equal0.IN6
scan_code[1] => Equal1.IN6
scan_code[2] => Decoder0.IN5
scan_code[2] => Equal0.IN5
scan_code[2] => Equal1.IN5
scan_code[3] => Decoder0.IN4
scan_code[3] => Equal0.IN4
scan_code[3] => Equal1.IN4
scan_code[4] => Decoder0.IN3
scan_code[4] => Equal0.IN3
scan_code[4] => Equal1.IN3
scan_code[5] => Decoder0.IN2
scan_code[5] => Equal0.IN2
scan_code[5] => Equal1.IN2
scan_code[6] => Decoder0.IN1
scan_code[6] => Equal0.IN1
scan_code[6] => Equal1.IN1
scan_code[7] => Decoder0.IN0
scan_code[7] => Equal0.IN0
scan_code[7] => Equal1.IN0
scan_code_ready => keys[7][0].ENA
scan_code_ready => released.ENA
scan_code_ready => extended.ENA
scan_code_ready => shifted.ENA
scan_code_ready => keys[0][4].ENA
scan_code_ready => keys[0][3].ENA
scan_code_ready => keys[0][2].ENA
scan_code_ready => keys[0][1].ENA
scan_code_ready => keys[0][0].ENA
scan_code_ready => keys[1][4].ENA
scan_code_ready => keys[1][3].ENA
scan_code_ready => keys[1][2].ENA
scan_code_ready => keys[1][1].ENA
scan_code_ready => keys[1][0].ENA
scan_code_ready => keys[2][4].ENA
scan_code_ready => keys[2][3].ENA
scan_code_ready => keys[2][2].ENA
scan_code_ready => keys[2][1].ENA
scan_code_ready => keys[2][0].ENA
scan_code_ready => keys[3][4].ENA
scan_code_ready => keys[3][3].ENA
scan_code_ready => keys[3][2].ENA
scan_code_ready => keys[3][1].ENA
scan_code_ready => keys[3][0].ENA
scan_code_ready => keys[4][4].ENA
scan_code_ready => keys[4][3].ENA
scan_code_ready => keys[4][2].ENA
scan_code_ready => keys[4][1].ENA
scan_code_ready => keys[4][0].ENA
scan_code_ready => keys[5][4].ENA
scan_code_ready => keys[5][3].ENA
scan_code_ready => keys[5][2].ENA
scan_code_ready => keys[5][1].ENA
scan_code_ready => keys[5][0].ENA
scan_code_ready => keys[6][4].ENA
scan_code_ready => keys[6][3].ENA
scan_code_ready => keys[6][2].ENA
scan_code_ready => keys[6][1].ENA
scan_code_ready => keys[6][0].ENA
scan_code_ready => keys[7][4].ENA
scan_code_ready => keys[7][3].ENA
scan_code_ready => keys[7][2].ENA
scan_code_ready => keys[7][1].ENA
scan_code_error => ~NO_FANOUT~
pressed <= pressed.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_
nM1 <= control_pins_n:control_pins_.pin_nM1
nMREQ <= control_pins_n:control_pins_.pin_nMREQ
nIORQ <= control_pins_n:control_pins_.pin_nIORQ
nRD <= control_pins_n:control_pins_.pin_nRD
nWR <= control_pins_n:control_pins_.pin_nWR
nRFSH <= control_pins_n:control_pins_.pin_nRFSH
nHALT <= control_pins_n:control_pins_.pin_nHALT
nBUSACK <= control_pins_n:control_pins_.pin_nBUSACK
nWAIT => nWAIT.IN1
nINT => nINT.IN1
nNMI => nNMI.IN1
nRESET => nRESET.IN1
nBUSRQ => nBUSRQ.IN1
CLK => CLK.IN1
A[0] <= address_pins:address_pins_.abus
A[1] <= address_pins:address_pins_.abus
A[2] <= address_pins:address_pins_.abus
A[3] <= address_pins:address_pins_.abus
A[4] <= address_pins:address_pins_.abus
A[5] <= address_pins:address_pins_.abus
A[6] <= address_pins:address_pins_.abus
A[7] <= address_pins:address_pins_.abus
A[8] <= address_pins:address_pins_.abus
A[9] <= address_pins:address_pins_.abus
A[10] <= address_pins:address_pins_.abus
A[11] <= address_pins:address_pins_.abus
A[12] <= address_pins:address_pins_.abus
A[13] <= address_pins:address_pins_.abus
A[14] <= address_pins:address_pins_.abus
A[15] <= address_pins:address_pins_.abus
D[0] <> data_pins:data_pins_.D
D[1] <> data_pins:data_pins_.D
D[2] <> data_pins:data_pins_.D
D[3] <> data_pins:data_pins_.D
D[4] <> data_pins:data_pins_.D
D[5] <> data_pins:data_pins_.D
D[6] <> data_pins:data_pins_.D
D[7] <> data_pins:data_pins_.D


|spectrum|z80_top_direct_n:z80_|clk_delay:clk_delay_
clk => DFF_inst5.CLK
clk => hold_clk_busrq_ALTERA_SYNTHESIZED.CLK
clk => SYNTHESIZED_WIRE_7.CLK
clk => SYNTHESIZED_WIRE_8.CLK
clk => SYNTHESIZED_WIRE_9.CLK
in_intr => SYNTHESIZED_WIRE_4.IN0
nreset => pin_control_oe.IN1
nreset => SYNTHESIZED_WIRE_9.ACLR
nreset => DFF_inst5.ACLR
nreset => hold_clk_busrq_ALTERA_SYNTHESIZED.ACLR
nreset => SYNTHESIZED_WIRE_8.ACLR
nreset => SYNTHESIZED_WIRE_7.ACLR
T1 => SYNTHESIZED_WIRE_4.IN1
latch_wait => SYNTHESIZED_WIRE_1.IN1
mwait => SYNTHESIZED_WIRE_9.DATAIN
M1 => SYNTHESIZED_WIRE_4.IN1
busrq => SYNTHESIZED_WIRE_8.DATAIN
setM1 => SYNTHESIZED_WIRE_5.IN1
hold_clk_iorq <= hold_clk_iorq.DB_MAX_OUTPUT_PORT_TYPE
hold_clk_wait <= SYNTHESIZED_WIRE_9.DB_MAX_OUTPUT_PORT_TYPE
iorq_Tw <= DFF_inst5.DB_MAX_OUTPUT_PORT_TYPE
busack <= busack.DB_MAX_OUTPUT_PORT_TYPE
pin_control_oe <= pin_control_oe.DB_MAX_OUTPUT_PORT_TYPE
hold_clk_busrq <= hold_clk_busrq_ALTERA_SYNTHESIZED.DB_MAX_OUTPUT_PORT_TYPE
nhold_clk_wait <= SYNTHESIZED_WIRE_9.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|decode_state:decode_state_
ctl_state_iy_set => SYNTHESIZED_WIRE_0.IN0
ctl_state_iy_set => DFFE_instIY1.DATAIN
ctl_state_ixiy_clr => SYNTHESIZED_WIRE_0.IN1
ctl_state_ixiy_we => DFFE_inst4.ENA
ctl_state_ixiy_we => DFFE_instIY1.ENA
ctl_state_halt_set => in_halt.IN1
ctl_state_tbl_ed_set => DFFE_instED.DATAIN
ctl_state_tbl_cb_set => DFFE_instCB.DATAIN
ctl_state_alu => in_alu.DATAIN
clk => DFFE_instNonRep.CLK
clk => DFFE_instIY1.CLK
clk => in_halt~reg0.CLK
clk => DFFE_instED.CLK
clk => DFFE_instCB.CLK
clk => DFFE_inst4.CLK
address_is_1 => DFFE_instNonRep.DATAIN
ctl_repeat_we => DFFE_instNonRep.ENA
in_intr => SYNTHESIZED_WIRE_3.IN0
in_nmi => SYNTHESIZED_WIRE_3.IN1
nreset => in_halt~reg0.ACLR
nreset => DFFE_instCB.ACLR
nreset => DFFE_instED.ACLR
nreset => DFFE_inst4.ACLR
nreset => DFFE_instNonRep.ACLR
nreset => DFFE_instIY1.ACLR
ctl_state_tbl_we => SYNTHESIZED_WIRE_4.IN0
nhold_clk_wait => SYNTHESIZED_WIRE_4.IN1
in_halt <= in_halt~reg0.DB_MAX_OUTPUT_PORT_TYPE
table_cb <= DFFE_instCB.DB_MAX_OUTPUT_PORT_TYPE
table_ed <= DFFE_instED.DB_MAX_OUTPUT_PORT_TYPE
table_xx <= table_xx.DB_MAX_OUTPUT_PORT_TYPE
use_ix <= DFFE_inst4.DB_MAX_OUTPUT_PORT_TYPE
use_ixiy <= use_ixiy.DB_MAX_OUTPUT_PORT_TYPE
in_alu <= ctl_state_alu.DB_MAX_OUTPUT_PORT_TYPE
repeat_en <= DFFE_instNonRep.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|execute:execute_
ctl_state_iy_set <= ctl_state_iy_set.DB_MAX_OUTPUT_PORT_TYPE
ctl_state_ixiy_clr <= ctl_state_ixiy_clr.DB_MAX_OUTPUT_PORT_TYPE
ctl_state_ixiy_we <= ctl_state_ixiy_we.DB_MAX_OUTPUT_PORT_TYPE
ctl_state_halt_set <= ctl_state_halt_set.DB_MAX_OUTPUT_PORT_TYPE
ctl_state_tbl_ed_set <= ctl_state_tbl_ed_set.DB_MAX_OUTPUT_PORT_TYPE
ctl_state_tbl_cb_set <= ctl_state_tbl_cb_set.DB_MAX_OUTPUT_PORT_TYPE
ctl_state_alu <= ctl_state_alu.DB_MAX_OUTPUT_PORT_TYPE
ctl_repeat_we <= ctl_repeat_we.DB_MAX_OUTPUT_PORT_TYPE
ctl_state_tbl_we <= ctl_state_tbl_we.DB_MAX_OUTPUT_PORT_TYPE
ctl_iff1_iff2 <= ctl_iff1_iff2.DB_MAX_OUTPUT_PORT_TYPE
ctl_iffx_we <= ctl_iffx_we.DB_MAX_OUTPUT_PORT_TYPE
ctl_iffx_bit <= ctl_iffx_bit.DB_MAX_OUTPUT_PORT_TYPE
ctl_im_we <= ctl_im_we.DB_MAX_OUTPUT_PORT_TYPE
ctl_no_ints <= ctl_no_ints.DB_MAX_OUTPUT_PORT_TYPE
ctl_ir_we <= ctl_ir_we.DB_MAX_OUTPUT_PORT_TYPE
ctl_mRead <= ctl_mRead.DB_MAX_OUTPUT_PORT_TYPE
ctl_mWrite <= ctl_mWrite.DB_MAX_OUTPUT_PORT_TYPE
ctl_iorw <= ctl_iorw.DB_MAX_OUTPUT_PORT_TYPE
ctl_shift_en <= ctl_shift_en.DB_MAX_OUTPUT_PORT_TYPE
ctl_daa_oe <= ctl_daa_oe.DB_MAX_OUTPUT_PORT_TYPE
ctl_alu_op_low <= ctl_alu_op_low.DB_MAX_OUTPUT_PORT_TYPE
ctl_cond_short <= ctl_mRead.DB_MAX_OUTPUT_PORT_TYPE
ctl_alu_core_hf <= ctl_alu_core_hf.DB_MAX_OUTPUT_PORT_TYPE
ctl_eval_cond <= ctl_state_alu.DB_MAX_OUTPUT_PORT_TYPE
ctl_66_oe <= ctl_66_oe.DB_MAX_OUTPUT_PORT_TYPE
ctl_pf_sel[0] <= ctl_pf_sel.DB_MAX_OUTPUT_PORT_TYPE
ctl_pf_sel[1] <= ctl_pf_sel.DB_MAX_OUTPUT_PORT_TYPE
ctl_alu_oe <= ctl_alu_oe.DB_MAX_OUTPUT_PORT_TYPE
ctl_alu_shift_oe <= ctl_alu_shift_oe.DB_MAX_OUTPUT_PORT_TYPE
ctl_alu_op2_oe <= ctl_alu_op2_oe.DB_MAX_OUTPUT_PORT_TYPE
ctl_alu_res_oe <= ctl_alu_res_oe.DB_MAX_OUTPUT_PORT_TYPE
ctl_alu_op1_oe <= ctl_alu_op1_oe.DB_MAX_OUTPUT_PORT_TYPE
ctl_alu_bs_oe <= ctl_alu_bs_oe.DB_MAX_OUTPUT_PORT_TYPE
ctl_alu_op1_sel_bus <= ctl_alu_op1_sel_bus.DB_MAX_OUTPUT_PORT_TYPE
ctl_alu_op1_sel_low <= ctl_alu_op1_sel_low.DB_MAX_OUTPUT_PORT_TYPE
ctl_alu_op1_sel_zero <= ctl_alu_op1_sel_zero.DB_MAX_OUTPUT_PORT_TYPE
ctl_alu_op2_sel_zero <= ctl_alu_op2_sel_zero.DB_MAX_OUTPUT_PORT_TYPE
ctl_alu_op2_sel_bus <= ctl_alu_op2_sel_bus.DB_MAX_OUTPUT_PORT_TYPE
ctl_alu_op2_sel_lq <= ctl_alu_op2_sel_lq.DB_MAX_OUTPUT_PORT_TYPE
ctl_alu_sel_op2_neg <= ctl_alu_sel_op2_neg.DB_MAX_OUTPUT_PORT_TYPE
ctl_alu_sel_op2_high <= ctl_alu_sel_op2_high.DB_MAX_OUTPUT_PORT_TYPE
ctl_alu_core_R <= ctl_alu_core_R.DB_MAX_OUTPUT_PORT_TYPE
ctl_alu_core_V <= ctl_alu_core_V.DB_MAX_OUTPUT_PORT_TYPE
ctl_alu_core_S <= ctl_alu_core_S.DB_MAX_OUTPUT_PORT_TYPE
ctl_flags_oe <= ctl_flags_oe.DB_MAX_OUTPUT_PORT_TYPE
ctl_flags_bus <= ctl_flags_bus.DB_MAX_OUTPUT_PORT_TYPE
ctl_flags_alu <= ctl_flags_alu.DB_MAX_OUTPUT_PORT_TYPE
ctl_flags_nf_set <= ctl_flags_nf_set.DB_MAX_OUTPUT_PORT_TYPE
ctl_flags_cf_set <= ctl_flags_cf_set.DB_MAX_OUTPUT_PORT_TYPE
ctl_flags_cf_cpl <= ctl_flags_cf_cpl.DB_MAX_OUTPUT_PORT_TYPE
ctl_flags_cf_we <= ctl_flags_cf_we.DB_MAX_OUTPUT_PORT_TYPE
ctl_flags_sz_we <= ctl_flags_sz_we.DB_MAX_OUTPUT_PORT_TYPE
ctl_flags_xy_we <= ctl_flags_xy_we.DB_MAX_OUTPUT_PORT_TYPE
ctl_flags_hf_we <= ctl_flags_hf_we.DB_MAX_OUTPUT_PORT_TYPE
ctl_flags_pf_we <= ctl_flags_pf_we.DB_MAX_OUTPUT_PORT_TYPE
ctl_flags_nf_we <= ctl_flags_nf_we.DB_MAX_OUTPUT_PORT_TYPE
ctl_flags_cf2_we <= ctl_flags_cf2_we.DB_MAX_OUTPUT_PORT_TYPE
ctl_flags_hf_cpl <= ctl_flags_hf_cpl.DB_MAX_OUTPUT_PORT_TYPE
ctl_flags_use_cf2 <= ctl_flags_use_cf2.DB_MAX_OUTPUT_PORT_TYPE
ctl_flags_hf2_we <= ctl_alu_shift_oe.DB_MAX_OUTPUT_PORT_TYPE
ctl_flags_nf_clr <= ctl_flags_nf_clr.DB_MAX_OUTPUT_PORT_TYPE
ctl_alu_zero_16bit <= ctl_alu_zero_16bit.DB_MAX_OUTPUT_PORT_TYPE
ctl_flags_cf2_sel_shift <= ctl_flags_cf2_sel_shift.DB_MAX_OUTPUT_PORT_TYPE
ctl_flags_cf2_sel_daa <= ctl_alu_shift_oe.DB_MAX_OUTPUT_PORT_TYPE
ctl_sw_4u <= ctl_sw_4u.DB_MAX_OUTPUT_PORT_TYPE
ctl_reg_in_hi <= ctl_reg_in_hi.DB_MAX_OUTPUT_PORT_TYPE
ctl_reg_in_lo <= ctl_reg_in_lo.DB_MAX_OUTPUT_PORT_TYPE
ctl_reg_out_lo <= ctl_reg_out_lo.DB_MAX_OUTPUT_PORT_TYPE
ctl_reg_out_hi <= ctl_reg_out_hi.DB_MAX_OUTPUT_PORT_TYPE
ctl_reg_exx <= ctl_reg_exx.DB_MAX_OUTPUT_PORT_TYPE
ctl_reg_ex_af <= ctl_reg_ex_af.DB_MAX_OUTPUT_PORT_TYPE
ctl_reg_ex_de_hl <= ctl_reg_ex_de_hl.DB_MAX_OUTPUT_PORT_TYPE
ctl_reg_use_sp <= ctl_reg_use_sp.DB_MAX_OUTPUT_PORT_TYPE
ctl_reg_sel_pc <= ctl_reg_sel_pc.DB_MAX_OUTPUT_PORT_TYPE
ctl_reg_sel_ir <= ctl_reg_sel_ir.DB_MAX_OUTPUT_PORT_TYPE
ctl_reg_sel_wz <= ctl_reg_sel_wz.DB_MAX_OUTPUT_PORT_TYPE
ctl_reg_gp_we <= ctl_reg_gp_we.DB_MAX_OUTPUT_PORT_TYPE
ctl_reg_not_pc <= ctl_reg_not_pc.DB_MAX_OUTPUT_PORT_TYPE
ctl_reg_sys_we_lo <= ctl_reg_sys_we_lo.DB_MAX_OUTPUT_PORT_TYPE
ctl_reg_sys_we_hi <= ctl_reg_sys_we_hi.DB_MAX_OUTPUT_PORT_TYPE
ctl_reg_sys_we <= ctl_reg_sys_we.DB_MAX_OUTPUT_PORT_TYPE
ctl_sw_4d <= ctl_sw_4d.DB_MAX_OUTPUT_PORT_TYPE
ctl_reg_gp_hilo[0] <= ctl_reg_gp_hilo.DB_MAX_OUTPUT_PORT_TYPE
ctl_reg_gp_hilo[1] <= ctl_reg_gp_hilo.DB_MAX_OUTPUT_PORT_TYPE
ctl_reg_gp_sel[0] <= ctl_reg_gp_sel.DB_MAX_OUTPUT_PORT_TYPE
ctl_reg_gp_sel[1] <= ctl_reg_gp_sel.DB_MAX_OUTPUT_PORT_TYPE
ctl_reg_sys_hilo[0] <= ctl_reg_sys_hilo.DB_MAX_OUTPUT_PORT_TYPE
ctl_reg_sys_hilo[1] <= ctl_reg_sys_hilo.DB_MAX_OUTPUT_PORT_TYPE
ctl_inc_cy <= ctl_inc_cy.DB_MAX_OUTPUT_PORT_TYPE
ctl_inc_dec <= ctl_inc_dec.DB_MAX_OUTPUT_PORT_TYPE
ctl_al_we <= ctl_al_we.DB_MAX_OUTPUT_PORT_TYPE
ctl_inc_limit6 <= ctl_inc_limit6.DB_MAX_OUTPUT_PORT_TYPE
ctl_bus_inc_oe <= ctl_bus_inc_oe.DB_MAX_OUTPUT_PORT_TYPE
ctl_apin_mux <= ctl_apin_mux.DB_MAX_OUTPUT_PORT_TYPE
ctl_apin_mux2 <= ctl_apin_mux2.DB_MAX_OUTPUT_PORT_TYPE
ctl_bus_ff_oe <= ctl_bus_ff_oe.DB_MAX_OUTPUT_PORT_TYPE
ctl_bus_zero_oe <= ctl_bus_zero_oe.DB_MAX_OUTPUT_PORT_TYPE
ctl_sw_1u <= ctl_sw_1u.DB_MAX_OUTPUT_PORT_TYPE
ctl_sw_1d <= ctl_sw_1d.DB_MAX_OUTPUT_PORT_TYPE
ctl_sw_2u <= ctl_sw_2u.DB_MAX_OUTPUT_PORT_TYPE
ctl_sw_2d <= ctl_sw_2d.DB_MAX_OUTPUT_PORT_TYPE
ctl_sw_mask543_en <= ctl_sw_mask543_en.DB_MAX_OUTPUT_PORT_TYPE
ctl_bus_db_we <= ctl_bus_db_we.DB_MAX_OUTPUT_PORT_TYPE
ctl_bus_db_oe <= ctl_bus_db_oe.DB_MAX_OUTPUT_PORT_TYPE
nextM <= nextM.DB_MAX_OUTPUT_PORT_TYPE
setM1 <= setM1.DB_MAX_OUTPUT_PORT_TYPE
fFetch <= M1.DB_MAX_OUTPUT_PORT_TYPE
fMRead <= fMRead.DB_MAX_OUTPUT_PORT_TYPE
fMWrite <= fMWrite.DB_MAX_OUTPUT_PORT_TYPE
fIORead <= fIORead.DB_MAX_OUTPUT_PORT_TYPE
fIOWrite <= fIOWrite.DB_MAX_OUTPUT_PORT_TYPE
pla[0] => setM1.IN0
pla[0] => setM1.IN0
pla[1] => ctl_reg_exx.IN1
pla[1] => validPLA.IN1
pla[2] => ctl_reg_ex_de_hl.IN1
pla[2] => validPLA.IN1
pla[3] => setIXIY.IN1
pla[3] => validPLA.IN1
pla[3] => ctl_no_ints.IN1
pla[4] => ~NO_FANOUT~
pla[5] => ctl_reg_gp_hilo_pla5M1T4_3.IN1
pla[5] => ctl_reg_gp_sel_pla5M1T4_2.IN1
pla[5] => ctl_reg_gp_sel_pla5M1T5_2.IN1
pla[5] => ctl_reg_gp_hilo_pla5M1T5_3.IN1
pla[5] => setM1.IN1
pla[6] => ctl_reg_gp_hilo_pla6M1T4_4.IN1
pla[6] => ctl_reg_gp_sel_pla6M1T4_3.IN1
pla[7] => ctl_reg_gp_sel_pla7M1T1_2.IN1
pla[7] => ctl_reg_gp_hilo_pla7M1T1_3.IN1
pla[7] => ctl_sw_1d.IN1
pla[7] => validPLA.IN1
pla[7] => ctl_mRead.IN1
pla[7] => ctl_reg_sys_hilo_pla7M2T1_3.IN1
pla[7] => ctl_reg_sys_hilo_pla7M2T2_4.IN1
pla[7] => ctl_mRead.IN1
pla[7] => ctl_reg_sys_hilo_pla7M3T1_3.IN1
pla[7] => ctl_reg_gp_sel_pla7M3T1_6.IN1
pla[7] => ctl_reg_gp_hilo_pla7M3T1_7.IN1
pla[7] => ctl_reg_sys_hilo_pla7M3T2_4.IN1
pla[7] => setM1.IN1
pla[8] => ctl_mWrite.IN0
pla[8] => ctl_mRead.IN0
pla[9] => ctl_reg_gp_sel_pla9M1T4_2.IN1
pla[9] => ctl_reg_gp_hilo_pla9M1T4_3.IN1
pla[9] => ctl_reg_gp_sel_pla9M1T5_2.IN1
pla[9] => ctl_reg_gp_hilo_pla9M1T5_3.IN1
pla[9] => setM1.IN1
pla[10] => validPLA.IN1
pla[10] => ctl_mRead.IN1
pla[10] => ctl_reg_gp_hilo_pla10M2T1_4.IN1
pla[10] => ctl_reg_gp_sel_pla10M2T1_3.IN1
pla[10] => ctl_reg_gp_sel_pla10M2T2_3.IN1
pla[10] => ctl_reg_gp_hilo_pla10M2T2_4.IN1
pla[10] => ctl_reg_sys_hilo_pla10M2T3_6.IN1
pla[10] => ctl_reg_gp_hilo_pla10M3T1_4.IN1
pla[10] => ctl_reg_gp_sel_pla10M3T1_3.IN1
pla[10] => ctl_reg_gp_sel_pla10M3T2_3.IN1
pla[10] => ctl_reg_gp_hilo_pla10M3T2_4.IN1
pla[10] => ctl_reg_sys_hilo_pla10M3T3_4.IN1
pla[10] => ctl_reg_gp_hilo_pla10M3T4_5.IN1
pla[10] => ctl_reg_gp_sel_pla10M3T4_4.IN1
pla[10] => ctl_reg_gp_sel_pla10M4T1_5.IN1
pla[10] => ctl_reg_gp_hilo_pla10M4T1_6.IN1
pla[10] => ctl_reg_gp_sel_pla10M4T2_3.IN1
pla[10] => ctl_reg_gp_hilo_pla10M4T2_4.IN1
pla[10] => ctl_reg_gp_hilo_pla10M4T3_6.IN1
pla[10] => ctl_reg_gp_sel_pla10M4T3_5.IN1
pla[10] => ctl_reg_gp_sel_pla10M5T1_5.IN1
pla[10] => ctl_reg_gp_hilo_pla10M5T1_6.IN1
pla[10] => ctl_reg_gp_sel_pla10M5T2_3.IN1
pla[10] => ctl_reg_gp_hilo_pla10M5T2_4.IN1
pla[10] => ctl_reg_sys_hilo_pla10M5T3_3.IN1
pla[10] => ctl_reg_gp_sel_pla10M5T4_2.IN1
pla[10] => ctl_reg_gp_hilo_pla10M5T4_3.IN1
pla[10] => setM1.IN1
pla[11] => ctl_pf_sel_pla11M1T1_11.IN1
pla[11] => ctl_reg_gp_sel_pla11M1T2_2.IN1
pla[11] => ctl_reg_gp_hilo_pla11M1T2_3.IN1
pla[11] => ctl_reg_gp_sel_pla11M1T3_1.IN1
pla[11] => ctl_reg_gp_hilo_pla11M1T3_2.IN1
pla[11] => validPLA.IN1
pla[11] => ctl_mRead.IN1
pla[11] => ctl_reg_gp_sel_pla11M2T1_2.IN1
pla[11] => ctl_reg_gp_hilo_pla11M2T1_3.IN1
pla[11] => ctl_reg_gp_sel_pla11M2T2_3.IN1
pla[11] => ctl_reg_gp_hilo_pla11M2T2_4.IN1
pla[11] => ctl_alu_op_low.IN1
pla[11] => ctl_alu_core_hf.IN1
pla[11] => ctl_reg_gp_hilo_pla11M3T3_2.IN1
pla[11] => ctl_reg_gp_hilo_pla11M3T4_3.IN1
pla[11] => setM1.IN1
pla[11] => ctl_reg_sys_hilo_pla11M4T1_2.IN1
pla[11] => ctl_reg_sys_hilo_pla11M4T2_3.IN1
pla[11] => ctl_reg_sys_hilo_pla11M4T3_2.IN1
pla[11] => ctl_reg_sys_hilo_pla11M4T4_3.IN1
pla[11] => setM1.IN1
pla[12] => ctl_pf_sel_pla12M1T1_12.IN1
pla[12] => ctl_reg_gp_sel_pla12M1T2_2.IN1
pla[12] => ctl_reg_gp_hilo_pla12M1T2_3.IN1
pla[12] => ctl_reg_gp_sel_pla12M1T3_1.IN1
pla[12] => ctl_reg_gp_hilo_pla12M1T3_2.IN1
pla[12] => validPLA.IN1
pla[12] => ctl_mRead.IN1
pla[12] => ctl_reg_gp_sel_pla12M2T1_2.IN1
pla[12] => ctl_reg_gp_hilo_pla12M2T1_3.IN1
pla[12] => ctl_reg_gp_sel_pla12M2T2_3.IN1
pla[12] => ctl_reg_gp_hilo_pla12M2T2_4.IN1
pla[12] => ctl_mWrite.IN1
pla[12] => ctl_reg_gp_sel_pla12M3T1_2.IN1
pla[12] => ctl_reg_gp_hilo_pla12M3T1_3.IN1
pla[12] => ctl_reg_gp_sel_pla12M3T2_3.IN1
pla[12] => ctl_reg_gp_hilo_pla12M3T2_4.IN1
pla[12] => ctl_reg_gp_hilo_pla12M3T3_3.IN1
pla[12] => ctl_reg_gp_hilo_pla12M3T4_3.IN1
pla[12] => setM1.IN1
pla[12] => ctl_reg_sys_hilo_pla12M4T1_2.IN1
pla[12] => ctl_reg_sys_hilo_pla12M4T2_3.IN1
pla[12] => ctl_reg_sys_hilo_pla12M4T3_2.IN1
pla[12] => ctl_reg_sys_hilo_pla12M4T4_3.IN1
pla[12] => setM1.IN1
pla[13] => ctl_mWrite.IN1
pla[13] => ctl_mRead.IN0
pla[13] => ctl_mRead.IN0
pla[13] => ctl_mRead.IN0
pla[13] => ctl_mRead.IN0
pla[13] => ctl_mRead.IN1
pla[14] => ~NO_FANOUT~
pla[15] => ctl_mRead.IN0
pla[15] => ctl_mRead.IN0
pla[16] => ctl_mWrite.IN0
pla[16] => ctl_mRead.IN0
pla[17] => ctl_mRead.IN0
pla[18] => ~NO_FANOUT~
pla[19] => ~NO_FANOUT~
pla[20] => ctl_mRead.IN0
pla[21] => ctl_mWrite.IN0
pla[22] => ~NO_FANOUT~
pla[23] => ctl_mWrite.IN1
pla[23] => ctl_mRead.IN1
pla[24] => validPLA.IN1
pla[24] => ctl_mRead.IN1
pla[24] => ctl_reg_sys_hilo_pla24M2T1_3.IN1
pla[24] => ctl_reg_sys_hilo_pla24M2T2_4.IN1
pla[24] => ctl_reg_sys_hilo_pla24M2T3_6.IN1
pla[24] => ctl_reg_sys_hilo_pla24M3T1_3.IN1
pla[24] => ctl_reg_sys_hilo_pla24M3T2_4.IN1
pla[24] => ctl_reg_sys_hilo_pla24M3T3_4.IN1
pla[24] => ctl_reg_gp_hilo_pla24M3T4_5.IN1
pla[24] => ctl_reg_gp_sel_pla24M3T4_4.IN1
pla[24] => ctl_reg_sys_hilo_pla24M4T1_6.IN1
pla[24] => ctl_reg_gp_sel_pla24M4T2_3.IN1
pla[24] => ctl_reg_gp_hilo_pla24M4T2_4.IN1
pla[24] => ctl_reg_gp_hilo_pla24M4T3_6.IN1
pla[24] => ctl_reg_gp_sel_pla24M4T3_5.IN1
pla[24] => ctl_reg_sys_hilo_pla24M5T1_6.IN1
pla[24] => ctl_reg_gp_sel_pla24M5T2_3.IN1
pla[24] => ctl_reg_gp_hilo_pla24M5T2_4.IN1
pla[24] => ctl_reg_sys_hilo_pla24M5T3_4.IN1
pla[25] => ctl_reg_gp_sel_pla25M1T1_2.IN1
pla[25] => ctl_reg_gp_hilo_pla25M1T1_3.IN1
pla[25] => ctl_reg_gp_sel_pla25M1T2_2.IN1
pla[25] => ctl_reg_gp_hilo_pla25M1T2_3.IN1
pla[25] => ctl_reg_gp_sel_pla25M1T3_1.IN1
pla[25] => ctl_reg_gp_hilo_pla25M1T3_2.IN1
pla[25] => ctl_reg_gp_sel_pla25M1T4_3.IN1
pla[25] => ctl_reg_gp_hilo_pla25M1T4_4.IN1
pla[25] => ctl_shift_en.IN1
pla[26] => ctl_reg_gp_sel_pla26M1T3_1.IN1
pla[26] => ctl_reg_gp_hilo_pla26M1T3_2.IN1
pla[26] => ctl_reg_gp_hilo_pla26M1T4_3.IN1
pla[26] => ctl_alu_op_low.IN1
pla[26] => ctl_reg_gp_hilo_pla26M1T5_5.IN1
pla[26] => ctl_reg_sys_hilo_pla26M2T1_3.IN1
pla[26] => ctl_reg_sys_hilo_pla26M2T2_4.IN1
pla[26] => setM1.IN1
pla[26] => ctl_alu_shift_oe.IN1
pla[26] => ctl_reg_sys_hilo_pla26M3T2_2.IN1
pla[26] => ctl_reg_sys_hilo_pla26M3T3_3.IN1
pla[26] => ctl_reg_sys_hilo_pla26M3T4_2.IN1
pla[26] => ctl_reg_sys_hilo_pla26M3T5_3.IN1
pla[26] => ctl_reg_sys_hilo_pla26M3T5_8.IN1
pla[27] => ctl_iorw.IN0
pla[27] => ctl_iorw.IN0
pla[28] => ctl_mRead.IN0
pla[28] => ctl_mRead.IN0
pla[29] => validPLA.IN1
pla[29] => ctl_mRead.IN1
pla[29] => ctl_reg_sys_hilo_pla29M2T1_3.IN1
pla[29] => ctl_reg_sys_hilo_pla29M2T2_4.IN1
pla[29] => ctl_reg_sys_hilo_pla29M2T3_6.IN1
pla[29] => ctl_reg_sys_hilo_pla29M3T1_3.IN1
pla[29] => ctl_reg_sys_hilo_pla29M3T2_4.IN1
pla[29] => ctl_reg_sys_hilo_pla29M3T3_4.IN1
pla[29] => ctl_reg_sys_hilo_pla29M3T3_9.IN1
pla[30] => ctl_mRead.IN1
pla[30] => ctl_mRead.IN1
pla[31] => ctl_mRead.IN0
pla[31] => ctl_mRead.IN0
pla[32] => ~NO_FANOUT~
pla[33] => ctl_mRead.IN1
pla[33] => ctl_mRead.IN1
pla[34] => ctl_iorw.IN1
pla[34] => ctl_iorw.IN1
pla[35] => validPLA.IN1
pla[35] => ctl_mRead.IN1
pla[35] => ctl_reg_gp_hilo_pla35M2T1_4.IN1
pla[35] => ctl_reg_gp_sel_pla35M2T1_3.IN1
pla[35] => ctl_reg_gp_sel_pla35M2T2_3.IN1
pla[35] => ctl_reg_gp_hilo_pla35M2T2_4.IN1
pla[35] => ctl_reg_sys_hilo_pla35M2T3_6.IN1
pla[35] => ctl_reg_gp_hilo_pla35M3T1_4.IN1
pla[35] => ctl_reg_gp_sel_pla35M3T1_3.IN1
pla[35] => ctl_reg_gp_sel_pla35M3T2_3.IN1
pla[35] => ctl_reg_gp_hilo_pla35M3T2_4.IN1
pla[35] => ctl_reg_sys_hilo_pla35M3T3_4.IN1
pla[35] => ctl_reg_sys_hilo_pla35M3T3_9.IN1
pla[36] => ~NO_FANOUT~
pla[37] => ctl_mRead.IN1
pla[37] => ctl_mRead.IN1
pla[38] => ctl_mRead.IN1
pla[38] => ctl_mRead.IN1
pla[39] => ctl_reg_ex_af.IN1
pla[39] => validPLA.IN1
pla[40] => validPLA.IN1
pla[40] => ctl_mRead.IN1
pla[40] => ctl_reg_sys_hilo_pla40M2T1_3.IN1
pla[40] => ctl_reg_sys_hilo_pla40M2T2_4.IN1
pla[40] => ctl_mRead.IN1
pla[40] => ctl_reg_sys_hilo_pla40M3T1_3.IN1
pla[40] => ctl_reg_sys_hilo_pla40M3T2_4.IN1
pla[40] => ixy_d.IN1
pla[40] => ixy_d.IN1
pla[40] => ixy_d.IN1
pla[40] => ctl_mRead.IN0
pla[41] => ~NO_FANOUT~
pla[42] => ctl_reg_gp_sel_pla42M1T3_1.IN1
pla[42] => ctl_reg_gp_hilo_pla42M1T3_2.IN1
pla[42] => validPLA.IN1
pla[42] => ctl_mRead.IN1
pla[42] => ctl_reg_sys_hilo_pla42M2T1_3.IN1
pla[42] => ctl_reg_sys_hilo_pla42M2T2_4.IN1
pla[42] => ctl_reg_sys_hilo_pla42M2T3_6.IN1
pla[42] => ctl_reg_sys_hilo_pla42M3T1_3.IN1
pla[42] => ctl_reg_sys_hilo_pla42M3T2_4.IN1
pla[42] => ctl_reg_sys_hilo_pla42M3T3_6.IN1
pla[42] => ctl_reg_gp_hilo_pla42M3T4_5.IN1
pla[42] => ctl_reg_gp_sel_pla42M3T4_4.IN1
pla[42] => ctl_reg_sys_hilo_pla42M4T1_6.IN1
pla[42] => ctl_reg_gp_sel_pla42M4T2_3.IN1
pla[42] => ctl_reg_gp_hilo_pla42M4T2_4.IN1
pla[42] => ctl_reg_gp_hilo_pla42M4T3_6.IN1
pla[42] => ctl_reg_gp_sel_pla42M4T3_5.IN1
pla[42] => ctl_reg_sys_hilo_pla42M5T1_6.IN1
pla[42] => ctl_reg_gp_sel_pla42M5T2_3.IN1
pla[42] => ctl_reg_gp_hilo_pla42M5T2_4.IN1
pla[42] => ctl_reg_sys_hilo_pla42M5T3_4.IN1
pla[43] => ctl_reg_gp_sel_pla43M1T3_1.IN1
pla[43] => ctl_reg_gp_hilo_pla43M1T3_2.IN1
pla[43] => validPLA.IN1
pla[43] => ctl_mRead.IN1
pla[43] => ctl_reg_sys_hilo_pla43M2T1_3.IN1
pla[43] => ctl_reg_sys_hilo_pla43M2T2_4.IN1
pla[43] => ctl_reg_sys_hilo_pla43M2T3_6.IN1
pla[43] => ctl_reg_sys_hilo_pla43M3T1_3.IN1
pla[43] => ctl_reg_sys_hilo_pla43M3T2_4.IN1
pla[43] => ctl_reg_sys_hilo_pla43M3T3_5.IN1
pla[43] => ctl_reg_sys_hilo_pla43M3T3_10.IN1
pla[44] => ctl_state_tbl_cb_set.IN1
pla[44] => validPLA.IN1
pla[44] => ctl_no_ints.IN1
pla[45] => ctl_reg_gp_sel_pla45M1T3_1.IN1
pla[45] => ctl_reg_gp_hilo_pla45M1T3_2.IN1
pla[45] => validPLA.IN1
pla[45] => ctl_mRead.IN1
pla[45] => ctl_reg_gp_hilo_pla45M2T1_4.IN1
pla[45] => ctl_reg_gp_sel_pla45M2T1_3.IN1
pla[45] => ctl_reg_gp_sel_pla45M2T2_3.IN1
pla[45] => ctl_reg_gp_hilo_pla45M2T2_4.IN1
pla[45] => ctl_reg_sys_hilo_pla45M2T3_6.IN1
pla[45] => ctl_reg_gp_hilo_pla45M3T1_4.IN1
pla[45] => ctl_reg_gp_sel_pla45M3T1_3.IN1
pla[45] => ctl_reg_gp_sel_pla45M3T2_3.IN1
pla[45] => ctl_reg_gp_hilo_pla45M3T2_4.IN1
pla[45] => ctl_reg_sys_hilo_pla45M3T3_4.IN1
pla[45] => ctl_reg_sys_hilo_pla45M3T3_9.IN1
pla[46] => validPLA.IN1
pla[46] => ctl_iff1_iff2.IN1
pla[46] => ctl_reg_gp_hilo_pla46M2T1_4.IN1
pla[46] => ctl_reg_gp_sel_pla46M2T1_3.IN1
pla[46] => ctl_reg_gp_sel_pla46M2T2_3.IN1
pla[46] => ctl_reg_gp_hilo_pla46M2T2_4.IN1
pla[46] => ctl_reg_sys_hilo_pla46M2T3_6.IN1
pla[46] => ctl_reg_gp_hilo_pla46M3T1_4.IN1
pla[46] => ctl_reg_gp_sel_pla46M3T1_3.IN1
pla[46] => ctl_reg_gp_sel_pla46M3T2_3.IN1
pla[46] => ctl_reg_gp_hilo_pla46M3T2_4.IN1
pla[46] => ctl_reg_sys_hilo_pla46M3T3_4.IN1
pla[46] => ctl_reg_sys_hilo_pla46M3T3_9.IN1
pla[47] => ctl_reg_gp_sel_pla47M1T3_1.IN1
pla[47] => ctl_reg_gp_hilo_pla47M1T3_2.IN1
pla[47] => validPLA.IN1
pla[47] => ctl_mRead.IN1
pla[47] => ctl_reg_sys_hilo_pla47M2T1_3.IN1
pla[47] => ctl_reg_sys_hilo_pla47M2T2_4.IN1
pla[47] => nextM.IN1
pla[47] => ctl_alu_shift_oe.IN1
pla[47] => ctl_reg_sys_hilo_pla47M3T2_2.IN1
pla[47] => ctl_reg_sys_hilo_pla47M3T3_3.IN1
pla[47] => ctl_reg_sys_hilo_pla47M3T4_2.IN1
pla[47] => ctl_reg_sys_hilo_pla47M3T5_3.IN1
pla[47] => ctl_reg_sys_hilo_pla47M3T5_8.IN1
pla[48] => ctl_reg_gp_sel_pla48M1T3_1.IN1
pla[48] => ctl_reg_gp_hilo_pla48M1T3_2.IN1
pla[48] => validPLA.IN1
pla[48] => ctl_mRead.IN1
pla[48] => ctl_reg_sys_hilo_pla48M2T1_3.IN1
pla[48] => ctl_reg_sys_hilo_pla48M2T2_4.IN1
pla[48] => setM1.IN1
pla[48] => ctl_alu_shift_oe.IN1
pla[48] => ctl_reg_sys_hilo_pla48M3T2_2.IN1
pla[48] => ctl_reg_sys_hilo_pla48M3T3_3.IN1
pla[48] => ctl_reg_sys_hilo_pla48M3T4_2.IN1
pla[48] => ctl_reg_sys_hilo_pla48M3T5_3.IN1
pla[48] => ctl_reg_sys_hilo_pla48M3T5_8.IN1
pla[49] => ctl_reg_gp_sel_pla49M1T3_1.IN1
pla[49] => ctl_reg_gp_hilo_pla49M1T3_2.IN1
pla[49] => validPLA.IN1
pla[49] => ctl_mRead.IN1
pla[49] => ctl_reg_sys_hilo_pla49M2T1_3.IN1
pla[49] => ctl_reg_sys_hilo_pla49M2T2_4.IN1
pla[49] => ctl_mRead.IN1
pla[49] => ctl_reg_sys_hilo_pla49M3T1_3.IN1
pla[49] => ctl_reg_sys_hilo_pla49M3T2_4.IN1
pla[49] => ixy_d.IN1
pla[49] => ixy_d.IN1
pla[49] => ixy_d.IN1
pla[49] => ctl_ir_we.IN1
pla[50] => ctl_mRead.IN1
pla[50] => ctl_mRead.IN1
pla[51] => ctl_state_tbl_ed_set.IN1
pla[51] => validPLA.IN1
pla[51] => ctl_no_ints.IN1
pla[52] => ixy_d.IN0
pla[52] => ctl_state_alu.IN0
pla[52] => ctl_state_alu.IN0
pla[53] => ixy_d.IN0
pla[53] => ctl_mRead.IN0
pla[53] => ctl_alu_op_low.IN0
pla[54] => ~NO_FANOUT~
pla[55] => ctl_ir_we.IN1
pla[55] => ctl_ir_we.IN1
pla[55] => ctl_ir_we.IN1
pla[55] => ctl_ir_we.IN1
pla[55] => ctl_ir_we.IN1
pla[55] => ctl_ir_we.IN1
pla[55] => ctl_ir_we.IN1
pla[55] => ctl_ir_we.IN1
pla[56] => ctl_reg_sys_hilo_pla56M1T3_3.IN1
pla[56] => ctl_66_oe.IN1
pla[56] => ctl_bus_ff_oe.IN1
pla[56] => validPLA.IN1
pla[56] => ctl_reg_gp_hilo_pla56M1T5_5.IN1
pla[56] => ctl_reg_gp_sel_pla56M1T5_4.IN1
pla[56] => ctl_reg_sys_hilo_pla56M2T1_6.IN1
pla[56] => ctl_reg_gp_sel_pla56M2T2_3.IN1
pla[56] => ctl_reg_gp_hilo_pla56M2T2_4.IN1
pla[56] => ctl_reg_gp_hilo_pla56M2T3_6.IN1
pla[56] => ctl_reg_gp_sel_pla56M2T3_5.IN1
pla[56] => ctl_reg_sys_hilo_pla56M3T1_6.IN1
pla[56] => ctl_reg_gp_sel_pla56M3T2_3.IN1
pla[56] => ctl_reg_gp_hilo_pla56M3T2_4.IN1
pla[56] => ctl_reg_sys_hilo_pla56M3T3_6.IN1
pla[56] => ctl_reg_sys_hilo_pla56M4T1_3.IN1
pla[56] => ctl_alu_shift_oe.IN1
pla[56] => ctl_reg_sys_hilo_pla56M4T3_6.IN1
pla[56] => ctl_reg_sys_hilo_pla56M5T1_3.IN1
pla[56] => ctl_inc_cy.IN1
pla[56] => ctl_reg_sys_hilo_pla56M5T3_4.IN1
pla[56] => ctl_reg_sys_hilo_pla56M5T3_9.IN1
pla[57] => ctl_reg_gp_sel_pla57M1T3_1.IN1
pla[57] => ctl_reg_gp_hilo_pla57M1T3_2.IN1
pla[57] => ctl_reg_sys_hilo_pla57M1T4_4.IN1
pla[57] => setM1.IN1
pla[58] => ixy_d.IN0
pla[58] => ctl_mRead.IN0
pla[58] => ctl_alu_oe.IN0
pla[59] => ixy_d.IN0
pla[59] => ctl_mWrite.IN0
pla[59] => ctl_alu_oe.IN1
pla[60] => ~NO_FANOUT~
pla[61] => ctl_alu_oe.IN1
pla[62] => ~NO_FANOUT~
pla[63] => ~NO_FANOUT~
pla[64] => ctl_sw_2u.IN1
pla[64] => ctl_state_alu.IN1
pla[64] => ctl_reg_gp_sel_pla64M1T2_2.IN1
pla[64] => ctl_reg_gp_hilo_pla64M1T2_3.IN1
pla[64] => ctl_reg_gp_sel_pla64M1T3_1.IN1
pla[64] => ctl_reg_gp_hilo_pla64M1T3_2.IN1
pla[64] => ctl_reg_gp_sel_pla64M1T4_4.IN1
pla[64] => ctl_reg_gp_hilo_pla64M1T4_5.IN1
pla[64] => ctl_state_alu.IN1
pla[64] => ctl_reg_sys_hilo_pla64M2T1_3.IN1
pla[64] => ctl_reg_sys_hilo_pla64M2T2_4.IN1
pla[64] => ctl_state_alu.IN1
pla[65] => ctl_state_alu.IN1
pla[66] => ctl_alu_op_low.IN1
pla[67] => ~NO_FANOUT~
pla[68] => ctl_alu_op_low.IN0
pla[68] => ctl_alu_op_low.IN0
pla[69] => ctl_reg_gp_sel_pla69M1T2_2.IN1
pla[69] => ctl_reg_gp_hilo_pla69M1T2_3.IN1
pla[69] => ctl_reg_gp_sel_pla69M1T3_1.IN1
pla[69] => ctl_reg_gp_hilo_pla69M1T3_2.IN1
pla[69] => ctl_reg_gp_sel_pla69M1T4_3.IN1
pla[69] => ctl_reg_gp_hilo_pla69M1T4_4.IN1
pla[69] => ctl_reg_gp_sel_pla69M2T1_1.IN1
pla[69] => ctl_reg_gp_hilo_pla69M2T1_2.IN1
pla[69] => ctl_reg_sys_hilo_pla69M2T2_3.IN1
pla[69] => ctl_reg_gp_sel_pla69M2T3_1.IN1
pla[69] => ctl_reg_gp_hilo_pla69M2T3_2.IN1
pla[69] => ctl_reg_gp_sel_pla69M2T4_2.IN1
pla[69] => ctl_reg_gp_hilo_pla69M2T4_3.IN1
pla[69] => ctl_reg_sys_hilo_pla69M3T1_2.IN1
pla[69] => ctl_reg_sys_hilo_pla69M3T1_7.IN1
pla[69] => ctl_reg_gp_sel_pla69M3T2_2.IN1
pla[69] => ctl_reg_gp_hilo_pla69M3T2_3.IN1
pla[69] => setM1.IN1
pla[70] => ctl_ir_we.IN0
pla[71] => ~NO_FANOUT~
pla[72] => ctl_ir_we.IN0
pla[73] => ctl_ir_we.IN0
pla[74] => ctl_ir_we.IN0
pla[75] => ctl_alu_sel_op2_neg.IN1
pla[75] => ctl_alu_sel_op2_neg.IN1
pla[75] => ctl_alu_sel_op2_neg.IN1
pla[76] => ctl_alu_sel_op2_neg.IN1
pla[76] => ctl_flags_cf_set.IN1
pla[76] => ctl_alu_core_hf.IN1
pla[76] => ctl_flags_nf_we.IN1
pla[76] => ctl_flags_nf_set.IN1
pla[76] => ctl_pf_sel_pla76M1T1_2.IN1
pla[77] => ctl_reg_gp_sel_pla77M1T1_2.IN1
pla[77] => ctl_reg_gp_hilo_pla77M1T1_3.IN1
pla[77] => ctl_reg_gp_sel_pla77M1T2_2.IN1
pla[77] => ctl_reg_gp_hilo_pla77M1T2_3.IN1
pla[77] => ctl_reg_gp_sel_pla77M1T3_1.IN1
pla[77] => ctl_reg_gp_hilo_pla77M1T3_2.IN1
pla[77] => ctl_alu_shift_oe.IN1
pla[77] => ctl_alu_shift_oe.IN1
pla[77] => ctl_daa_oe.IN1
pla[78] => ctl_alu_sel_op2_neg.IN1
pla[78] => ctl_flags_cf_set.IN1
pla[78] => ctl_alu_core_hf.IN1
pla[78] => ctl_flags_nf_we.IN1
pla[78] => ctl_flags_nf_set.IN1
pla[78] => ctl_reg_gp_sel_pla78M1T1_2.IN1
pla[78] => ctl_reg_gp_hilo_pla78M1T1_3.IN1
pla[78] => ctl_pf_sel_pla78M1T1_8.IN1
pla[79] => ctl_alu_sel_op2_neg.IN1
pla[79] => ctl_flags_cf_cpl.IN1
pla[79] => ctl_alu_core_hf.IN1
pla[79] => ctl_flags_nf_we.IN1
pla[79] => ctl_flags_nf_set.IN1
pla[79] => ctl_reg_gp_sel_pla79M1T1_2.IN1
pla[79] => ctl_reg_gp_hilo_pla79M1T1_3.IN1
pla[79] => ctl_pf_sel_pla79M1T1_8.IN1
pla[80] => ctl_alu_core_hf.IN1
pla[80] => ctl_flags_nf_we.IN1
pla[80] => ctl_flags_nf_clr.IN1
pla[80] => ctl_reg_gp_sel_pla80M1T1_2.IN1
pla[80] => ctl_reg_gp_hilo_pla80M1T1_3.IN1
pla[80] => ctl_pf_sel_pla80M1T1_8.IN1
pla[81] => ctl_reg_gp_sel_pla81M1T1_2.IN1
pla[81] => ctl_reg_gp_hilo_pla81M1T1_3.IN1
pla[81] => ctl_reg_gp_sel_pla81M1T2_2.IN1
pla[81] => ctl_reg_gp_hilo_pla81M1T2_3.IN1
pla[81] => ctl_reg_gp_sel_pla81M1T3_1.IN1
pla[81] => ctl_reg_gp_hilo_pla81M1T3_2.IN1
pla[81] => ctl_alu_op1_sel_zero.IN1
pla[81] => ctl_alu_op_low.IN1
pla[82] => ctl_reg_gp_sel_pla82M1T1_2.IN1
pla[82] => ctl_reg_gp_hilo_pla82M1T1_3.IN1
pla[82] => ctl_pf_sel_pla82M1T1_16.IN1
pla[82] => ctl_reg_gp_sel_pla82M1T2_2.IN1
pla[82] => ctl_reg_gp_hilo_pla82M1T2_3.IN1
pla[82] => ctl_reg_gp_sel_pla82M1T3_1.IN1
pla[82] => ctl_reg_gp_hilo_pla82M1T3_2.IN1
pla[82] => ctl_alu_op1_sel_zero.IN1
pla[82] => ctl_alu_op_low.IN1
pla[83] => ctl_reg_gp_sel_pla83M1T1_2.IN1
pla[83] => ctl_reg_gp_hilo_pla83M1T1_3.IN1
pla[83] => ctl_pf_sel_pla83M1T1_19.IN1
pla[83] => ctl_reg_gp_sel_pla83M1T2_2.IN1
pla[83] => ctl_reg_gp_hilo_pla83M1T2_3.IN1
pla[83] => ctl_reg_gp_sel_pla83M1T3_1.IN1
pla[83] => ctl_reg_gp_hilo_pla83M1T3_2.IN1
pla[83] => ctl_reg_sys_hilo_pla83M1T4_3.IN1
pla[83] => ctl_alu_op_low.IN1
pla[83] => setM1.IN1
pla[84] => ctl_flags_cf_set.IN1
pla[84] => ctl_alu_core_hf.IN1
pla[84] => ctl_flags_nf_we.IN1
pla[84] => ctl_flags_nf_clr.IN1
pla[84] => ctl_reg_gp_sel_pla84M1T1_2.IN1
pla[84] => ctl_reg_gp_hilo_pla84M1T1_3.IN1
pla[84] => ctl_pf_sel_pla84M1T1_8.IN1
pla[85] => ctl_alu_core_S.IN1
pla[85] => ctl_flags_cf_set.IN1
pla[85] => ctl_flags_nf_we.IN1
pla[85] => ctl_flags_nf_clr.IN1
pla[85] => ctl_reg_gp_sel_pla85M1T1_2.IN1
pla[85] => ctl_reg_gp_hilo_pla85M1T1_3.IN1
pla[85] => ctl_flags_cf_set.IN1
pla[86] => ctl_alu_core_R.IN1
pla[86] => ctl_alu_core_V.IN1
pla[86] => ctl_alu_core_S.IN1
pla[86] => ctl_flags_cf_set.IN1
pla[86] => ctl_flags_cf_cpl.IN1
pla[86] => ctl_flags_nf_we.IN1
pla[86] => ctl_flags_nf_clr.IN1
pla[86] => ctl_reg_gp_sel_pla86M1T1_2.IN1
pla[86] => ctl_reg_gp_hilo_pla86M1T1_3.IN1
pla[86] => ctl_flags_cf_set.IN1
pla[87] => ~NO_FANOUT~
pla[88] => ctl_alu_core_R.IN1
pla[88] => ctl_flags_cf_set.IN1
pla[88] => ctl_flags_cf_cpl.IN1
pla[88] => ctl_flags_nf_we.IN1
pla[88] => ctl_flags_nf_clr.IN1
pla[88] => ctl_reg_gp_sel_pla88M1T1_2.IN1
pla[88] => ctl_reg_gp_hilo_pla88M1T1_3.IN1
pla[88] => ctl_flags_cf_set.IN1
pla[89] => ctl_alu_oe.IN1
pla[89] => ctl_reg_gp_sel_pla89M1T2_2.IN1
pla[89] => ctl_reg_gp_hilo_pla89M1T2_3.IN1
pla[89] => ctl_reg_gp_sel_pla89M1T3_1.IN1
pla[89] => ctl_reg_gp_hilo_pla89M1T3_2.IN1
pla[89] => ctl_alu_op_low.IN1
pla[89] => ctl_alu_core_R.IN1
pla[90] => ~NO_FANOUT~
pla[91] => ctl_mWrite.IN1
pla[91] => ctl_mRead.IN1
pla[92] => ctl_alu_oe.IN1
pla[92] => ctl_reg_gp_sel_pla92M1T2_2.IN1
pla[92] => ctl_reg_gp_hilo_pla92M1T2_3.IN1
pla[92] => ctl_reg_gp_sel_pla92M1T3_1.IN1
pla[92] => ctl_reg_gp_hilo_pla92M1T3_2.IN1
pla[92] => ctl_alu_op_low.IN1
pla[92] => ctl_alu_core_R.IN1
pla[93] => ~NO_FANOUT~
pla[94] => ~NO_FANOUT~
pla[95] => ctl_state_halt_set.IN1
pla[95] => validPLA.IN1
pla[96] => ctl_sw_1d.IN1
pla[96] => ctl_im_we.IN1
pla[96] => validPLA.IN1
pla[97] => ctl_iffx_we.IN1
pla[97] => validPLA.IN1
pla[97] => ctl_no_ints.IN1
pla[98] => ~NO_FANOUT~
pla[99] => rsel0.IN1
pla[100] => ctl_reg_gp_sel.IN1
pla[100] => ctl_reg_gp_sel.IN1
pla[100] => ctl_reg_gp_sel.IN1
pla[100] => ctl_reg_gp_sel.IN1
pla[100] => ctl_reg_gp_sel.IN1
pla[100] => ctl_reg_gp_sel.IN1
pla[100] => ctl_reg_gp_sel.IN1
pla[100] => ctl_reg_gp_sel.IN1
pla[100] => ctl_reg_gp_sel.IN1
pla[100] => ctl_reg_gp_sel.IN1
pla[100] => ctl_reg_gp_sel.IN1
pla[100] => ctl_reg_gp_sel.IN1
pla[100] => comb.IN0
pla[101] => ctl_reg_gp_sel.IN1
pla[101] => ctl_reg_gp_sel.IN1
pla[101] => ctl_reg_gp_sel.IN1
pla[101] => ctl_reg_gp_sel.IN1
pla[101] => ctl_reg_gp_sel.IN1
pla[101] => ctl_reg_gp_sel.IN1
pla[101] => ctl_reg_gp_sel.IN1
pla[101] => ctl_reg_gp_sel.IN1
pla[101] => ctl_reg_gp_sel.IN1
pla[101] => ctl_reg_gp_sel.IN1
pla[101] => ctl_reg_gp_sel.IN1
pla[101] => ctl_reg_gp_sel.IN1
pla[101] => comb.IN1
pla[102] => rsel3.IN1
pla[102] => ctl_reg_sys_hilo.IN1
pla[102] => ctl_reg_sys_hilo.IN1
pla[102] => ctl_inc_dec.IN1
pla[102] => ctl_inc_dec.IN1
pla[102] => ctl_inc_dec.IN1
pla[102] => ctl_alu_op_low.IN1
pla[102] => ctl_inc_dec.IN1
pla[102] => ctl_iffx_bit.IN1
pla[102] => ctl_mRead.IN1
pla[102] => ctl_inc_dec.IN1
pla[102] => ctl_inc_dec.IN1
pla[102] => ctl_mRead.IN1
pla[102] => ctl_alu_op_low.IN1
pla[102] => ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2.IN1
pla[102] => ctl_reg_sys_hilo.IN1
pla[102] => ctl_reg_sys_hilo.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => ctl_reg_gp_sel.IN1
pla[103] => comb.IN0
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => ctl_reg_gp_sel.IN1
pla[104] => comb.IN1
pla[104] => ctl_state_iy_set.IN1
in_intr => ctl_bus_ff_oe.IN0
in_intr => ctl_mRead.IN0
in_intr => pc_inc_hold.IN0
in_intr => ctl_bus_ff_oe.IN1
in_nmi => ctl_sw_mask543_en.IN1
in_nmi => ctl_66_oe.IN1
in_nmi => pc_inc_hold.IN1
in_nmi => ctl_bus_ff_oe.IN1
in_nmi => ctl_sw_1d.IN1
in_halt => pc_inc_hold.IN1
in_halt => ctl_bus_zero_oe.IN1
im1 => ctl_bus_ff_oe.IN1
im1 => ctl_bus_ff_oe.IN0
im2 => ctl_mRead.IN1
im2 => ctl_bus_ff_oe.IN1
use_ixiy => ixy_d.IN1
use_ixiy => ixy_d.IN1
use_ixiy => ixy_d.IN1
use_ixiy => ixy_d.IN1
use_ixiy => ctl_state_alu.IN1
use_ixiy => ctl_ir_we.IN1
use_ixiy => ctl_ir_we.IN1
use_ixiy => ctl_ir_we.IN1
use_ixiy => ctl_ir_we.IN1
use_ixiy => ctl_mRead.IN1
use_ixiy => ctl_mRead.IN1
use_ixiy => ctl_mWrite.IN1
flags_cond_true => ctl_reg_sys_hilo.IN1
flags_cond_true => ctl_reg_sel_wz.IN1
flags_cond_true => ctl_reg_sel_wz.IN1
flags_cond_true => setM1.IN1
flags_cond_true => setM1.IN1
flags_cond_true => setM1.IN1
flags_cond_true => nextM.IN1
repeat_en => setM1.IN1
flags_zf => setM1.IN1
flags_zf => setM1.IN1
flags_zf => setM1.IN1
flags_nf => ctl_flags_hf_cpl.IN1
flags_nf => ctl_flags_cf_cpl.IN1
flags_nf => ctl_flags_cf_cpl.IN1
flags_nf => ctl_flags_cf_cpl.IN1
flags_nf => ctl_flags_hf_cpl.IN1
flags_nf => ctl_flags_hf_cpl.IN1
flags_nf => ctl_flags_cf_cpl.IN1
flags_nf => ctl_alu_sel_op2_neg.IN1
flags_nf => ctl_flags_hf_cpl.IN1
flags_nf => ctl_alu_sel_op2_neg.IN1
flags_nf => ctl_flags_hf_cpl.IN1
flags_nf => ctl_flags_cf_cpl.IN1
flags_nf => ctl_flags_cf_cpl.IN1
flags_nf => ctl_flags_cf_cpl.IN1
flags_sf => ctl_alu_sel_op2_neg.IN1
flags_sf => ctl_alu_sel_op2_neg.IN1
flags_sf => ctl_alu_sel_op2_neg.IN1
flags_sf => ctl_alu_sel_op2_neg.IN1
flags_sf => ctl_alu_sel_op2_neg.IN1
flags_sf => ctl_alu_sel_op2_neg.IN1
flags_sf => ctl_alu_sel_op2_neg.IN1
flags_sf => ctl_alu_sel_op2_neg.IN1
flags_cf => ctl_flags_hf_cpl.IN1
M1 => ctl_state_alu.IN0
M1 => ctl_reg_sys_hilo_1M1T1_3.IN0
M1 => setM1.IN0
M1 => ctl_reg_sys_hilo_1M1T3_3.IN0
M1 => ctl_mRead.IN0
M1 => ctl_reg_sys_hilo_1M1T2_2.IN0
M1 => ctl_inc_limit6.IN0
M1 => fFetch.DATAIN
M2 => ctl_state_alu.IN0
M2 => ctl_state_alu.IN0
M2 => ctl_alu_sel_op2_neg.IN0
M2 => ctl_alu_op_low.IN0
M2 => ctl_mWrite.IN0
M3 => ixy_d.IN0
M3 => ixy_d.IN0
M3 => ixy_d.IN0
M3 => ixy_d.IN0
M3 => ixy_d.IN0
M4 => ctl_state_alu.IN0
M4 => ctl_alu_sel_op2_neg.IN1
M4 => ctl_mWrite.IN0
M4 => setM1.IN0
M4 => ctl_alu_shift_oe.IN0
M4 => ctl_ir_we.IN0
M5 => ctl_sw_4u.IN0
M5 => setM1.IN0
M5 => ctl_sw_4u.IN0
M5 => ctl_alu_oe.IN0
M5 => ctl_reg_in_hi.IN0
T1 => ctl_state_alu.IN1
T1 => ctl_reg_sys_hilo_1M1T1_3.IN1
T1 => ctl_alu_oe.IN1
T1 => ixy_d.IN1
T1 => ctl_ir_we.IN1
T1 => ctl_alu_shift_oe.IN1
T2 => ctl_alu_op_low.IN1
T2 => ctl_sw_4u.IN1
T2 => ctl_alu_shift_oe.IN1
T2 => ixy_d.IN1
T2 => ctl_reg_sys_hilo_1M1T2_2.IN1
T2 => ctl_reg_gp_sel_ixy_dT2_1.IN1
T2 => ctl_reg_gp_hilo_ixy_dT2_2.IN1
T3 => ctl_state_alu.IN1
T3 => ctl_state_alu.IN1
T3 => ctl_reg_sys_hilo_1M1T3_3.IN1
T3 => ctl_reg_in_hi.IN1
T3 => ixy_d.IN1
T3 => ctl_reg_sys_hilo_ixy_dT3_3.IN1
T3 => ctl_inc_limit6.IN1
T4 => ctl_sw_4u.IN1
T4 => ctl_state_alu.IN1
T4 => ctl_mWrite.IN1
T4 => ctl_mWrite.IN1
T4 => ixy_d.IN1
T4 => ctl_reg_gp_sel_ixy_dT4_1.IN1
T4 => ctl_reg_gp_hilo_ixy_dT4_2.IN1
T5 => setM1.IN1
T5 => setM1.IN1
T5 => ctl_mRead.IN1
T5 => ixy_d.IN1
T5 => ctl_reg_sys_hilo_ixy_dT5_2.IN1
T5 => ctl_reg_sys_hilo_ixy_dT5_7.IN1
T6 => setM1.IN1


|spectrum|z80_top_direct_n:z80_|interrupts:interrupts_
ctl_iff1_iff2 => SYNTHESIZED_WIRE_1.IN1
ctl_iff1_iff2 => SYNTHESIZED_WIRE_17.IN0
ctl_iff1_iff2 => SYNTHESIZED_WIRE_2.IN0
nmi => nmi_armed.CLK
setM1 => test1.IN0
intr => SYNTHESIZED_WIRE_13.IN1
ctl_iffx_we => SYNTHESIZED_WIRE_17.IN1
ctl_iffx_we => DFFE_instIFF2.ENA
ctl_iffx_bit => SYNTHESIZED_WIRE_2.IN1
ctl_iffx_bit => DFFE_instIFF2.DATAIN
ctl_im_we => im2~reg0.ENA
ctl_im_we => im1~reg0.ENA
clk => im2~reg0.CLK
clk => im1~reg0.CLK
clk => DFFE_instIFF2.CLK
clk => iff1.CLK
clk => int_armed.CLK
clk => DFFE_inst44.CLK
clk => in_nmi_ALTERA_SYNTHESIZED.CLK
ctl_no_ints => test1.IN1
nreset => SYNTHESIZED_WIRE_21.IN1
nreset => SYNTHESIZED_WIRE_12.IN1
nreset => SYNTHESIZED_WIRE_9.IN1
nreset => im1~reg0.ACLR
nreset => im2~reg0.ACLR
nreset => in_nmi_ALTERA_SYNTHESIZED.ACLR
nreset => DFFE_inst44.ACLR
db[0] => SYNTHESIZED_WIRE_20.IN0
db[0] => SYNTHESIZED_WIRE_19.IN0
db[1] => SYNTHESIZED_WIRE_20.IN1
db[1] => SYNTHESIZED_WIRE_19.IN1
iff2 <= DFFE_instIFF2.DB_MAX_OUTPUT_PORT_TYPE
im1 <= im1~reg0.DB_MAX_OUTPUT_PORT_TYPE
im2 <= im2~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_nmi <= in_nmi_ALTERA_SYNTHESIZED.DB_MAX_OUTPUT_PORT_TYPE
in_intr <= in_intr_ALTERA_SYNTHESIZED.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|ir:ir_
ctl_ir_we => SYNTHESIZED_WIRE_0.IN0
clk => opcode[0]~reg0.CLK
clk => opcode[1]~reg0.CLK
clk => opcode[2]~reg0.CLK
clk => opcode[3]~reg0.CLK
clk => opcode[4]~reg0.CLK
clk => opcode[5]~reg0.CLK
clk => opcode[6]~reg0.CLK
clk => opcode[7]~reg0.CLK
nreset => opcode[0]~reg0.ACLR
nreset => opcode[1]~reg0.ACLR
nreset => opcode[2]~reg0.ACLR
nreset => opcode[3]~reg0.ACLR
nreset => opcode[4]~reg0.ACLR
nreset => opcode[5]~reg0.ACLR
nreset => opcode[6]~reg0.ACLR
nreset => opcode[7]~reg0.ACLR
nhold_clk_wait => SYNTHESIZED_WIRE_0.IN1
db[0] => opcode[0]~reg0.DATAIN
db[1] => opcode[1]~reg0.DATAIN
db[2] => opcode[2]~reg0.DATAIN
db[3] => opcode[3]~reg0.DATAIN
db[4] => opcode[4]~reg0.DATAIN
db[5] => opcode[5]~reg0.DATAIN
db[6] => opcode[6]~reg0.DATAIN
db[7] => opcode[7]~reg0.DATAIN
opcode[0] <= opcode[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
opcode[1] <= opcode[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
opcode[2] <= opcode[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
opcode[3] <= opcode[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
opcode[4] <= opcode[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
opcode[5] <= opcode[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
opcode[6] <= opcode[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
opcode[7] <= opcode[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|pin_control:pin_control_
fFetch => SYNTHESIZED_WIRE_9.IN0
fFetch => SYNTHESIZED_WIRE_4.IN0
fFetch => SYNTHESIZED_WIRE_6.IN0
fMRead => SYNTHESIZED_WIRE_9.IN1
fMRead => SYNTHESIZED_WIRE_2.IN0
fMWrite => SYNTHESIZED_WIRE_9.IN1
fMWrite => SYNTHESIZED_WIRE_1.IN1
fIORead => SYNTHESIZED_WIRE_9.IN1
fIORead => SYNTHESIZED_WIRE_3.IN0
fIOWrite => SYNTHESIZED_WIRE_9.IN1
fIOWrite => SYNTHESIZED_WIRE_9.IN1
fIOWrite => SYNTHESIZED_WIRE_0.IN1
T1 => SYNTHESIZED_WIRE_5.IN1
T2 => SYNTHESIZED_WIRE_7.IN0
T2 => SYNTHESIZED_WIRE_4.IN1
T2 => SYNTHESIZED_WIRE_2.IN1
T3 => SYNTHESIZED_WIRE_7.IN1
T3 => SYNTHESIZED_WIRE_3.IN1
T3 => SYNTHESIZED_WIRE_6.IN1
T4 => SYNTHESIZED_WIRE_8.IN1
bus_ab_pin_we <= bus_ab_pin_we.DB_MAX_OUTPUT_PORT_TYPE
bus_db_pin_oe <= bus_db_pin_oe.DB_MAX_OUTPUT_PORT_TYPE
bus_db_pin_re <= bus_db_pin_re.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|pla_decode:pla_decode_
prefix[0] => Equal0.IN0
prefix[0] => Equal10.IN0
prefix[0] => Equal11.IN0
prefix[0] => Equal13.IN0
prefix[0] => Equal16.IN0
prefix[0] => Equal17.IN0
prefix[0] => Equal22.IN0
prefix[0] => Equal26.IN0
prefix[0] => Equal27.IN0
prefix[0] => Equal28.IN0
prefix[0] => Equal38.IN0
prefix[0] => Equal48.IN0
prefix[0] => Equal55.IN0
prefix[0] => Equal68.IN0
prefix[0] => Equal69.IN0
prefix[0] => Equal75.IN0
prefix[0] => Equal78.IN0
prefix[1] => Equal46.IN0
prefix[1] => Equal57.IN0
prefix[1] => Equal58.IN0
prefix[1] => Equal59.IN0
prefix[1] => Equal60.IN0
prefix[2] => Equal1.IN0
prefix[2] => Equal2.IN0
prefix[2] => Equal3.IN0
prefix[2] => Equal4.IN0
prefix[2] => Equal5.IN0
prefix[2] => Equal6.IN0
prefix[2] => Equal7.IN0
prefix[2] => Equal8.IN0
prefix[2] => Equal9.IN0
prefix[2] => Equal12.IN0
prefix[2] => Equal14.IN0
prefix[2] => Equal15.IN0
prefix[2] => Equal18.IN0
prefix[2] => Equal19.IN0
prefix[2] => Equal20.IN0
prefix[2] => Equal21.IN0
prefix[2] => Equal23.IN0
prefix[2] => Equal24.IN0
prefix[2] => Equal25.IN0
prefix[2] => Equal29.IN0
prefix[2] => Equal30.IN0
prefix[2] => Equal31.IN0
prefix[2] => Equal32.IN0
prefix[2] => Equal33.IN1
prefix[2] => Equal34.IN0
prefix[2] => Equal35.IN0
prefix[2] => Equal36.IN0
prefix[2] => Equal37.IN0
prefix[2] => Equal39.IN0
prefix[2] => Equal40.IN0
prefix[2] => Equal42.IN0
prefix[2] => Equal43.IN0
prefix[2] => Equal44.IN0
prefix[2] => Equal45.IN0
prefix[2] => Equal47.IN0
prefix[2] => Equal49.IN1
prefix[2] => Equal50.IN1
prefix[2] => Equal51.IN0
prefix[2] => Equal52.IN0
prefix[2] => Equal53.IN0
prefix[2] => Equal54.IN0
prefix[2] => Equal56.IN0
prefix[2] => Equal61.IN0
prefix[2] => Equal63.IN0
prefix[2] => Equal67.IN0
prefix[2] => Equal74.IN0
prefix[2] => Equal76.IN0
prefix[2] => Equal77.IN0
prefix[2] => Equal79.IN0
prefix[3] => Equal62.IN0
prefix[3] => Equal64.IN0
prefix[3] => Equal65.IN0
prefix[3] => Equal66.IN0
prefix[3] => Equal70.IN0
prefix[3] => Equal71.IN0
prefix[3] => Equal72.IN0
prefix[3] => Equal73.IN0
prefix[4] => Equal49.IN0
prefix[4] => Equal50.IN0
prefix[5] => Equal33.IN0
prefix[5] => Equal41.IN0
prefix[6] => ~NO_FANOUT~
opcode[0] => Equal1.IN5
opcode[0] => Equal2.IN6
opcode[0] => Equal3.IN6
opcode[0] => Equal4.IN6
opcode[0] => Equal5.IN5
opcode[0] => Equal6.IN1
opcode[0] => Equal7.IN14
opcode[0] => Equal8.IN2
opcode[0] => Equal9.IN5
opcode[0] => Equal10.IN3
opcode[0] => Equal11.IN14
opcode[0] => Equal12.IN14
opcode[0] => Equal13.IN5
opcode[0] => Equal14.IN4
opcode[0] => Equal15.IN14
opcode[0] => Equal16.IN4
opcode[0] => Equal17.IN14
opcode[0] => Equal18.IN3
opcode[0] => Equal19.IN5
opcode[0] => Equal20.IN3
opcode[0] => Equal21.IN14
opcode[0] => Equal23.IN5
opcode[0] => Equal24.IN4
opcode[0] => Equal25.IN14
opcode[0] => Equal26.IN3
opcode[0] => Equal27.IN3
opcode[0] => Equal28.IN2
opcode[0] => Equal29.IN4
opcode[0] => Equal30.IN5
opcode[0] => Equal31.IN14
opcode[0] => Equal32.IN14
opcode[0] => Equal33.IN14
opcode[0] => Equal34.IN14
opcode[0] => Equal35.IN14
opcode[0] => Equal36.IN5
opcode[0] => Equal37.IN14
opcode[0] => Equal38.IN3
opcode[0] => Equal39.IN14
opcode[0] => Equal40.IN14
opcode[0] => Equal41.IN5
opcode[0] => Equal42.IN14
opcode[0] => Equal43.IN6
opcode[0] => Equal44.IN14
opcode[0] => Equal46.IN14
opcode[0] => Equal47.IN5
opcode[0] => Equal48.IN4
opcode[0] => Equal49.IN14
opcode[0] => Equal52.IN14
opcode[0] => Equal55.IN14
opcode[0] => Equal56.IN2
opcode[0] => Equal61.IN2
opcode[0] => Equal63.IN4
opcode[0] => Equal67.IN5
opcode[0] => Equal68.IN14
opcode[0] => Equal69.IN5
opcode[0] => Equal74.IN6
opcode[0] => Equal76.IN5
opcode[0] => Equal77.IN14
opcode[0] => Equal78.IN14
opcode[0] => Equal79.IN6
opcode[0] => pla[99].DATAIN
opcode[1] => Equal1.IN14
opcode[1] => Equal2.IN5
opcode[1] => Equal3.IN14
opcode[1] => Equal4.IN14
opcode[1] => Equal5.IN14
opcode[1] => Equal6.IN14
opcode[1] => Equal7.IN1
opcode[1] => Equal8.IN1
opcode[1] => Equal9.IN4
opcode[1] => Equal10.IN14
opcode[1] => Equal11.IN13
opcode[1] => Equal12.IN1
opcode[1] => Equal13.IN4
opcode[1] => Equal14.IN14
opcode[1] => Equal15.IN2
opcode[1] => Equal16.IN3
opcode[1] => Equal17.IN3
opcode[1] => Equal18.IN14
opcode[1] => Equal19.IN14
opcode[1] => Equal20.IN2
opcode[1] => Equal21.IN13
opcode[1] => Equal22.IN13
opcode[1] => Equal23.IN4
opcode[1] => Equal24.IN3
opcode[1] => Equal25.IN2
opcode[1] => Equal26.IN2
opcode[1] => Equal27.IN2
opcode[1] => Equal28.IN14
opcode[1] => Equal29.IN14
opcode[1] => Equal30.IN4
opcode[1] => Equal31.IN3
opcode[1] => Equal32.IN13
opcode[1] => Equal33.IN5
opcode[1] => Equal34.IN13
opcode[1] => Equal35.IN3
opcode[1] => Equal36.IN4
opcode[1] => Equal37.IN13
opcode[1] => Equal38.IN14
opcode[1] => Equal39.IN13
opcode[1] => Equal40.IN13
opcode[1] => Equal41.IN4
opcode[1] => Equal42.IN4
opcode[1] => Equal43.IN14
opcode[1] => Equal44.IN3
opcode[1] => Equal45.IN13
opcode[1] => Equal46.IN2
opcode[1] => Equal47.IN4
opcode[1] => Equal48.IN3
opcode[1] => Equal49.IN4
opcode[1] => Equal52.IN4
opcode[1] => Equal54.IN13
opcode[1] => Equal55.IN2
opcode[1] => Equal56.IN14
opcode[1] => Equal61.IN14
opcode[1] => Equal63.IN3
opcode[1] => Equal67.IN4
opcode[1] => Equal68.IN13
opcode[1] => Equal69.IN4
opcode[1] => Equal74.IN5
opcode[1] => Equal75.IN3
opcode[1] => Equal76.IN4
opcode[1] => Equal77.IN5
opcode[1] => Equal78.IN3
opcode[1] => Equal79.IN5
opcode[1] => pla[100].DATAIN
opcode[2] => Equal0.IN12
opcode[2] => Equal1.IN13
opcode[2] => Equal2.IN14
opcode[2] => Equal3.IN5
opcode[2] => Equal4.IN13
opcode[2] => Equal5.IN13
opcode[2] => Equal6.IN13
opcode[2] => Equal7.IN13
opcode[2] => Equal8.IN14
opcode[2] => Equal9.IN14
opcode[2] => Equal10.IN13
opcode[2] => Equal11.IN12
opcode[2] => Equal12.IN13
opcode[2] => Equal13.IN3
opcode[2] => Equal14.IN3
opcode[2] => Equal15.IN1
opcode[2] => Equal16.IN14
opcode[2] => Equal17.IN13
opcode[2] => Equal19.IN4
opcode[2] => Equal20.IN1
opcode[2] => Equal21.IN12
opcode[2] => Equal22.IN12
opcode[2] => Equal23.IN14
opcode[2] => Equal24.IN14
opcode[2] => Equal25.IN13
opcode[2] => Equal26.IN14
opcode[2] => Equal27.IN14
opcode[2] => Equal28.IN13
opcode[2] => Equal29.IN13
opcode[2] => Equal30.IN14
opcode[2] => Equal31.IN13
opcode[2] => Equal32.IN12
opcode[2] => Equal33.IN4
opcode[2] => Equal34.IN3
opcode[2] => Equal35.IN13
opcode[2] => Equal36.IN14
opcode[2] => Equal37.IN12
opcode[2] => Equal38.IN2
opcode[2] => Equal39.IN12
opcode[2] => Equal40.IN12
opcode[2] => Equal41.IN14
opcode[2] => Equal42.IN3
opcode[2] => Equal43.IN5
opcode[2] => Equal44.IN2
opcode[2] => Equal45.IN3
opcode[2] => Equal46.IN1
opcode[2] => Equal47.IN3
opcode[2] => Equal48.IN2
opcode[2] => Equal49.IN3
opcode[2] => Equal52.IN3
opcode[2] => Equal54.IN1
opcode[2] => Equal55.IN13
opcode[2] => Equal56.IN13
opcode[2] => Equal61.IN1
opcode[2] => Equal63.IN2
opcode[2] => Equal67.IN3
opcode[2] => Equal68.IN2
opcode[2] => Equal69.IN3
opcode[2] => Equal74.IN4
opcode[2] => Equal75.IN13
opcode[2] => Equal76.IN3
opcode[2] => Equal77.IN4
opcode[2] => Equal78.IN2
opcode[2] => Equal79.IN14
opcode[2] => pla[101].DATAIN
opcode[3] => Equal1.IN4
opcode[3] => Equal2.IN4
opcode[3] => Equal3.IN4
opcode[3] => Equal4.IN5
opcode[3] => Equal5.IN4
opcode[3] => Equal6.IN12
opcode[3] => Equal9.IN13
opcode[3] => Equal12.IN12
opcode[3] => Equal14.IN13
opcode[3] => Equal18.IN12
opcode[3] => Equal19.IN3
opcode[3] => Equal21.IN11
opcode[3] => Equal23.IN13
opcode[3] => Equal24.IN13
opcode[3] => Equal27.IN13
opcode[3] => Equal29.IN3
opcode[3] => Equal32.IN1
opcode[3] => Equal33.IN13
opcode[3] => Equal36.IN3
opcode[3] => Equal39.IN2
opcode[3] => Equal41.IN3
opcode[3] => Equal42.IN13
opcode[3] => Equal43.IN4
opcode[3] => Equal45.IN12
opcode[3] => Equal50.IN11
opcode[3] => Equal56.IN1
opcode[3] => Equal62.IN3
opcode[3] => Equal63.IN14
opcode[3] => Equal64.IN11
opcode[3] => Equal65.IN2
opcode[3] => Equal66.IN1
opcode[3] => Equal67.IN2
opcode[3] => Equal70.IN11
opcode[3] => Equal71.IN11
opcode[3] => Equal72.IN11
opcode[3] => Equal73.IN2
opcode[3] => Equal74.IN3
opcode[3] => Equal76.IN14
opcode[3] => Equal77.IN13
opcode[3] => pla[102].DATAIN
opcode[4] => Equal0.IN10
opcode[4] => Equal1.IN3
opcode[4] => Equal2.IN13
opcode[4] => Equal3.IN3
opcode[4] => Equal4.IN4
opcode[4] => Equal5.IN12
opcode[4] => Equal9.IN12
opcode[4] => Equal13.IN13
opcode[4] => Equal19.IN13
opcode[4] => Equal21.IN1
opcode[4] => Equal23.IN3
opcode[4] => Equal24.IN12
opcode[4] => Equal25.IN11
opcode[4] => Equal29.IN12
opcode[4] => Equal30.IN3
opcode[4] => Equal31.IN2
opcode[4] => Equal32.IN11
opcode[4] => Equal33.IN3
opcode[4] => Equal36.IN13
opcode[4] => Equal39.IN1
opcode[4] => Equal41.IN13
opcode[4] => Equal42.IN2
opcode[4] => Equal43.IN13
opcode[4] => Equal45.IN2
opcode[4] => Equal48.IN13
opcode[4] => Equal50.IN4
opcode[4] => Equal62.IN2
opcode[4] => Equal63.IN13
opcode[4] => Equal64.IN1
opcode[4] => Equal65.IN1
opcode[4] => Equal66.IN11
opcode[4] => Equal67.IN14
opcode[4] => Equal69.IN2
opcode[4] => Equal70.IN10
opcode[4] => Equal71.IN10
opcode[4] => Equal72.IN2
opcode[4] => Equal73.IN11
opcode[4] => Equal74.IN2
opcode[4] => Equal76.IN2
opcode[4] => Equal77.IN3
opcode[4] => Equal79.IN4
opcode[4] => pla[103].DATAIN
opcode[5] => Equal0.IN2
opcode[5] => Equal1.IN12
opcode[5] => Equal2.IN3
opcode[5] => Equal4.IN3
opcode[5] => Equal5.IN3
opcode[5] => Equal7.IN10
opcode[5] => Equal9.IN3
opcode[5] => Equal10.IN2
opcode[5] => Equal11.IN2
opcode[5] => Equal13.IN2
opcode[5] => Equal16.IN2
opcode[5] => Equal17.IN2
opcode[5] => Equal19.IN12
opcode[5] => Equal20.IN12
opcode[5] => Equal21.IN10
opcode[5] => Equal23.IN12
opcode[5] => Equal24.IN11
opcode[5] => Equal25.IN1
opcode[5] => Equal29.IN11
opcode[5] => Equal30.IN12
opcode[5] => Equal31.IN1
opcode[5] => Equal32.IN10
opcode[5] => Equal33.IN2
opcode[5] => Equal36.IN12
opcode[5] => Equal39.IN11
opcode[5] => Equal40.IN1
opcode[5] => Equal41.IN12
opcode[5] => Equal42.IN1
opcode[5] => Equal43.IN3
opcode[5] => Equal45.IN1
opcode[5] => Equal48.IN12
opcode[5] => Equal50.IN3
opcode[5] => Equal62.IN1
opcode[5] => Equal63.IN1
opcode[5] => Equal64.IN10
opcode[5] => Equal65.IN11
opcode[5] => Equal66.IN10
opcode[5] => Equal67.IN1
opcode[5] => Equal69.IN13
opcode[5] => Equal70.IN9
opcode[5] => Equal71.IN1
opcode[5] => Equal72.IN1
opcode[5] => Equal73.IN1
opcode[5] => Equal74.IN1
opcode[5] => Equal75.IN2
opcode[5] => Equal76.IN1
opcode[5] => Equal77.IN2
opcode[5] => Equal79.IN3
opcode[5] => pla[104].DATAIN
opcode[6] => Equal0.IN9
opcode[6] => Equal1.IN2
opcode[6] => Equal2.IN2
opcode[6] => Equal3.IN2
opcode[6] => Equal4.IN2
opcode[6] => Equal5.IN2
opcode[6] => Equal6.IN9
opcode[6] => Equal7.IN9
opcode[6] => Equal8.IN10
opcode[6] => Equal9.IN2
opcode[6] => Equal10.IN10
opcode[6] => Equal11.IN9
opcode[6] => Equal12.IN9
opcode[6] => Equal13.IN1
opcode[6] => Equal14.IN2
opcode[6] => Equal15.IN10
opcode[6] => Equal16.IN11
opcode[6] => Equal17.IN10
opcode[6] => Equal18.IN2
opcode[6] => Equal19.IN2
opcode[6] => Equal20.IN11
opcode[6] => Equal21.IN9
opcode[6] => Equal22.IN1
opcode[6] => Equal23.IN2
opcode[6] => Equal24.IN2
opcode[6] => Equal25.IN10
opcode[6] => Equal26.IN1
opcode[6] => Equal27.IN1
opcode[6] => Equal28.IN1
opcode[6] => Equal29.IN2
opcode[6] => Equal30.IN2
opcode[6] => Equal31.IN11
opcode[6] => Equal32.IN9
opcode[6] => Equal33.IN12
opcode[6] => Equal34.IN2
opcode[6] => Equal35.IN2
opcode[6] => Equal36.IN2
opcode[6] => Equal37.IN2
opcode[6] => Equal38.IN1
opcode[6] => Equal39.IN10
opcode[6] => Equal40.IN9
opcode[6] => Equal41.IN2
opcode[6] => Equal42.IN12
opcode[6] => Equal43.IN2
opcode[6] => Equal44.IN10
opcode[6] => Equal45.IN11
opcode[6] => Equal47.IN2
opcode[6] => Equal48.IN1
opcode[6] => Equal49.IN2
opcode[6] => Equal50.IN2
opcode[6] => Equal51.IN1
opcode[6] => Equal52.IN2
opcode[6] => Equal53.IN8
opcode[6] => Equal54.IN9
opcode[6] => Equal55.IN1
opcode[6] => Equal56.IN10
opcode[6] => Equal57.IN8
opcode[6] => Equal58.IN1
opcode[6] => Equal59.IN8
opcode[6] => Equal60.IN2
opcode[6] => Equal61.IN10
opcode[6] => Equal63.IN12
opcode[6] => Equal67.IN13
opcode[6] => Equal68.IN1
opcode[6] => Equal69.IN1
opcode[6] => Equal74.IN14
opcode[6] => Equal75.IN10
opcode[6] => Equal76.IN13
opcode[6] => Equal77.IN1
opcode[6] => Equal78.IN1
opcode[6] => Equal79.IN2
opcode[7] => Equal0.IN1
opcode[7] => Equal1.IN1
opcode[7] => Equal2.IN1
opcode[7] => Equal3.IN1
opcode[7] => Equal4.IN1
opcode[7] => Equal5.IN1
opcode[7] => Equal6.IN8
opcode[7] => Equal7.IN8
opcode[7] => Equal8.IN9
opcode[7] => Equal9.IN1
opcode[7] => Equal10.IN1
opcode[7] => Equal11.IN1
opcode[7] => Equal12.IN8
opcode[7] => Equal13.IN12
opcode[7] => Equal14.IN1
opcode[7] => Equal15.IN9
opcode[7] => Equal16.IN1
opcode[7] => Equal17.IN1
opcode[7] => Equal18.IN1
opcode[7] => Equal19.IN1
opcode[7] => Equal20.IN10
opcode[7] => Equal21.IN8
opcode[7] => Equal22.IN8
opcode[7] => Equal23.IN1
opcode[7] => Equal24.IN1
opcode[7] => Equal25.IN9
opcode[7] => Equal26.IN10
opcode[7] => Equal27.IN10
opcode[7] => Equal28.IN9
opcode[7] => Equal29.IN1
opcode[7] => Equal30.IN1
opcode[7] => Equal31.IN10
opcode[7] => Equal32.IN8
opcode[7] => Equal33.IN11
opcode[7] => Equal34.IN1
opcode[7] => Equal35.IN1
opcode[7] => Equal36.IN1
opcode[7] => Equal37.IN1
opcode[7] => Equal38.IN10
opcode[7] => Equal39.IN9
opcode[7] => Equal40.IN8
opcode[7] => Equal41.IN1
opcode[7] => Equal42.IN11
opcode[7] => Equal43.IN1
opcode[7] => Equal44.IN1
opcode[7] => Equal45.IN10
opcode[7] => Equal47.IN1
opcode[7] => Equal48.IN11
opcode[7] => Equal49.IN10
opcode[7] => Equal50.IN10
opcode[7] => Equal51.IN8
opcode[7] => Equal52.IN1
opcode[7] => Equal53.IN1
opcode[7] => Equal54.IN8
opcode[7] => Equal55.IN9
opcode[7] => Equal56.IN9
opcode[7] => Equal57.IN7
opcode[7] => Equal58.IN8
opcode[7] => Equal59.IN1
opcode[7] => Equal60.IN1
opcode[7] => Equal61.IN9
opcode[7] => Equal63.IN11
opcode[7] => Equal67.IN12
opcode[7] => Equal68.IN9
opcode[7] => Equal69.IN12
opcode[7] => Equal74.IN13
opcode[7] => Equal75.IN1
opcode[7] => Equal76.IN12
opcode[7] => Equal77.IN12
opcode[7] => Equal78.IN10
opcode[7] => Equal79.IN1
pla[0] <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
pla[1] <= Equal1.DB_MAX_OUTPUT_PORT_TYPE
pla[2] <= Equal2.DB_MAX_OUTPUT_PORT_TYPE
pla[3] <= Equal3.DB_MAX_OUTPUT_PORT_TYPE
pla[4] <= <GND>
pla[5] <= Equal4.DB_MAX_OUTPUT_PORT_TYPE
pla[6] <= Equal5.DB_MAX_OUTPUT_PORT_TYPE
pla[7] <= Equal6.DB_MAX_OUTPUT_PORT_TYPE
pla[8] <= Equal7.DB_MAX_OUTPUT_PORT_TYPE
pla[9] <= Equal8.DB_MAX_OUTPUT_PORT_TYPE
pla[10] <= Equal9.DB_MAX_OUTPUT_PORT_TYPE
pla[11] <= Equal10.DB_MAX_OUTPUT_PORT_TYPE
pla[12] <= Equal11.DB_MAX_OUTPUT_PORT_TYPE
pla[13] <= Equal12.DB_MAX_OUTPUT_PORT_TYPE
pla[14] <= <GND>
pla[15] <= Equal13.DB_MAX_OUTPUT_PORT_TYPE
pla[16] <= Equal14.DB_MAX_OUTPUT_PORT_TYPE
pla[17] <= Equal15.DB_MAX_OUTPUT_PORT_TYPE
pla[18] <= <GND>
pla[19] <= <GND>
pla[20] <= Equal16.DB_MAX_OUTPUT_PORT_TYPE
pla[21] <= Equal17.DB_MAX_OUTPUT_PORT_TYPE
pla[22] <= <GND>
pla[23] <= Equal18.DB_MAX_OUTPUT_PORT_TYPE
pla[24] <= Equal19.DB_MAX_OUTPUT_PORT_TYPE
pla[25] <= Equal20.DB_MAX_OUTPUT_PORT_TYPE
pla[26] <= Equal21.DB_MAX_OUTPUT_PORT_TYPE
pla[27] <= Equal22.DB_MAX_OUTPUT_PORT_TYPE
pla[28] <= Equal23.DB_MAX_OUTPUT_PORT_TYPE
pla[29] <= Equal24.DB_MAX_OUTPUT_PORT_TYPE
pla[30] <= Equal25.DB_MAX_OUTPUT_PORT_TYPE
pla[31] <= Equal26.DB_MAX_OUTPUT_PORT_TYPE
pla[32] <= <GND>
pla[33] <= Equal27.DB_MAX_OUTPUT_PORT_TYPE
pla[34] <= Equal28.DB_MAX_OUTPUT_PORT_TYPE
pla[35] <= Equal29.DB_MAX_OUTPUT_PORT_TYPE
pla[36] <= <GND>
pla[37] <= Equal30.DB_MAX_OUTPUT_PORT_TYPE
pla[38] <= Equal31.DB_MAX_OUTPUT_PORT_TYPE
pla[39] <= Equal32.DB_MAX_OUTPUT_PORT_TYPE
pla[40] <= Equal33.DB_MAX_OUTPUT_PORT_TYPE
pla[41] <= <GND>
pla[42] <= Equal34.DB_MAX_OUTPUT_PORT_TYPE
pla[43] <= Equal35.DB_MAX_OUTPUT_PORT_TYPE
pla[44] <= Equal36.DB_MAX_OUTPUT_PORT_TYPE
pla[45] <= Equal37.DB_MAX_OUTPUT_PORT_TYPE
pla[46] <= Equal38.DB_MAX_OUTPUT_PORT_TYPE
pla[47] <= Equal39.DB_MAX_OUTPUT_PORT_TYPE
pla[48] <= Equal40.DB_MAX_OUTPUT_PORT_TYPE
pla[49] <= Equal41.DB_MAX_OUTPUT_PORT_TYPE
pla[50] <= Equal42.DB_MAX_OUTPUT_PORT_TYPE
pla[51] <= Equal43.DB_MAX_OUTPUT_PORT_TYPE
pla[52] <= Equal44.DB_MAX_OUTPUT_PORT_TYPE
pla[53] <= Equal45.DB_MAX_OUTPUT_PORT_TYPE
pla[54] <= <GND>
pla[55] <= Equal46.DB_MAX_OUTPUT_PORT_TYPE
pla[56] <= Equal47.DB_MAX_OUTPUT_PORT_TYPE
pla[57] <= Equal48.DB_MAX_OUTPUT_PORT_TYPE
pla[58] <= Equal49.DB_MAX_OUTPUT_PORT_TYPE
pla[59] <= Equal50.DB_MAX_OUTPUT_PORT_TYPE
pla[60] <= <GND>
pla[61] <= Equal51.DB_MAX_OUTPUT_PORT_TYPE
pla[62] <= <GND>
pla[63] <= <GND>
pla[64] <= Equal52.DB_MAX_OUTPUT_PORT_TYPE
pla[65] <= Equal53.DB_MAX_OUTPUT_PORT_TYPE
pla[66] <= Equal54.DB_MAX_OUTPUT_PORT_TYPE
pla[67] <= <GND>
pla[68] <= Equal55.DB_MAX_OUTPUT_PORT_TYPE
pla[69] <= Equal56.DB_MAX_OUTPUT_PORT_TYPE
pla[70] <= Equal57.DB_MAX_OUTPUT_PORT_TYPE
pla[71] <= <GND>
pla[72] <= Equal58.DB_MAX_OUTPUT_PORT_TYPE
pla[73] <= Equal59.DB_MAX_OUTPUT_PORT_TYPE
pla[74] <= Equal60.DB_MAX_OUTPUT_PORT_TYPE
pla[75] <= Equal61.DB_MAX_OUTPUT_PORT_TYPE
pla[76] <= Equal62.DB_MAX_OUTPUT_PORT_TYPE
pla[77] <= Equal63.DB_MAX_OUTPUT_PORT_TYPE
pla[78] <= Equal64.DB_MAX_OUTPUT_PORT_TYPE
pla[79] <= Equal65.DB_MAX_OUTPUT_PORT_TYPE
pla[80] <= Equal66.DB_MAX_OUTPUT_PORT_TYPE
pla[81] <= Equal67.DB_MAX_OUTPUT_PORT_TYPE
pla[82] <= Equal68.DB_MAX_OUTPUT_PORT_TYPE
pla[83] <= Equal69.DB_MAX_OUTPUT_PORT_TYPE
pla[84] <= Equal70.DB_MAX_OUTPUT_PORT_TYPE
pla[85] <= Equal71.DB_MAX_OUTPUT_PORT_TYPE
pla[86] <= Equal72.DB_MAX_OUTPUT_PORT_TYPE
pla[87] <= <GND>
pla[88] <= Equal73.DB_MAX_OUTPUT_PORT_TYPE
pla[89] <= Equal74.DB_MAX_OUTPUT_PORT_TYPE
pla[90] <= <GND>
pla[91] <= Equal75.DB_MAX_OUTPUT_PORT_TYPE
pla[92] <= Equal76.DB_MAX_OUTPUT_PORT_TYPE
pla[93] <= <GND>
pla[94] <= <GND>
pla[95] <= Equal77.DB_MAX_OUTPUT_PORT_TYPE
pla[96] <= Equal78.DB_MAX_OUTPUT_PORT_TYPE
pla[97] <= Equal79.DB_MAX_OUTPUT_PORT_TYPE
pla[98] <= <GND>
pla[99] <= opcode[0].DB_MAX_OUTPUT_PORT_TYPE
pla[100] <= opcode[1].DB_MAX_OUTPUT_PORT_TYPE
pla[101] <= opcode[2].DB_MAX_OUTPUT_PORT_TYPE
pla[102] <= opcode[3].DB_MAX_OUTPUT_PORT_TYPE
pla[103] <= opcode[4].DB_MAX_OUTPUT_PORT_TYPE
pla[104] <= opcode[5].DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|resets:resets_
reset_in => x1.IN1
reset_in => x1.IN1
clk => SYNTHESIZED_WIRE_12.CLK
clk => clrpc_int.CLK
clk => SYNTHESIZED_WIRE_9.CLK
clk => SYNTHESIZED_WIRE_10.CLK
clk => DFFE_intr_ff3.CLK
clk => x1.CLK
M1 => SYNTHESIZED_WIRE_11.IN0
T2 => SYNTHESIZED_WIRE_11.IN1
fpga_reset => x1.PRESET
fpga_reset => SYNTHESIZED_WIRE_12.PRESET
nhold_clk_wait => DFFE_intr_ff3.ENA
nhold_clk_wait => SYNTHESIZED_WIRE_10.ENA
nhold_clk_wait => SYNTHESIZED_WIRE_9.ENA
clrpc <= clrpc.DB_MAX_OUTPUT_PORT_TYPE
nreset <= SYNTHESIZED_WIRE_12.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|memory_ifc:memory_ifc_
clk => q2.CLK
clk => q1.CLK
clk => DFFE_mwr_ff1.CLK
clk => DFFE_mrd_ff1.CLK
clk => DFFE_m1_ff3.CLK
clk => SYNTHESIZED_WIRE_16.CLK
clk => SYNTHESIZED_WIRE_15.CLK
clk => DFFE_iorq_ff1.CLK
clk => DFFE_intr_ff3.CLK
clk => mwr_wr.CLK
clk => wait_mwr.CLK
clk => DFFE_mreq_ff2.CLK
clk => SYNTHESIZED_WIRE_17.CLK
clk => DFFE_mrd_ff3.CLK
clk => wait_mrd.CLK
clk => wait_m_ALTERA_SYNTHESIZED1.CLK
clk => DFFE_m1_ff1.CLK
clk => DFFE_iorq_ff4.CLK
clk => wait_iorq.CLK
clk => wait_iorqinta.CLK
nM1_int => SYNTHESIZED_WIRE_16.DATAIN
ctl_mRead => DFFE_mrd_ff1.DATAIN
ctl_mWrite => DFFE_mwr_ff1.DATAIN
in_intr => m1_mreq.IN1
nreset => nM1_out.IN1
nreset => wait_m_ALTERA_SYNTHESIZED1.ACLR
nreset => wait_iorqinta.ACLR
nreset => DFFE_intr_ff3.ACLR
nreset => DFFE_iorq_ff1.ACLR
nreset => SYNTHESIZED_WIRE_15.ACLR
nreset => wait_iorq.ACLR
nreset => DFFE_iorq_ff4.ACLR
nreset => SYNTHESIZED_WIRE_16.ACLR
nreset => DFFE_m1_ff1.PRESET
nreset => DFFE_m1_ff3.ACLR
nreset => DFFE_mrd_ff1.ACLR
nreset => wait_mrd.ACLR
nreset => DFFE_mrd_ff3.ACLR
nreset => SYNTHESIZED_WIRE_17.ACLR
nreset => DFFE_mreq_ff2.ACLR
nreset => DFFE_mwr_ff1.ACLR
nreset => q2.ACLR
nreset => wait_mwr.ACLR
nreset => mwr_wr.ACLR
nreset => q1.ACLR
fIORead => ioRead.IN1
fIOWrite => ioWrite.IN1
setM1 => DFFE_m1_ff1.DATAIN
ctl_iorw => DFFE_iorq_ff1.DATAIN
timings_en => DFFE_iorq_ff1.ENA
timings_en => SYNTHESIZED_WIRE_15.ENA
timings_en => wait_iorq.ENA
timings_en => DFFE_iorq_ff4.ENA
timings_en => SYNTHESIZED_WIRE_16.ENA
timings_en => DFFE_m1_ff1.ENA
timings_en => wait_m_ALTERA_SYNTHESIZED1.ENA
timings_en => DFFE_m1_ff3.ENA
timings_en => DFFE_mrd_ff1.ENA
timings_en => wait_mrd.ENA
timings_en => DFFE_mrd_ff3.ENA
timings_en => SYNTHESIZED_WIRE_17.ENA
timings_en => DFFE_mreq_ff2.ENA
timings_en => DFFE_mwr_ff1.ENA
timings_en => q2.ENA
timings_en => wait_mwr.ENA
timings_en => mwr_wr.ENA
timings_en => q1.ENA
iorq_Tw => wait_iorqinta.DATAIN
nhold_clk_wait => DFFE_intr_ff3.ENA
nM1_out <= nM1_out.DB_MAX_OUTPUT_PORT_TYPE
nRFSH_out <= nRFSH_out.DB_MAX_OUTPUT_PORT_TYPE
nMREQ_out <= nMREQ_out.DB_MAX_OUTPUT_PORT_TYPE
nRD_out <= nRD_out.DB_MAX_OUTPUT_PORT_TYPE
nWR_out <= nWR_out.DB_MAX_OUTPUT_PORT_TYPE
nIORQ_out <= nIORQ_out.DB_MAX_OUTPUT_PORT_TYPE
latch_wait <= latch_wait.DB_MAX_OUTPUT_PORT_TYPE
wait_m1 <= wait_m_ALTERA_SYNTHESIZED1.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|sequencer:sequencer_
clk => T6~reg0.CLK
clk => DFFE_T5_ff.CLK
clk => DFFE_T4_ff.CLK
clk => DFFE_T3_ff.CLK
clk => DFFE_T2_ff.CLK
clk => DFFE_T1_ff.CLK
clk => M5~reg0.CLK
clk => DFFE_M4_ff.CLK
clk => DFFE_M3_ff.CLK
clk => DFFE_M2_ff.CLK
clk => DFFE_M1_ff.CLK
nextM => ena_M.IN0
setM1 => ena_M.IN1
setM1 => SYNTHESIZED_WIRE_12.IN1
setM1 => SYNTHESIZED_WIRE_9.IN1
setM1 => SYNTHESIZED_WIRE_10.IN1
setM1 => SYNTHESIZED_WIRE_11.IN1
setM1 => DFFE_M1_ff.DATAIN
nreset => DFFE_M1_ff.PRESET
nreset => DFFE_M2_ff.ACLR
nreset => DFFE_M3_ff.ACLR
nreset => DFFE_M4_ff.ACLR
nreset => M5~reg0.ACLR
nreset => DFFE_T1_ff.PRESET
nreset => DFFE_T2_ff.ACLR
nreset => DFFE_T3_ff.ACLR
nreset => DFFE_T4_ff.ACLR
nreset => DFFE_T5_ff.ACLR
nreset => T6~reg0.ACLR
hold_clk_iorq => ena_T.IN0
hold_clk_wait => ena_T.IN1
hold_clk_busrq => ena_T.IN1
M1 <= DFFE_M1_ff.DB_MAX_OUTPUT_PORT_TYPE
M2 <= DFFE_M2_ff.DB_MAX_OUTPUT_PORT_TYPE
M3 <= DFFE_M3_ff.DB_MAX_OUTPUT_PORT_TYPE
M4 <= DFFE_M4_ff.DB_MAX_OUTPUT_PORT_TYPE
M5 <= M5~reg0.DB_MAX_OUTPUT_PORT_TYPE
T1 <= DFFE_T1_ff.DB_MAX_OUTPUT_PORT_TYPE
T2 <= DFFE_T2_ff.DB_MAX_OUTPUT_PORT_TYPE
T3 <= DFFE_T3_ff.DB_MAX_OUTPUT_PORT_TYPE
T4 <= DFFE_T4_ff.DB_MAX_OUTPUT_PORT_TYPE
T5 <= DFFE_T5_ff.DB_MAX_OUTPUT_PORT_TYPE
T6 <= T6~reg0.DB_MAX_OUTPUT_PORT_TYPE
timings_en <= ena_T.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|alu_control:alu_control_
alu_shift_db0 => alu_shift_db0.IN1
alu_shift_db7 => alu_shift_db7.IN2
ctl_shift_en => alu_shift_right.IN0
ctl_shift_en => alu_shift_left.IN0
alu_low_gt_9 => SYNTHESIZED_WIRE_9.IN0
alu_low_gt_9 => SYNTHESIZED_WIRE_8.IN0
alu_high_gt_9 => SYNTHESIZED_WIRE_21.IN0
alu_high_eq_9 => SYNTHESIZED_WIRE_8.IN1
ctl_daa_oe => SYNTHESIZED_WIRE_2.IN0
ctl_alu_op_low => alu_parity_in.IN1
ctl_alu_op_low => alu_op_low.DATAIN
ctl_alu_op_low => DFFE_latch_pf_tmp.ENA
alu_parity_out => alu_parity_out.IN1
flags_cf => flags_cf.IN1
flags_zf => flags_zf.IN1
flags_pf => flags_pf.IN1
flags_sf => flags_sf.IN1
ctl_cond_short => sel.IN0
alu_vf_out => alu_vf_out.IN1
iff2 => iff2.IN1
ctl_alu_core_hf => SYNTHESIZED_WIRE_16.IN0
ctl_alu_core_hf => SYNTHESIZED_WIRE_15.IN0
ctl_eval_cond => flags_cond_true~reg0.ENA
repeat_en => repeat_en.IN1
flags_cf_latch => flags_cf_latch.IN2
flags_hf2 => SYNTHESIZED_WIRE_9.IN1
flags_hf => SYNTHESIZED_WIRE_16.IN1
ctl_66_oe => SYNTHESIZED_WIRE_2.IN1
ctl_66_oe => SYNTHESIZED_WIRE_21.IN1
ctl_66_oe => out[2].IN1
clk => DFFE_latch_pf_tmp.CLK
clk => flags_cond_true~reg0.CLK
ctl_pf_sel[0] => ctl_pf_sel[0].IN1
ctl_pf_sel[1] => ctl_pf_sel[1].IN1
op543[0] => op543[0].IN1
op543[1] => sel[0].IN2
op543[2] => op543[2].IN1
alu_shift_in <= alu_mux_8:b2v_inst_shift_mux.out
alu_shift_right <= alu_shift_right.DB_MAX_OUTPUT_PORT_TYPE
alu_shift_left <= alu_shift_left.DB_MAX_OUTPUT_PORT_TYPE
shift_cf_out <= shift_cf_out.DB_MAX_OUTPUT_PORT_TYPE
alu_parity_in <= alu_parity_in.DB_MAX_OUTPUT_PORT_TYPE
flags_cond_true <= flags_cond_true~reg0.DB_MAX_OUTPUT_PORT_TYPE
daa_cf_out <= out[6].DB_MAX_OUTPUT_PORT_TYPE
pf_sel <= alu_mux_4:b2v_inst_pf_sel.out
alu_op_low <= ctl_alu_op_low.DB_MAX_OUTPUT_PORT_TYPE
alu_core_cf_in <= alu_core_cf_in.DB_MAX_OUTPUT_PORT_TYPE
db[0] <= db[0].DB_MAX_OUTPUT_PORT_TYPE
db[1] <= db[1].DB_MAX_OUTPUT_PORT_TYPE
db[2] <= db[2].DB_MAX_OUTPUT_PORT_TYPE
db[3] <= db[3].DB_MAX_OUTPUT_PORT_TYPE
db[4] <= db[4].DB_MAX_OUTPUT_PORT_TYPE
db[5] <= db[5].DB_MAX_OUTPUT_PORT_TYPE
db[6] <= db[6].DB_MAX_OUTPUT_PORT_TYPE
db[7] <= db[7].DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|alu_control:alu_control_|alu_mux_4:b2v_inst_cond_mux
in0 => SYNTHESIZED_WIRE_4.IN1
in1 => SYNTHESIZED_WIRE_7.IN1
in2 => SYNTHESIZED_WIRE_5.IN1
in3 => SYNTHESIZED_WIRE_6.IN1
sel[0] => SYNTHESIZED_WIRE_7.IN0
sel[0] => SYNTHESIZED_WIRE_6.IN0
sel[0] => SYNTHESIZED_WIRE_4.IN0
sel[0] => SYNTHESIZED_WIRE_5.IN0
sel[1] => SYNTHESIZED_WIRE_5.IN1
sel[1] => SYNTHESIZED_WIRE_6.IN1
sel[1] => SYNTHESIZED_WIRE_4.IN1
sel[1] => SYNTHESIZED_WIRE_7.IN1
out <= out.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|alu_control:alu_control_|alu_mux_4:b2v_inst_pf_sel
in0 => SYNTHESIZED_WIRE_4.IN1
in1 => SYNTHESIZED_WIRE_7.IN1
in2 => SYNTHESIZED_WIRE_5.IN1
in3 => SYNTHESIZED_WIRE_6.IN1
sel[0] => SYNTHESIZED_WIRE_7.IN0
sel[0] => SYNTHESIZED_WIRE_6.IN0
sel[0] => SYNTHESIZED_WIRE_4.IN0
sel[0] => SYNTHESIZED_WIRE_5.IN0
sel[1] => SYNTHESIZED_WIRE_5.IN1
sel[1] => SYNTHESIZED_WIRE_6.IN1
sel[1] => SYNTHESIZED_WIRE_4.IN1
sel[1] => SYNTHESIZED_WIRE_7.IN1
out <= out.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|alu_control:alu_control_|alu_mux_8:b2v_inst_shift_mux
in0 => SYNTHESIZED_WIRE_12.IN1
in1 => SYNTHESIZED_WIRE_14.IN1
in2 => SYNTHESIZED_WIRE_13.IN1
in3 => SYNTHESIZED_WIRE_15.IN1
in4 => SYNTHESIZED_WIRE_17.IN1
in5 => SYNTHESIZED_WIRE_16.IN1
in6 => SYNTHESIZED_WIRE_18.IN1
in7 => SYNTHESIZED_WIRE_19.IN1
sel[0] => SYNTHESIZED_WIRE_16.IN0
sel[0] => SYNTHESIZED_WIRE_19.IN0
sel[0] => SYNTHESIZED_WIRE_17.IN0
sel[0] => SYNTHESIZED_WIRE_18.IN0
sel[1] => SYNTHESIZED_WIRE_18.IN1
sel[1] => SYNTHESIZED_WIRE_19.IN1
sel[1] => SYNTHESIZED_WIRE_17.IN1
sel[1] => SYNTHESIZED_WIRE_16.IN1
sel[2] => SYNTHESIZED_WIRE_17.IN1
sel[2] => SYNTHESIZED_WIRE_16.IN1
sel[2] => SYNTHESIZED_WIRE_18.IN1
sel[2] => SYNTHESIZED_WIRE_19.IN1
sel[2] => SYNTHESIZED_WIRE_12.IN1
sel[2] => SYNTHESIZED_WIRE_14.IN1
sel[2] => SYNTHESIZED_WIRE_13.IN1
sel[2] => SYNTHESIZED_WIRE_15.IN1
out <= out.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|alu_select:alu_select_
ctl_alu_oe => alu_oe.DATAIN
ctl_alu_shift_oe => alu_shift_oe.DATAIN
ctl_alu_op2_oe => alu_op2_oe.DATAIN
ctl_alu_res_oe => alu_res_oe.DATAIN
ctl_alu_op1_oe => alu_op1_oe.DATAIN
ctl_alu_bs_oe => alu_bs_oe.DATAIN
ctl_alu_op1_sel_bus => alu_op1_sel_bus.DATAIN
ctl_alu_op1_sel_low => alu_op1_sel_low.DATAIN
ctl_alu_op1_sel_zero => alu_op1_sel_zero.DATAIN
ctl_alu_op2_sel_zero => alu_op2_sel_zero.DATAIN
ctl_alu_op2_sel_bus => alu_op2_sel_bus.DATAIN
ctl_alu_op2_sel_lq => alu_op2_sel_lq.DATAIN
ctl_alu_sel_op2_neg => alu_sel_op2_neg.DATAIN
ctl_alu_sel_op2_high => alu_sel_op2_high.DATAIN
ctl_alu_core_R => alu_core_R.DATAIN
ctl_alu_core_V => alu_core_V.DATAIN
ctl_alu_core_S => alu_core_S.DATAIN
alu_oe <= ctl_alu_oe.DB_MAX_OUTPUT_PORT_TYPE
alu_shift_oe <= ctl_alu_shift_oe.DB_MAX_OUTPUT_PORT_TYPE
alu_op2_oe <= ctl_alu_op2_oe.DB_MAX_OUTPUT_PORT_TYPE
alu_res_oe <= ctl_alu_res_oe.DB_MAX_OUTPUT_PORT_TYPE
alu_op1_oe <= ctl_alu_op1_oe.DB_MAX_OUTPUT_PORT_TYPE
alu_bs_oe <= ctl_alu_bs_oe.DB_MAX_OUTPUT_PORT_TYPE
alu_op1_sel_bus <= ctl_alu_op1_sel_bus.DB_MAX_OUTPUT_PORT_TYPE
alu_op1_sel_low <= ctl_alu_op1_sel_low.DB_MAX_OUTPUT_PORT_TYPE
alu_op1_sel_zero <= ctl_alu_op1_sel_zero.DB_MAX_OUTPUT_PORT_TYPE
alu_op2_sel_zero <= ctl_alu_op2_sel_zero.DB_MAX_OUTPUT_PORT_TYPE
alu_op2_sel_bus <= ctl_alu_op2_sel_bus.DB_MAX_OUTPUT_PORT_TYPE
alu_op2_sel_lq <= ctl_alu_op2_sel_lq.DB_MAX_OUTPUT_PORT_TYPE
alu_sel_op2_neg <= ctl_alu_sel_op2_neg.DB_MAX_OUTPUT_PORT_TYPE
alu_sel_op2_high <= ctl_alu_sel_op2_high.DB_MAX_OUTPUT_PORT_TYPE
alu_core_R <= ctl_alu_core_R.DB_MAX_OUTPUT_PORT_TYPE
alu_core_V <= ctl_alu_core_V.DB_MAX_OUTPUT_PORT_TYPE
alu_core_S <= ctl_alu_core_S.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|alu_flags:alu_flags_
ctl_flags_oe => db[0].OE
ctl_flags_oe => db[1].OE
ctl_flags_oe => db[2].OE
ctl_flags_oe => db[3].OE
ctl_flags_oe => db[4].OE
ctl_flags_oe => db[5].OE
ctl_flags_oe => db[6].OE
ctl_flags_oe => db[7].OE
ctl_flags_bus => SYNTHESIZED_WIRE_10.IN1
ctl_flags_bus => SYNTHESIZED_WIRE_20.IN1
ctl_flags_bus => SYNTHESIZED_WIRE_2.IN1
ctl_flags_bus => SYNTHESIZED_WIRE_22.IN1
ctl_flags_bus => SYNTHESIZED_WIRE_12.IN1
ctl_flags_bus => SYNTHESIZED_WIRE_14.IN1
ctl_flags_bus => SYNTHESIZED_WIRE_16.IN1
ctl_flags_bus => SYNTHESIZED_WIRE_18.IN1
ctl_flags_alu => SYNTHESIZED_WIRE_17.IN0
ctl_flags_alu => SYNTHESIZED_WIRE_19.IN0
ctl_flags_alu => SYNTHESIZED_WIRE_21.IN0
ctl_flags_alu => SYNTHESIZED_WIRE_1.IN0
ctl_flags_alu => SYNTHESIZED_WIRE_9.IN0
ctl_flags_alu => SYNTHESIZED_WIRE_11.IN0
ctl_flags_alu => SYNTHESIZED_WIRE_13.IN0
ctl_flags_alu => SYNTHESIZED_WIRE_15.IN0
alu_sf_out => SYNTHESIZED_WIRE_1.IN1
alu_sf_out => SYNTHESIZED_WIRE_9.IN1
alu_yf_out => SYNTHESIZED_WIRE_13.IN1
alu_xf_out => SYNTHESIZED_WIRE_17.IN1
ctl_flags_nf_set => SYNTHESIZED_WIRE_5.IN1
alu_zero => SYNTHESIZED_WIRE_11.IN1
shift_cf_out => shift_cf_out.IN1
alu_core_cf_out => alu_core_cf_out.IN1
daa_cf_out => daa_cf_out.IN1
ctl_flags_cf_set => SYNTHESIZED_WIRE_0.IN1
ctl_flags_cf_cpl => SYNTHESIZED_WIRE_24.IN1
pf_sel => SYNTHESIZED_WIRE_19.IN1
ctl_flags_cf_we => SYNTHESIZED_WIRE_27.IN0
ctl_flags_sz_we => DFFE_inst_latch_sf.ENA
ctl_flags_sz_we => SYNTHESIZED_WIRE_39.ENA
ctl_flags_xy_we => flags_xf.ENA
ctl_flags_xy_we => flags_yf.ENA
ctl_flags_hf_we => DFFE_inst_latch_hf.ENA
ctl_flags_pf_we => DFFE_inst_latch_pf.ENA
ctl_flags_nf_we => DFFE_inst_latch_nf.ENA
ctl_flags_cf2_we => SYNTHESIZED_WIRE_29.IN0
ctl_flags_cf2_we => SYNTHESIZED_WIRE_27.IN1
ctl_flags_hf_cpl => SYNTHESIZED_WIRE_23.IN1
ctl_flags_use_cf2 => ctl_flags_use_cf2.IN1
ctl_flags_hf2_we => flags_hf2~reg0.ENA
ctl_flags_nf_clr => SYNTHESIZED_WIRE_32.IN1
ctl_alu_zero_16bit => SYNTHESIZED_WIRE_4.IN1
clk => SYNTHESIZED_WIRE_39.CLK
clk => flags_yf.CLK
clk => flags_xf.CLK
clk => DFFE_inst_latch_sf.CLK
clk => DFFE_inst_latch_pf.CLK
clk => DFFE_inst_latch_nf.CLK
clk => flags_hf2~reg0.CLK
clk => DFFE_inst_latch_hf.CLK
clk => DFFE_inst_latch_cf2.CLK
clk => DFFE_inst_latch_cf.CLK
ctl_flags_cf2_sel_shift => sel[0].IN1
ctl_flags_cf2_sel_daa => sel[1].IN1
nhold_clk_wait => SYNTHESIZED_WIRE_27.IN1
nhold_clk_wait => SYNTHESIZED_WIRE_29.IN1
flags_sf <= DFFE_inst_latch_sf.DB_MAX_OUTPUT_PORT_TYPE
flags_zf <= SYNTHESIZED_WIRE_39.DB_MAX_OUTPUT_PORT_TYPE
flags_hf <= SYNTHESIZED_WIRE_23.DB_MAX_OUTPUT_PORT_TYPE
flags_pf <= DFFE_inst_latch_pf.DB_MAX_OUTPUT_PORT_TYPE
flags_cf <= SYNTHESIZED_WIRE_24.DB_MAX_OUTPUT_PORT_TYPE
flags_nf <= DFFE_inst_latch_nf.DB_MAX_OUTPUT_PORT_TYPE
flags_cf_latch <= DFFE_inst_latch_cf.DB_MAX_OUTPUT_PORT_TYPE
flags_hf2 <= flags_hf2~reg0.DB_MAX_OUTPUT_PORT_TYPE
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|alu_flags:alu_flags_|alu_mux_2:b2v_inst_mux_cf
sel1 => SYNTHESIZED_WIRE_1.IN0
sel1 => SYNTHESIZED_WIRE_2.IN0
in1 => SYNTHESIZED_WIRE_1.IN1
in0 => SYNTHESIZED_WIRE_2.IN1
out <= out.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|alu_flags:alu_flags_|alu_mux_4:b2v_inst_mux_cf2
in0 => SYNTHESIZED_WIRE_4.IN1
in1 => SYNTHESIZED_WIRE_7.IN1
in2 => SYNTHESIZED_WIRE_5.IN1
in3 => SYNTHESIZED_WIRE_6.IN1
sel[0] => SYNTHESIZED_WIRE_7.IN0
sel[0] => SYNTHESIZED_WIRE_6.IN0
sel[0] => SYNTHESIZED_WIRE_4.IN0
sel[0] => SYNTHESIZED_WIRE_5.IN0
sel[1] => SYNTHESIZED_WIRE_5.IN1
sel[1] => SYNTHESIZED_WIRE_6.IN1
sel[1] => SYNTHESIZED_WIRE_4.IN1
sel[1] => SYNTHESIZED_WIRE_7.IN1
out <= out.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|alu:alu_
alu_core_R => alu_core_R.IN1
alu_core_V => alu_core_V.IN1
alu_core_S => alu_core_S.IN1
alu_bs_oe => db_high[0].OE
alu_bs_oe => db_high[1].OE
alu_bs_oe => db_high[2].OE
alu_bs_oe => db_high[3].OE
alu_bs_oe => db_low[0].OE
alu_bs_oe => db_low[1].OE
alu_bs_oe => db_low[2].OE
alu_bs_oe => db_low[3].OE
alu_parity_in => SYNTHESIZED_WIRE_32.IN1
alu_oe => db[4].OE
alu_oe => db[5].OE
alu_oe => db[6].OE
alu_oe => db[7].OE
alu_oe => db[0].OE
alu_oe => db[1].OE
alu_oe => db[2].OE
alu_oe => db[3].OE
alu_shift_oe => db_high[0].OE
alu_shift_oe => db_high[1].OE
alu_shift_oe => db_high[2].OE
alu_shift_oe => db_high[3].OE
alu_shift_oe => db_low[0].OE
alu_shift_oe => db_low[1].OE
alu_shift_oe => db_low[2].OE
alu_shift_oe => db_low[3].OE
alu_core_cf_in => alu_core_cf_in.IN1
alu_op2_oe => db_high[0].OE
alu_op2_oe => db_high[1].OE
alu_op2_oe => db_high[2].OE
alu_op2_oe => db_high[3].OE
alu_op2_oe => db_low[0].OE
alu_op2_oe => db_low[1].OE
alu_op2_oe => db_low[2].OE
alu_op2_oe => db_low[3].OE
alu_op1_oe => db_high[0].OE
alu_op1_oe => db_high[1].OE
alu_op1_oe => db_high[2].OE
alu_op1_oe => db_high[3].OE
alu_op1_oe => db_low[0].OE
alu_op1_oe => db_low[1].OE
alu_op1_oe => db_low[2].OE
alu_op1_oe => db_low[3].OE
alu_res_oe => db_high[0].OE
alu_res_oe => db_high[1].OE
alu_res_oe => db_high[2].OE
alu_res_oe => db_high[3].OE
alu_res_oe => db_low[0].OE
alu_res_oe => db_low[1].OE
alu_res_oe => db_low[2].OE
alu_res_oe => db_low[3].OE
alu_op1_sel_low => alu_op1_sel_low.IN1
alu_op1_sel_zero => alu_op1_sel_zero.IN2
alu_op1_sel_bus => alu_op1_sel_bus.IN2
alu_op2_sel_zero => alu_op2_sel_zero.IN2
alu_op2_sel_bus => alu_op2_sel_bus.IN2
alu_op2_sel_lq => alu_op2_sel_lq.IN2
alu_op_low => SYNTHESIZED_WIRE_3[0].IN0
alu_op_low => SYNTHESIZED_WIRE_3[1].IN0
alu_op_low => SYNTHESIZED_WIRE_3[2].IN0
alu_op_low => SYNTHESIZED_WIRE_3[3].IN0
alu_op_low => SYNTHESIZED_WIRE_2[0].IN0
alu_op_low => SYNTHESIZED_WIRE_2[1].IN0
alu_op_low => SYNTHESIZED_WIRE_2[2].IN0
alu_op_low => SYNTHESIZED_WIRE_2[3].IN0
alu_op_low => result_lo[0].ENA
alu_op_low => result_lo[1].ENA
alu_op_low => result_lo[2].ENA
alu_op_low => result_lo[3].ENA
alu_shift_in => alu_shift_in.IN1
alu_sel_op2_neg => SYNTHESIZED_WIRE_11[0].IN1
alu_sel_op2_neg => SYNTHESIZED_WIRE_11[1].IN1
alu_sel_op2_neg => SYNTHESIZED_WIRE_11[2].IN1
alu_sel_op2_neg => SYNTHESIZED_WIRE_11[3].IN1
alu_sel_op2_neg => SYNTHESIZED_WIRE_13[0].IN1
alu_sel_op2_neg => SYNTHESIZED_WIRE_13[1].IN1
alu_sel_op2_neg => SYNTHESIZED_WIRE_13[2].IN1
alu_sel_op2_neg => SYNTHESIZED_WIRE_13[3].IN1
alu_sel_op2_neg => SYNTHESIZED_WIRE_12[0].IN1
alu_sel_op2_neg => SYNTHESIZED_WIRE_12[1].IN1
alu_sel_op2_neg => SYNTHESIZED_WIRE_12[2].IN1
alu_sel_op2_neg => SYNTHESIZED_WIRE_12[3].IN1
alu_sel_op2_neg => SYNTHESIZED_WIRE_14[0].IN1
alu_sel_op2_neg => SYNTHESIZED_WIRE_14[1].IN1
alu_sel_op2_neg => SYNTHESIZED_WIRE_14[2].IN1
alu_sel_op2_neg => SYNTHESIZED_WIRE_14[3].IN1
alu_sel_op2_high => SYNTHESIZED_WIRE_15[0].IN1
alu_sel_op2_high => SYNTHESIZED_WIRE_15[1].IN1
alu_sel_op2_high => SYNTHESIZED_WIRE_15[2].IN1
alu_sel_op2_high => SYNTHESIZED_WIRE_15[3].IN1
alu_sel_op2_high => SYNTHESIZED_WIRE_16[0].IN1
alu_sel_op2_high => SYNTHESIZED_WIRE_16[1].IN1
alu_sel_op2_high => SYNTHESIZED_WIRE_16[2].IN1
alu_sel_op2_high => SYNTHESIZED_WIRE_16[3].IN1
alu_shift_left => alu_shift_left.IN1
alu_shift_right => alu_shift_right.IN1
clk => result_lo[0].CLK
clk => result_lo[1].CLK
clk => result_lo[2].CLK
clk => result_lo[3].CLK
clk => op1_low[0].CLK
clk => op1_low[1].CLK
clk => op1_low[2].CLK
clk => op1_low[3].CLK
clk => op1_high[0].CLK
clk => op1_high[1].CLK
clk => op1_high[2].CLK
clk => op1_high[3].CLK
clk => op2_low[0].CLK
clk => op2_low[1].CLK
clk => op2_low[2].CLK
clk => op2_low[3].CLK
clk => op2_high[0].CLK
clk => op2_high[1].CLK
clk => op2_high[2].CLK
clk => op2_high[3].CLK
bsel[0] => bsel[0].IN1
bsel[1] => bsel[1].IN1
bsel[2] => bsel[2].IN1
alu_zero <= alu_zero.DB_MAX_OUTPUT_PORT_TYPE
alu_parity_out <= alu_parity_out.DB_MAX_OUTPUT_PORT_TYPE
alu_high_eq_9 <= alu_prep_daa:b2v_prep_daa.high_eq_9
alu_high_gt_9 <= alu_prep_daa:b2v_prep_daa.high_gt_9
alu_low_gt_9 <= alu_prep_daa:b2v_prep_daa.low_gt_9
alu_shift_db0 <= alu_shifter_core:b2v_input_shift.shift_db0
alu_shift_db7 <= alu_shifter_core:b2v_input_shift.shift_db7
alu_core_cf_out <= alu_core:b2v_core.cy_out
alu_sf_out <= db_high[3].DB_MAX_OUTPUT_PORT_TYPE
alu_yf_out <= db_high[1].DB_MAX_OUTPUT_PORT_TYPE
alu_xf_out <= db_low[3].DB_MAX_OUTPUT_PORT_TYPE
alu_vf_out <= alu_core:b2v_core.vf_out
db[0] <> alu_shifter_core:b2v_input_shift.db
db[0] <> db[0]
db[1] <> alu_shifter_core:b2v_input_shift.db
db[1] <> db[1]
db[2] <> alu_shifter_core:b2v_input_shift.db
db[2] <> db[2]
db[3] <> alu_shifter_core:b2v_input_shift.db
db[3] <> db[3]
db[4] <> alu_shifter_core:b2v_input_shift.db
db[4] <> db[4]
db[5] <> alu_shifter_core:b2v_input_shift.db
db[5] <> db[5]
db[6] <> alu_shifter_core:b2v_input_shift.db
db[6] <> db[6]
db[7] <> alu_shifter_core:b2v_input_shift.db
db[7] <> db[7]
test_db_high[0] <= db_high[0].DB_MAX_OUTPUT_PORT_TYPE
test_db_high[1] <= db_high[1].DB_MAX_OUTPUT_PORT_TYPE
test_db_high[2] <= db_high[2].DB_MAX_OUTPUT_PORT_TYPE
test_db_high[3] <= db_high[3].DB_MAX_OUTPUT_PORT_TYPE
test_db_low[0] <= db_low[0].DB_MAX_OUTPUT_PORT_TYPE
test_db_low[1] <= db_low[1].DB_MAX_OUTPUT_PORT_TYPE
test_db_low[2] <= db_low[2].DB_MAX_OUTPUT_PORT_TYPE
test_db_low[3] <= db_low[3].DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core
cy_in => cy_in.IN1
S => S.IN4
V => V.IN4
R => R.IN4
op1[0] => op1[0].IN1
op1[1] => op1[1].IN1
op1[2] => op1[2].IN1
op1[3] => op1[3].IN1
op2[0] => op2[0].IN1
op2[1] => op2[1].IN1
op2[2] => op2[2].IN1
op2[3] => op2[3].IN1
cy_out <= alu_slice:b2v_alu_slice_bit_3.cy_out
vf_out <= vf_out.DB_MAX_OUTPUT_PORT_TYPE
result[0] <= alu_slice:b2v_alu_slice_bit_0.result
result[1] <= alu_slice:b2v_alu_slice_bit_1.result
result[2] <= alu_slice:b2v_alu_slice_bit_2.result
result[3] <= alu_slice:b2v_alu_slice_bit_3.result


|spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_0
op2 => SYNTHESIZED_WIRE_0.IN0
op2 => SYNTHESIZED_WIRE_4.IN0
op2 => SYNTHESIZED_WIRE_5.IN0
op2 => SYNTHESIZED_WIRE_8.IN0
op1 => SYNTHESIZED_WIRE_0.IN1
op1 => SYNTHESIZED_WIRE_4.IN1
op1 => SYNTHESIZED_WIRE_5.IN1
op1 => SYNTHESIZED_WIRE_8.IN1
cy_in => SYNTHESIZED_WIRE_0.IN1
cy_in => SYNTHESIZED_WIRE_4.IN1
cy_in => SYNTHESIZED_WIRE_7.IN1
R => cy_out.IN1
S => SYNTHESIZED_WIRE_10.IN1
V => SYNTHESIZED_WIRE_1.IN1
cy_out <= cy_out.DB_MAX_OUTPUT_PORT_TYPE
result <= SYNTHESIZED_WIRE_2.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1
op2 => SYNTHESIZED_WIRE_0.IN0
op2 => SYNTHESIZED_WIRE_4.IN0
op2 => SYNTHESIZED_WIRE_5.IN0
op2 => SYNTHESIZED_WIRE_8.IN0
op1 => SYNTHESIZED_WIRE_0.IN1
op1 => SYNTHESIZED_WIRE_4.IN1
op1 => SYNTHESIZED_WIRE_5.IN1
op1 => SYNTHESIZED_WIRE_8.IN1
cy_in => SYNTHESIZED_WIRE_0.IN1
cy_in => SYNTHESIZED_WIRE_4.IN1
cy_in => SYNTHESIZED_WIRE_7.IN1
R => cy_out.IN1
S => SYNTHESIZED_WIRE_10.IN1
V => SYNTHESIZED_WIRE_1.IN1
cy_out <= cy_out.DB_MAX_OUTPUT_PORT_TYPE
result <= SYNTHESIZED_WIRE_2.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2
op2 => SYNTHESIZED_WIRE_0.IN0
op2 => SYNTHESIZED_WIRE_4.IN0
op2 => SYNTHESIZED_WIRE_5.IN0
op2 => SYNTHESIZED_WIRE_8.IN0
op1 => SYNTHESIZED_WIRE_0.IN1
op1 => SYNTHESIZED_WIRE_4.IN1
op1 => SYNTHESIZED_WIRE_5.IN1
op1 => SYNTHESIZED_WIRE_8.IN1
cy_in => SYNTHESIZED_WIRE_0.IN1
cy_in => SYNTHESIZED_WIRE_4.IN1
cy_in => SYNTHESIZED_WIRE_7.IN1
R => cy_out.IN1
S => SYNTHESIZED_WIRE_10.IN1
V => SYNTHESIZED_WIRE_1.IN1
cy_out <= cy_out.DB_MAX_OUTPUT_PORT_TYPE
result <= SYNTHESIZED_WIRE_2.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3
op2 => SYNTHESIZED_WIRE_0.IN0
op2 => SYNTHESIZED_WIRE_4.IN0
op2 => SYNTHESIZED_WIRE_5.IN0
op2 => SYNTHESIZED_WIRE_8.IN0
op1 => SYNTHESIZED_WIRE_0.IN1
op1 => SYNTHESIZED_WIRE_4.IN1
op1 => SYNTHESIZED_WIRE_5.IN1
op1 => SYNTHESIZED_WIRE_8.IN1
cy_in => SYNTHESIZED_WIRE_0.IN1
cy_in => SYNTHESIZED_WIRE_4.IN1
cy_in => SYNTHESIZED_WIRE_7.IN1
R => cy_out.IN1
S => SYNTHESIZED_WIRE_10.IN1
V => SYNTHESIZED_WIRE_1.IN1
cy_out <= cy_out.DB_MAX_OUTPUT_PORT_TYPE
result <= SYNTHESIZED_WIRE_2.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|alu:alu_|alu_bit_select:b2v_input_bit_select
bsel[0] => bs_out_high_ALTERA_SYNTHESIZED.IN0
bsel[0] => bs_out_high_ALTERA_SYNTHESIZED.IN0
bsel[0] => bs_out_high_ALTERA_SYNTHESIZED.IN0
bsel[0] => bs_out_high_ALTERA_SYNTHESIZED.IN0
bsel[1] => bs_out_high_ALTERA_SYNTHESIZED.IN1
bsel[1] => bs_out_high_ALTERA_SYNTHESIZED.IN1
bsel[1] => bs_out_high_ALTERA_SYNTHESIZED.IN1
bsel[1] => bs_out_high_ALTERA_SYNTHESIZED.IN1
bsel[2] => bs_out_high_ALTERA_SYNTHESIZED.IN1
bsel[2] => bs_out_high_ALTERA_SYNTHESIZED.IN1
bsel[2] => bs_out_high_ALTERA_SYNTHESIZED.IN1
bsel[2] => bs_out_high_ALTERA_SYNTHESIZED.IN1
bsel[2] => bs_out_low_ALTERA_SYNTHESIZED.IN1
bsel[2] => bs_out_low_ALTERA_SYNTHESIZED.IN1
bsel[2] => bs_out_low_ALTERA_SYNTHESIZED.IN1
bsel[2] => bs_out_low_ALTERA_SYNTHESIZED.IN1
bs_out_high[0] <= bs_out_high_ALTERA_SYNTHESIZED.DB_MAX_OUTPUT_PORT_TYPE
bs_out_high[1] <= bs_out_high_ALTERA_SYNTHESIZED.DB_MAX_OUTPUT_PORT_TYPE
bs_out_high[2] <= bs_out_high_ALTERA_SYNTHESIZED.DB_MAX_OUTPUT_PORT_TYPE
bs_out_high[3] <= bs_out_high_ALTERA_SYNTHESIZED.DB_MAX_OUTPUT_PORT_TYPE
bs_out_low[0] <= bs_out_low_ALTERA_SYNTHESIZED.DB_MAX_OUTPUT_PORT_TYPE
bs_out_low[1] <= bs_out_low_ALTERA_SYNTHESIZED.DB_MAX_OUTPUT_PORT_TYPE
bs_out_low[2] <= bs_out_low_ALTERA_SYNTHESIZED.DB_MAX_OUTPUT_PORT_TYPE
bs_out_low[3] <= bs_out_low_ALTERA_SYNTHESIZED.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|alu:alu_|alu_shifter_core:b2v_input_shift
shift_in => SYNTHESIZED_WIRE_9.IN0
shift_in => SYNTHESIZED_WIRE_31.IN0
shift_right => SYNTHESIZED_WIRE_10.IN0
shift_right => SYNTHESIZED_WIRE_13.IN0
shift_right => SYNTHESIZED_WIRE_16.IN0
shift_right => SYNTHESIZED_WIRE_19.IN0
shift_right => SYNTHESIZED_WIRE_22.IN0
shift_right => SYNTHESIZED_WIRE_25.IN0
shift_right => SYNTHESIZED_WIRE_28.IN0
shift_right => SYNTHESIZED_WIRE_31.IN1
shift_right => SYNTHESIZED_WIRE_32.IN0
shift_left => SYNTHESIZED_WIRE_9.IN1
shift_left => SYNTHESIZED_WIRE_12.IN0
shift_left => SYNTHESIZED_WIRE_15.IN0
shift_left => SYNTHESIZED_WIRE_18.IN0
shift_left => SYNTHESIZED_WIRE_21.IN0
shift_left => SYNTHESIZED_WIRE_24.IN0
shift_left => SYNTHESIZED_WIRE_27.IN0
shift_left => SYNTHESIZED_WIRE_30.IN0
shift_left => SYNTHESIZED_WIRE_32.IN1
db[0] => SYNTHESIZED_WIRE_8.IN1
db[0] => SYNTHESIZED_WIRE_12.IN1
db[0] => shift_db0.DATAIN
db[1] => SYNTHESIZED_WIRE_10.IN1
db[1] => SYNTHESIZED_WIRE_11.IN1
db[1] => SYNTHESIZED_WIRE_15.IN1
db[2] => SYNTHESIZED_WIRE_13.IN1
db[2] => SYNTHESIZED_WIRE_14.IN1
db[2] => SYNTHESIZED_WIRE_18.IN1
db[3] => SYNTHESIZED_WIRE_16.IN1
db[3] => SYNTHESIZED_WIRE_17.IN1
db[3] => SYNTHESIZED_WIRE_21.IN1
db[4] => SYNTHESIZED_WIRE_19.IN1
db[4] => SYNTHESIZED_WIRE_20.IN1
db[4] => SYNTHESIZED_WIRE_24.IN1
db[5] => SYNTHESIZED_WIRE_22.IN1
db[5] => SYNTHESIZED_WIRE_23.IN1
db[5] => SYNTHESIZED_WIRE_27.IN1
db[6] => SYNTHESIZED_WIRE_25.IN1
db[6] => SYNTHESIZED_WIRE_26.IN1
db[6] => SYNTHESIZED_WIRE_30.IN1
db[7] => SYNTHESIZED_WIRE_28.IN1
db[7] => SYNTHESIZED_WIRE_29.IN1
db[7] => shift_db7.DATAIN
shift_db0 <= db[0].DB_MAX_OUTPUT_PORT_TYPE
shift_db7 <= db[7].DB_MAX_OUTPUT_PORT_TYPE
out_high[0] <= out_high_ALTERA_SYNTHESIZED.DB_MAX_OUTPUT_PORT_TYPE
out_high[1] <= out_high_ALTERA_SYNTHESIZED.DB_MAX_OUTPUT_PORT_TYPE
out_high[2] <= out_high_ALTERA_SYNTHESIZED.DB_MAX_OUTPUT_PORT_TYPE
out_high[3] <= out_high_ALTERA_SYNTHESIZED.DB_MAX_OUTPUT_PORT_TYPE
out_low[0] <= out_low_ALTERA_SYNTHESIZED.DB_MAX_OUTPUT_PORT_TYPE
out_low[1] <= out_low_ALTERA_SYNTHESIZED.DB_MAX_OUTPUT_PORT_TYPE
out_low[2] <= out_low_ALTERA_SYNTHESIZED.DB_MAX_OUTPUT_PORT_TYPE
out_low[3] <= out_low_ALTERA_SYNTHESIZED.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|alu:alu_|alu_mux_2z:b2v_op1_latch_mux_high
sel_a => SYNTHESIZED_WIRE_0[0].IN0
sel_a => SYNTHESIZED_WIRE_0[1].IN0
sel_a => SYNTHESIZED_WIRE_0[2].IN0
sel_a => SYNTHESIZED_WIRE_0[3].IN0
sel_a => ena.IN0
sel_zero => ena.IN1
sel_zero => Q.IN1
sel_zero => Q.IN1
sel_zero => Q.IN1
sel_zero => Q.IN1
a[0] => SYNTHESIZED_WIRE_0[0].IN1
a[1] => SYNTHESIZED_WIRE_0[1].IN1
a[2] => SYNTHESIZED_WIRE_0[2].IN1
a[3] => SYNTHESIZED_WIRE_0[3].IN1
ena <= ena.DB_MAX_OUTPUT_PORT_TYPE
Q[0] <= Q.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= Q.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= Q.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= Q.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op1_latch_mux_low
sel_zero => ena.IN1
sel_zero => Q.IN1
sel_zero => Q.IN1
sel_zero => Q.IN1
sel_zero => Q.IN1
sel_a => SYNTHESIZED_WIRE_3[0].IN0
sel_a => SYNTHESIZED_WIRE_3[1].IN0
sel_a => SYNTHESIZED_WIRE_3[2].IN0
sel_a => SYNTHESIZED_WIRE_3[3].IN0
sel_a => ena.IN0
sel_b => ena.IN1
sel_b => SYNTHESIZED_WIRE_2[0].IN0
sel_b => SYNTHESIZED_WIRE_2[1].IN0
sel_b => SYNTHESIZED_WIRE_2[2].IN0
sel_b => SYNTHESIZED_WIRE_2[3].IN0
a[0] => SYNTHESIZED_WIRE_3[0].IN1
a[1] => SYNTHESIZED_WIRE_3[1].IN1
a[2] => SYNTHESIZED_WIRE_3[2].IN1
a[3] => SYNTHESIZED_WIRE_3[3].IN1
b[0] => SYNTHESIZED_WIRE_2[0].IN1
b[1] => SYNTHESIZED_WIRE_2[1].IN1
b[2] => SYNTHESIZED_WIRE_2[2].IN1
b[3] => SYNTHESIZED_WIRE_2[3].IN1
ena <= ena.DB_MAX_OUTPUT_PORT_TYPE
Q[0] <= Q.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= Q.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= Q.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= Q.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op2_latch_mux_high
sel_zero => ena.IN1
sel_zero => Q.IN1
sel_zero => Q.IN1
sel_zero => Q.IN1
sel_zero => Q.IN1
sel_a => SYNTHESIZED_WIRE_3[0].IN0
sel_a => SYNTHESIZED_WIRE_3[1].IN0
sel_a => SYNTHESIZED_WIRE_3[2].IN0
sel_a => SYNTHESIZED_WIRE_3[3].IN0
sel_a => ena.IN0
sel_b => ena.IN1
sel_b => SYNTHESIZED_WIRE_2[0].IN0
sel_b => SYNTHESIZED_WIRE_2[1].IN0
sel_b => SYNTHESIZED_WIRE_2[2].IN0
sel_b => SYNTHESIZED_WIRE_2[3].IN0
a[0] => SYNTHESIZED_WIRE_3[0].IN1
a[1] => SYNTHESIZED_WIRE_3[1].IN1
a[2] => SYNTHESIZED_WIRE_3[2].IN1
a[3] => SYNTHESIZED_WIRE_3[3].IN1
b[0] => SYNTHESIZED_WIRE_2[0].IN1
b[1] => SYNTHESIZED_WIRE_2[1].IN1
b[2] => SYNTHESIZED_WIRE_2[2].IN1
b[3] => SYNTHESIZED_WIRE_2[3].IN1
ena <= ena.DB_MAX_OUTPUT_PORT_TYPE
Q[0] <= Q.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= Q.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= Q.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= Q.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op2_latch_mux_low
sel_zero => ena.IN1
sel_zero => Q.IN1
sel_zero => Q.IN1
sel_zero => Q.IN1
sel_zero => Q.IN1
sel_a => SYNTHESIZED_WIRE_3[0].IN0
sel_a => SYNTHESIZED_WIRE_3[1].IN0
sel_a => SYNTHESIZED_WIRE_3[2].IN0
sel_a => SYNTHESIZED_WIRE_3[3].IN0
sel_a => ena.IN0
sel_b => ena.IN1
sel_b => SYNTHESIZED_WIRE_2[0].IN0
sel_b => SYNTHESIZED_WIRE_2[1].IN0
sel_b => SYNTHESIZED_WIRE_2[2].IN0
sel_b => SYNTHESIZED_WIRE_2[3].IN0
a[0] => SYNTHESIZED_WIRE_3[0].IN1
a[1] => SYNTHESIZED_WIRE_3[1].IN1
a[2] => SYNTHESIZED_WIRE_3[2].IN1
a[3] => SYNTHESIZED_WIRE_3[3].IN1
b[0] => SYNTHESIZED_WIRE_2[0].IN1
b[1] => SYNTHESIZED_WIRE_2[1].IN1
b[2] => SYNTHESIZED_WIRE_2[2].IN1
b[3] => SYNTHESIZED_WIRE_2[3].IN1
ena <= ena.DB_MAX_OUTPUT_PORT_TYPE
Q[0] <= Q.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= Q.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= Q.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= Q.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|alu:alu_|alu_prep_daa:b2v_prep_daa
high[0] => high_eq_9.IN0
high[1] => SYNTHESIZED_WIRE_2.IN0
high[1] => high_eq_9.IN1
high[2] => SYNTHESIZED_WIRE_3.IN0
high[2] => high_eq_9.IN1
high[3] => SYNTHESIZED_WIRE_3.IN1
high[3] => SYNTHESIZED_WIRE_2.IN1
high[3] => high_eq_9.IN1
low[0] => ~NO_FANOUT~
low[1] => SYNTHESIZED_WIRE_0.IN0
low[2] => SYNTHESIZED_WIRE_1.IN0
low[3] => SYNTHESIZED_WIRE_1.IN1
low[3] => SYNTHESIZED_WIRE_0.IN1
low_gt_9 <= low_gt_9.DB_MAX_OUTPUT_PORT_TYPE
high_eq_9 <= high_eq_9.DB_MAX_OUTPUT_PORT_TYPE
high_gt_9 <= high_gt_9.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|reg_file:reg_file_
reg_sel_sys_lo => SYNTHESIZED_WIRE_82.IN0
reg_sel_sys_lo => SYNTHESIZED_WIRE_74.IN0
reg_sel_sys_lo => SYNTHESIZED_WIRE_63.IN0
reg_sel_sys_lo => SYNTHESIZED_WIRE_75.IN0
reg_sel_sys_lo => SYNTHESIZED_WIRE_83.IN0
reg_sel_sys_lo => SYNTHESIZED_WIRE_62.IN0
reg_sel_gp_lo => SYNTHESIZED_WIRE_78.IN0
reg_sel_gp_lo => SYNTHESIZED_WIRE_71.IN0
reg_sel_gp_lo => SYNTHESIZED_WIRE_67.IN0
reg_sel_gp_lo => SYNTHESIZED_WIRE_55.IN0
reg_sel_gp_lo => SYNTHESIZED_WIRE_59.IN0
reg_sel_gp_lo => SYNTHESIZED_WIRE_47.IN0
reg_sel_gp_lo => SYNTHESIZED_WIRE_51.IN0
reg_sel_gp_lo => SYNTHESIZED_WIRE_70.IN0
reg_sel_gp_lo => SYNTHESIZED_WIRE_39.IN0
reg_sel_gp_lo => SYNTHESIZED_WIRE_43.IN0
reg_sel_gp_lo => SYNTHESIZED_WIRE_31.IN0
reg_sel_gp_lo => SYNTHESIZED_WIRE_66.IN0
reg_sel_gp_lo => SYNTHESIZED_WIRE_35.IN0
reg_sel_gp_lo => SYNTHESIZED_WIRE_54.IN0
reg_sel_gp_lo => SYNTHESIZED_WIRE_58.IN0
reg_sel_gp_lo => SYNTHESIZED_WIRE_46.IN0
reg_sel_gp_lo => SYNTHESIZED_WIRE_50.IN0
reg_sel_gp_lo => SYNTHESIZED_WIRE_38.IN0
reg_sel_gp_lo => SYNTHESIZED_WIRE_42.IN0
reg_sel_gp_lo => SYNTHESIZED_WIRE_30.IN0
reg_sel_gp_lo => SYNTHESIZED_WIRE_34.IN0
reg_sel_gp_lo => SYNTHESIZED_WIRE_79.IN0
reg_sel_sys_hi => SYNTHESIZED_WIRE_80.IN0
reg_sel_sys_hi => SYNTHESIZED_WIRE_72.IN0
reg_sel_sys_hi => SYNTHESIZED_WIRE_81.IN1
reg_sel_sys_hi => SYNTHESIZED_WIRE_61.IN1
reg_sel_sys_hi => SYNTHESIZED_WIRE_73.IN1
reg_sel_sys_hi => SYNTHESIZED_WIRE_60.IN0
reg_sel_gp_hi => SYNTHESIZED_WIRE_76.IN0
reg_sel_gp_hi => SYNTHESIZED_WIRE_68.IN0
reg_sel_gp_hi => SYNTHESIZED_WIRE_77.IN1
reg_sel_gp_hi => SYNTHESIZED_WIRE_64.IN0
reg_sel_gp_hi => SYNTHESIZED_WIRE_69.IN1
reg_sel_gp_hi => SYNTHESIZED_WIRE_65.IN1
reg_sel_gp_hi => SYNTHESIZED_WIRE_53.IN1
reg_sel_gp_hi => SYNTHESIZED_WIRE_52.IN0
reg_sel_gp_hi => SYNTHESIZED_WIRE_57.IN1
reg_sel_gp_hi => SYNTHESIZED_WIRE_45.IN1
reg_sel_gp_hi => SYNTHESIZED_WIRE_49.IN1
reg_sel_gp_hi => SYNTHESIZED_WIRE_37.IN1
reg_sel_gp_hi => SYNTHESIZED_WIRE_56.IN0
reg_sel_gp_hi => SYNTHESIZED_WIRE_41.IN1
reg_sel_gp_hi => SYNTHESIZED_WIRE_29.IN1
reg_sel_gp_hi => SYNTHESIZED_WIRE_33.IN1
reg_sel_gp_hi => SYNTHESIZED_WIRE_44.IN0
reg_sel_gp_hi => SYNTHESIZED_WIRE_48.IN0
reg_sel_gp_hi => SYNTHESIZED_WIRE_36.IN0
reg_sel_gp_hi => SYNTHESIZED_WIRE_40.IN0
reg_sel_gp_hi => SYNTHESIZED_WIRE_28.IN0
reg_sel_gp_hi => SYNTHESIZED_WIRE_32.IN0
reg_sel_ir => SYNTHESIZED_WIRE_63.IN1
reg_sel_ir => SYNTHESIZED_WIRE_61.IN0
reg_sel_ir => SYNTHESIZED_WIRE_62.IN1
reg_sel_ir => SYNTHESIZED_WIRE_60.IN1
reg_sel_pc => SYNTHESIZED_WIRE_74.IN1
reg_sel_pc => SYNTHESIZED_WIRE_72.IN1
reg_sel_pc => SYNTHESIZED_WIRE_75.IN1
reg_sel_pc => SYNTHESIZED_WIRE_73.IN0
ctl_sw_4u => gdfx_temp1[0].OE
ctl_sw_4u => gdfx_temp1[1].OE
ctl_sw_4u => gdfx_temp1[2].OE
ctl_sw_4u => gdfx_temp1[3].OE
ctl_sw_4u => gdfx_temp1[4].OE
ctl_sw_4u => gdfx_temp1[5].OE
ctl_sw_4u => gdfx_temp1[6].OE
ctl_sw_4u => gdfx_temp1[7].OE
ctl_sw_4u => gdfx_temp0[0].OE
ctl_sw_4u => gdfx_temp0[1].OE
ctl_sw_4u => gdfx_temp0[2].OE
ctl_sw_4u => gdfx_temp0[3].OE
ctl_sw_4u => gdfx_temp0[4].OE
ctl_sw_4u => gdfx_temp0[5].OE
ctl_sw_4u => gdfx_temp0[6].OE
ctl_sw_4u => gdfx_temp0[7].OE
reg_sel_wz => SYNTHESIZED_WIRE_82.IN1
reg_sel_wz => SYNTHESIZED_WIRE_80.IN1
reg_sel_wz => SYNTHESIZED_WIRE_81.IN0
reg_sel_wz => SYNTHESIZED_WIRE_83.IN1
reg_sel_sp => SYNTHESIZED_WIRE_78.IN1
reg_sel_sp => SYNTHESIZED_WIRE_76.IN1
reg_sel_sp => SYNTHESIZED_WIRE_77.IN0
reg_sel_sp => SYNTHESIZED_WIRE_79.IN1
reg_sel_iy => SYNTHESIZED_WIRE_71.IN1
reg_sel_iy => SYNTHESIZED_WIRE_70.IN1
reg_sel_iy => SYNTHESIZED_WIRE_68.IN1
reg_sel_iy => SYNTHESIZED_WIRE_69.IN0
reg_sel_ix => SYNTHESIZED_WIRE_67.IN1
reg_sel_ix => SYNTHESIZED_WIRE_66.IN1
reg_sel_ix => SYNTHESIZED_WIRE_64.IN1
reg_sel_ix => SYNTHESIZED_WIRE_65.IN0
reg_sel_hl2 => SYNTHESIZED_WIRE_55.IN1
reg_sel_hl2 => SYNTHESIZED_WIRE_53.IN0
reg_sel_hl2 => SYNTHESIZED_WIRE_54.IN1
reg_sel_hl2 => SYNTHESIZED_WIRE_52.IN1
reg_sel_hl => SYNTHESIZED_WIRE_59.IN1
reg_sel_hl => SYNTHESIZED_WIRE_57.IN0
reg_sel_hl => SYNTHESIZED_WIRE_58.IN1
reg_sel_hl => SYNTHESIZED_WIRE_56.IN1
reg_sel_de2 => SYNTHESIZED_WIRE_47.IN1
reg_sel_de2 => SYNTHESIZED_WIRE_45.IN0
reg_sel_de2 => SYNTHESIZED_WIRE_46.IN1
reg_sel_de2 => SYNTHESIZED_WIRE_44.IN1
reg_sel_de => SYNTHESIZED_WIRE_51.IN1
reg_sel_de => SYNTHESIZED_WIRE_49.IN0
reg_sel_de => SYNTHESIZED_WIRE_50.IN1
reg_sel_de => SYNTHESIZED_WIRE_48.IN1
reg_sel_bc2 => SYNTHESIZED_WIRE_39.IN1
reg_sel_bc2 => SYNTHESIZED_WIRE_37.IN0
reg_sel_bc2 => SYNTHESIZED_WIRE_38.IN1
reg_sel_bc2 => SYNTHESIZED_WIRE_36.IN1
reg_sel_bc => SYNTHESIZED_WIRE_43.IN1
reg_sel_bc => SYNTHESIZED_WIRE_41.IN0
reg_sel_bc => SYNTHESIZED_WIRE_42.IN1
reg_sel_bc => SYNTHESIZED_WIRE_40.IN1
reg_sel_af2 => SYNTHESIZED_WIRE_31.IN1
reg_sel_af2 => SYNTHESIZED_WIRE_29.IN0
reg_sel_af2 => SYNTHESIZED_WIRE_30.IN1
reg_sel_af2 => SYNTHESIZED_WIRE_28.IN1
reg_sel_af => SYNTHESIZED_WIRE_35.IN1
reg_sel_af => SYNTHESIZED_WIRE_33.IN0
reg_sel_af => SYNTHESIZED_WIRE_34.IN1
reg_sel_af => SYNTHESIZED_WIRE_32.IN1
reg_gp_we => SYNTHESIZED_WIRE_71.IN1
reg_gp_we => SYNTHESIZED_WIRE_67.IN1
reg_gp_we => SYNTHESIZED_WIRE_55.IN1
reg_gp_we => SYNTHESIZED_WIRE_59.IN1
reg_gp_we => SYNTHESIZED_WIRE_47.IN1
reg_gp_we => SYNTHESIZED_WIRE_51.IN1
reg_gp_we => SYNTHESIZED_WIRE_39.IN1
reg_gp_we => SYNTHESIZED_WIRE_43.IN1
reg_gp_we => SYNTHESIZED_WIRE_31.IN1
reg_gp_we => SYNTHESIZED_WIRE_77.IN1
reg_gp_we => SYNTHESIZED_WIRE_35.IN1
reg_gp_we => SYNTHESIZED_WIRE_69.IN1
reg_gp_we => SYNTHESIZED_WIRE_65.IN1
reg_gp_we => SYNTHESIZED_WIRE_53.IN1
reg_gp_we => SYNTHESIZED_WIRE_57.IN1
reg_gp_we => SYNTHESIZED_WIRE_45.IN1
reg_gp_we => SYNTHESIZED_WIRE_49.IN1
reg_gp_we => SYNTHESIZED_WIRE_37.IN1
reg_gp_we => SYNTHESIZED_WIRE_41.IN1
reg_gp_we => SYNTHESIZED_WIRE_29.IN1
reg_gp_we => SYNTHESIZED_WIRE_33.IN1
reg_gp_we => SYNTHESIZED_WIRE_79.IN1
reg_gp_we => SYNTHESIZED_WIRE_78.IN1
reg_gp_we => SYNTHESIZED_WIRE_76.IN1
reg_gp_we => SYNTHESIZED_WIRE_70.IN1
reg_gp_we => SYNTHESIZED_WIRE_68.IN1
reg_gp_we => SYNTHESIZED_WIRE_66.IN1
reg_gp_we => SYNTHESIZED_WIRE_64.IN1
reg_gp_we => SYNTHESIZED_WIRE_54.IN1
reg_gp_we => SYNTHESIZED_WIRE_52.IN1
reg_gp_we => SYNTHESIZED_WIRE_58.IN1
reg_gp_we => SYNTHESIZED_WIRE_56.IN1
reg_gp_we => SYNTHESIZED_WIRE_46.IN1
reg_gp_we => SYNTHESIZED_WIRE_44.IN1
reg_gp_we => SYNTHESIZED_WIRE_50.IN1
reg_gp_we => SYNTHESIZED_WIRE_48.IN1
reg_gp_we => SYNTHESIZED_WIRE_38.IN1
reg_gp_we => SYNTHESIZED_WIRE_36.IN1
reg_gp_we => SYNTHESIZED_WIRE_42.IN1
reg_gp_we => SYNTHESIZED_WIRE_40.IN1
reg_gp_we => SYNTHESIZED_WIRE_30.IN1
reg_gp_we => SYNTHESIZED_WIRE_28.IN1
reg_gp_we => SYNTHESIZED_WIRE_34.IN1
reg_gp_we => SYNTHESIZED_WIRE_32.IN1
reg_sys_we_lo => SYNTHESIZED_WIRE_63.IN1
reg_sys_we_lo => SYNTHESIZED_WIRE_75.IN1
reg_sys_we_lo => SYNTHESIZED_WIRE_83.IN1
reg_sys_we_lo => SYNTHESIZED_WIRE_82.IN1
reg_sys_we_lo => SYNTHESIZED_WIRE_74.IN1
reg_sys_we_lo => SYNTHESIZED_WIRE_62.IN1
reg_sys_we_hi => SYNTHESIZED_WIRE_81.IN1
reg_sys_we_hi => SYNTHESIZED_WIRE_61.IN1
reg_sys_we_hi => SYNTHESIZED_WIRE_73.IN1
reg_sys_we_hi => SYNTHESIZED_WIRE_80.IN1
reg_sys_we_hi => SYNTHESIZED_WIRE_72.IN1
reg_sys_we_hi => SYNTHESIZED_WIRE_60.IN1
ctl_reg_in_hi => gdfx_temp1[0].OE
ctl_reg_in_hi => gdfx_temp1[1].OE
ctl_reg_in_hi => gdfx_temp1[2].OE
ctl_reg_in_hi => gdfx_temp1[3].OE
ctl_reg_in_hi => gdfx_temp1[4].OE
ctl_reg_in_hi => gdfx_temp1[5].OE
ctl_reg_in_hi => gdfx_temp1[6].OE
ctl_reg_in_hi => gdfx_temp1[7].OE
ctl_reg_in_lo => gdfx_temp0[0].OE
ctl_reg_in_lo => gdfx_temp0[1].OE
ctl_reg_in_lo => gdfx_temp0[2].OE
ctl_reg_in_lo => gdfx_temp0[3].OE
ctl_reg_in_lo => gdfx_temp0[4].OE
ctl_reg_in_lo => gdfx_temp0[5].OE
ctl_reg_in_lo => gdfx_temp0[6].OE
ctl_reg_in_lo => gdfx_temp0[7].OE
ctl_reg_out_lo => db_lo_ds[0].OE
ctl_reg_out_lo => db_lo_ds[1].OE
ctl_reg_out_lo => db_lo_ds[2].OE
ctl_reg_out_lo => db_lo_ds[3].OE
ctl_reg_out_lo => db_lo_ds[4].OE
ctl_reg_out_lo => db_lo_ds[5].OE
ctl_reg_out_lo => db_lo_ds[6].OE
ctl_reg_out_lo => db_lo_ds[7].OE
ctl_reg_out_hi => db_hi_ds[0].OE
ctl_reg_out_hi => db_hi_ds[1].OE
ctl_reg_out_hi => db_hi_ds[2].OE
ctl_reg_out_hi => db_hi_ds[3].OE
ctl_reg_out_hi => db_hi_ds[4].OE
ctl_reg_out_hi => db_hi_ds[5].OE
ctl_reg_out_hi => db_hi_ds[6].OE
ctl_reg_out_hi => db_hi_ds[7].OE
clk => clk.IN28
reg_sw_4d_lo => db_lo_as[0].OE
reg_sw_4d_lo => db_lo_as[1].OE
reg_sw_4d_lo => db_lo_as[2].OE
reg_sw_4d_lo => db_lo_as[3].OE
reg_sw_4d_lo => db_lo_as[4].OE
reg_sw_4d_lo => db_lo_as[5].OE
reg_sw_4d_lo => db_lo_as[6].OE
reg_sw_4d_lo => db_lo_as[7].OE
reg_sw_4d_hi => db_hi_as[0].OE
reg_sw_4d_hi => db_hi_as[1].OE
reg_sw_4d_hi => db_hi_as[2].OE
reg_sw_4d_hi => db_hi_as[3].OE
reg_sw_4d_hi => db_hi_as[4].OE
reg_sw_4d_hi => db_hi_as[5].OE
reg_sw_4d_hi => db_hi_as[6].OE
reg_sw_4d_hi => db_hi_as[7].OE
db_hi_as[0] <> reg_latch:b2v_latch_ir_hi.db
db_hi_as[0] <> reg_latch:b2v_latch_pc_hi.db
db_hi_as[0] <> db_hi_as[0]
db_hi_as[1] <> reg_latch:b2v_latch_ir_hi.db
db_hi_as[1] <> reg_latch:b2v_latch_pc_hi.db
db_hi_as[1] <> db_hi_as[1]
db_hi_as[2] <> reg_latch:b2v_latch_ir_hi.db
db_hi_as[2] <> reg_latch:b2v_latch_pc_hi.db
db_hi_as[2] <> db_hi_as[2]
db_hi_as[3] <> reg_latch:b2v_latch_ir_hi.db
db_hi_as[3] <> reg_latch:b2v_latch_pc_hi.db
db_hi_as[3] <> db_hi_as[3]
db_hi_as[4] <> reg_latch:b2v_latch_ir_hi.db
db_hi_as[4] <> reg_latch:b2v_latch_pc_hi.db
db_hi_as[4] <> db_hi_as[4]
db_hi_as[5] <> reg_latch:b2v_latch_ir_hi.db
db_hi_as[5] <> reg_latch:b2v_latch_pc_hi.db
db_hi_as[5] <> db_hi_as[5]
db_hi_as[6] <> reg_latch:b2v_latch_ir_hi.db
db_hi_as[6] <> reg_latch:b2v_latch_pc_hi.db
db_hi_as[6] <> db_hi_as[6]
db_hi_as[7] <> reg_latch:b2v_latch_ir_hi.db
db_hi_as[7] <> reg_latch:b2v_latch_pc_hi.db
db_hi_as[7] <> db_hi_as[7]
db_hi_ds[0] <> db_hi_ds[0]
db_hi_ds[1] <> db_hi_ds[1]
db_hi_ds[2] <> db_hi_ds[2]
db_hi_ds[3] <> db_hi_ds[3]
db_hi_ds[4] <> db_hi_ds[4]
db_hi_ds[5] <> db_hi_ds[5]
db_hi_ds[6] <> db_hi_ds[6]
db_hi_ds[7] <> db_hi_ds[7]
db_lo_as[0] <> reg_latch:b2v_latch_ir_lo.db
db_lo_as[0] <> reg_latch:b2v_latch_pc_lo.db
db_lo_as[0] <> db_lo_as[0]
db_lo_as[1] <> reg_latch:b2v_latch_ir_lo.db
db_lo_as[1] <> reg_latch:b2v_latch_pc_lo.db
db_lo_as[1] <> db_lo_as[1]
db_lo_as[2] <> reg_latch:b2v_latch_ir_lo.db
db_lo_as[2] <> reg_latch:b2v_latch_pc_lo.db
db_lo_as[2] <> db_lo_as[2]
db_lo_as[3] <> reg_latch:b2v_latch_ir_lo.db
db_lo_as[3] <> reg_latch:b2v_latch_pc_lo.db
db_lo_as[3] <> db_lo_as[3]
db_lo_as[4] <> reg_latch:b2v_latch_ir_lo.db
db_lo_as[4] <> reg_latch:b2v_latch_pc_lo.db
db_lo_as[4] <> db_lo_as[4]
db_lo_as[5] <> reg_latch:b2v_latch_ir_lo.db
db_lo_as[5] <> reg_latch:b2v_latch_pc_lo.db
db_lo_as[5] <> db_lo_as[5]
db_lo_as[6] <> reg_latch:b2v_latch_ir_lo.db
db_lo_as[6] <> reg_latch:b2v_latch_pc_lo.db
db_lo_as[6] <> db_lo_as[6]
db_lo_as[7] <> reg_latch:b2v_latch_ir_lo.db
db_lo_as[7] <> reg_latch:b2v_latch_pc_lo.db
db_lo_as[7] <> db_lo_as[7]
db_lo_ds[0] <> db_lo_ds[0]
db_lo_ds[1] <> db_lo_ds[1]
db_lo_ds[2] <> db_lo_ds[2]
db_lo_ds[3] <> db_lo_ds[3]
db_lo_ds[4] <> db_lo_ds[4]
db_lo_ds[5] <> db_lo_ds[5]
db_lo_ds[6] <> db_lo_ds[6]
db_lo_ds[7] <> db_lo_ds[7]


|spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af2_hi
we => latch[0].ENA
we => latch[1].ENA
we => latch[2].ENA
we => latch[3].ENA
we => latch[4].ENA
we => latch[5].ENA
we => latch[6].ENA
we => latch[7].ENA
oe => db[0].OE
oe => db[1].OE
oe => db[2].OE
oe => db[3].OE
oe => db[4].OE
oe => db[5].OE
oe => db[6].OE
oe => db[7].OE
clk => latch[0].CLK
clk => latch[1].CLK
clk => latch[2].CLK
clk => latch[3].CLK
clk => latch[4].CLK
clk => latch[5].CLK
clk => latch[6].CLK
clk => latch[7].CLK
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af2_lo
we => latch[0].ENA
we => latch[1].ENA
we => latch[2].ENA
we => latch[3].ENA
we => latch[4].ENA
we => latch[5].ENA
we => latch[6].ENA
we => latch[7].ENA
oe => db[0].OE
oe => db[1].OE
oe => db[2].OE
oe => db[3].OE
oe => db[4].OE
oe => db[5].OE
oe => db[6].OE
oe => db[7].OE
clk => latch[0].CLK
clk => latch[1].CLK
clk => latch[2].CLK
clk => latch[3].CLK
clk => latch[4].CLK
clk => latch[5].CLK
clk => latch[6].CLK
clk => latch[7].CLK
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af_hi
we => latch[0].ENA
we => latch[1].ENA
we => latch[2].ENA
we => latch[3].ENA
we => latch[4].ENA
we => latch[5].ENA
we => latch[6].ENA
we => latch[7].ENA
oe => db[0].OE
oe => db[1].OE
oe => db[2].OE
oe => db[3].OE
oe => db[4].OE
oe => db[5].OE
oe => db[6].OE
oe => db[7].OE
clk => latch[0].CLK
clk => latch[1].CLK
clk => latch[2].CLK
clk => latch[3].CLK
clk => latch[4].CLK
clk => latch[5].CLK
clk => latch[6].CLK
clk => latch[7].CLK
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af_lo
we => latch[0].ENA
we => latch[1].ENA
we => latch[2].ENA
we => latch[3].ENA
we => latch[4].ENA
we => latch[5].ENA
we => latch[6].ENA
we => latch[7].ENA
oe => db[0].OE
oe => db[1].OE
oe => db[2].OE
oe => db[3].OE
oe => db[4].OE
oe => db[5].OE
oe => db[6].OE
oe => db[7].OE
clk => latch[0].CLK
clk => latch[1].CLK
clk => latch[2].CLK
clk => latch[3].CLK
clk => latch[4].CLK
clk => latch[5].CLK
clk => latch[6].CLK
clk => latch[7].CLK
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_bc2_hi
we => latch[0].ENA
we => latch[1].ENA
we => latch[2].ENA
we => latch[3].ENA
we => latch[4].ENA
we => latch[5].ENA
we => latch[6].ENA
we => latch[7].ENA
oe => db[0].OE
oe => db[1].OE
oe => db[2].OE
oe => db[3].OE
oe => db[4].OE
oe => db[5].OE
oe => db[6].OE
oe => db[7].OE
clk => latch[0].CLK
clk => latch[1].CLK
clk => latch[2].CLK
clk => latch[3].CLK
clk => latch[4].CLK
clk => latch[5].CLK
clk => latch[6].CLK
clk => latch[7].CLK
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_bc2_lo
we => latch[0].ENA
we => latch[1].ENA
we => latch[2].ENA
we => latch[3].ENA
we => latch[4].ENA
we => latch[5].ENA
we => latch[6].ENA
we => latch[7].ENA
oe => db[0].OE
oe => db[1].OE
oe => db[2].OE
oe => db[3].OE
oe => db[4].OE
oe => db[5].OE
oe => db[6].OE
oe => db[7].OE
clk => latch[0].CLK
clk => latch[1].CLK
clk => latch[2].CLK
clk => latch[3].CLK
clk => latch[4].CLK
clk => latch[5].CLK
clk => latch[6].CLK
clk => latch[7].CLK
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_bc_hi
we => latch[0].ENA
we => latch[1].ENA
we => latch[2].ENA
we => latch[3].ENA
we => latch[4].ENA
we => latch[5].ENA
we => latch[6].ENA
we => latch[7].ENA
oe => db[0].OE
oe => db[1].OE
oe => db[2].OE
oe => db[3].OE
oe => db[4].OE
oe => db[5].OE
oe => db[6].OE
oe => db[7].OE
clk => latch[0].CLK
clk => latch[1].CLK
clk => latch[2].CLK
clk => latch[3].CLK
clk => latch[4].CLK
clk => latch[5].CLK
clk => latch[6].CLK
clk => latch[7].CLK
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_bc_lo
we => latch[0].ENA
we => latch[1].ENA
we => latch[2].ENA
we => latch[3].ENA
we => latch[4].ENA
we => latch[5].ENA
we => latch[6].ENA
we => latch[7].ENA
oe => db[0].OE
oe => db[1].OE
oe => db[2].OE
oe => db[3].OE
oe => db[4].OE
oe => db[5].OE
oe => db[6].OE
oe => db[7].OE
clk => latch[0].CLK
clk => latch[1].CLK
clk => latch[2].CLK
clk => latch[3].CLK
clk => latch[4].CLK
clk => latch[5].CLK
clk => latch[6].CLK
clk => latch[7].CLK
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_de2_hi
we => latch[0].ENA
we => latch[1].ENA
we => latch[2].ENA
we => latch[3].ENA
we => latch[4].ENA
we => latch[5].ENA
we => latch[6].ENA
we => latch[7].ENA
oe => db[0].OE
oe => db[1].OE
oe => db[2].OE
oe => db[3].OE
oe => db[4].OE
oe => db[5].OE
oe => db[6].OE
oe => db[7].OE
clk => latch[0].CLK
clk => latch[1].CLK
clk => latch[2].CLK
clk => latch[3].CLK
clk => latch[4].CLK
clk => latch[5].CLK
clk => latch[6].CLK
clk => latch[7].CLK
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_de2_lo
we => latch[0].ENA
we => latch[1].ENA
we => latch[2].ENA
we => latch[3].ENA
we => latch[4].ENA
we => latch[5].ENA
we => latch[6].ENA
we => latch[7].ENA
oe => db[0].OE
oe => db[1].OE
oe => db[2].OE
oe => db[3].OE
oe => db[4].OE
oe => db[5].OE
oe => db[6].OE
oe => db[7].OE
clk => latch[0].CLK
clk => latch[1].CLK
clk => latch[2].CLK
clk => latch[3].CLK
clk => latch[4].CLK
clk => latch[5].CLK
clk => latch[6].CLK
clk => latch[7].CLK
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_de_hi
we => latch[0].ENA
we => latch[1].ENA
we => latch[2].ENA
we => latch[3].ENA
we => latch[4].ENA
we => latch[5].ENA
we => latch[6].ENA
we => latch[7].ENA
oe => db[0].OE
oe => db[1].OE
oe => db[2].OE
oe => db[3].OE
oe => db[4].OE
oe => db[5].OE
oe => db[6].OE
oe => db[7].OE
clk => latch[0].CLK
clk => latch[1].CLK
clk => latch[2].CLK
clk => latch[3].CLK
clk => latch[4].CLK
clk => latch[5].CLK
clk => latch[6].CLK
clk => latch[7].CLK
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_de_lo
we => latch[0].ENA
we => latch[1].ENA
we => latch[2].ENA
we => latch[3].ENA
we => latch[4].ENA
we => latch[5].ENA
we => latch[6].ENA
we => latch[7].ENA
oe => db[0].OE
oe => db[1].OE
oe => db[2].OE
oe => db[3].OE
oe => db[4].OE
oe => db[5].OE
oe => db[6].OE
oe => db[7].OE
clk => latch[0].CLK
clk => latch[1].CLK
clk => latch[2].CLK
clk => latch[3].CLK
clk => latch[4].CLK
clk => latch[5].CLK
clk => latch[6].CLK
clk => latch[7].CLK
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_hl2_hi
we => latch[0].ENA
we => latch[1].ENA
we => latch[2].ENA
we => latch[3].ENA
we => latch[4].ENA
we => latch[5].ENA
we => latch[6].ENA
we => latch[7].ENA
oe => db[0].OE
oe => db[1].OE
oe => db[2].OE
oe => db[3].OE
oe => db[4].OE
oe => db[5].OE
oe => db[6].OE
oe => db[7].OE
clk => latch[0].CLK
clk => latch[1].CLK
clk => latch[2].CLK
clk => latch[3].CLK
clk => latch[4].CLK
clk => latch[5].CLK
clk => latch[6].CLK
clk => latch[7].CLK
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_hl2_lo
we => latch[0].ENA
we => latch[1].ENA
we => latch[2].ENA
we => latch[3].ENA
we => latch[4].ENA
we => latch[5].ENA
we => latch[6].ENA
we => latch[7].ENA
oe => db[0].OE
oe => db[1].OE
oe => db[2].OE
oe => db[3].OE
oe => db[4].OE
oe => db[5].OE
oe => db[6].OE
oe => db[7].OE
clk => latch[0].CLK
clk => latch[1].CLK
clk => latch[2].CLK
clk => latch[3].CLK
clk => latch[4].CLK
clk => latch[5].CLK
clk => latch[6].CLK
clk => latch[7].CLK
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_hl_hi
we => latch[0].ENA
we => latch[1].ENA
we => latch[2].ENA
we => latch[3].ENA
we => latch[4].ENA
we => latch[5].ENA
we => latch[6].ENA
we => latch[7].ENA
oe => db[0].OE
oe => db[1].OE
oe => db[2].OE
oe => db[3].OE
oe => db[4].OE
oe => db[5].OE
oe => db[6].OE
oe => db[7].OE
clk => latch[0].CLK
clk => latch[1].CLK
clk => latch[2].CLK
clk => latch[3].CLK
clk => latch[4].CLK
clk => latch[5].CLK
clk => latch[6].CLK
clk => latch[7].CLK
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_hl_lo
we => latch[0].ENA
we => latch[1].ENA
we => latch[2].ENA
we => latch[3].ENA
we => latch[4].ENA
we => latch[5].ENA
we => latch[6].ENA
we => latch[7].ENA
oe => db[0].OE
oe => db[1].OE
oe => db[2].OE
oe => db[3].OE
oe => db[4].OE
oe => db[5].OE
oe => db[6].OE
oe => db[7].OE
clk => latch[0].CLK
clk => latch[1].CLK
clk => latch[2].CLK
clk => latch[3].CLK
clk => latch[4].CLK
clk => latch[5].CLK
clk => latch[6].CLK
clk => latch[7].CLK
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_ir_hi
we => latch[0].ENA
we => latch[1].ENA
we => latch[2].ENA
we => latch[3].ENA
we => latch[4].ENA
we => latch[5].ENA
we => latch[6].ENA
we => latch[7].ENA
oe => db[0].OE
oe => db[1].OE
oe => db[2].OE
oe => db[3].OE
oe => db[4].OE
oe => db[5].OE
oe => db[6].OE
oe => db[7].OE
clk => latch[0].CLK
clk => latch[1].CLK
clk => latch[2].CLK
clk => latch[3].CLK
clk => latch[4].CLK
clk => latch[5].CLK
clk => latch[6].CLK
clk => latch[7].CLK
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_ir_lo
we => latch[0].ENA
we => latch[1].ENA
we => latch[2].ENA
we => latch[3].ENA
we => latch[4].ENA
we => latch[5].ENA
we => latch[6].ENA
we => latch[7].ENA
oe => db[0].OE
oe => db[1].OE
oe => db[2].OE
oe => db[3].OE
oe => db[4].OE
oe => db[5].OE
oe => db[6].OE
oe => db[7].OE
clk => latch[0].CLK
clk => latch[1].CLK
clk => latch[2].CLK
clk => latch[3].CLK
clk => latch[4].CLK
clk => latch[5].CLK
clk => latch[6].CLK
clk => latch[7].CLK
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_ix_hi
we => latch[0].ENA
we => latch[1].ENA
we => latch[2].ENA
we => latch[3].ENA
we => latch[4].ENA
we => latch[5].ENA
we => latch[6].ENA
we => latch[7].ENA
oe => db[0].OE
oe => db[1].OE
oe => db[2].OE
oe => db[3].OE
oe => db[4].OE
oe => db[5].OE
oe => db[6].OE
oe => db[7].OE
clk => latch[0].CLK
clk => latch[1].CLK
clk => latch[2].CLK
clk => latch[3].CLK
clk => latch[4].CLK
clk => latch[5].CLK
clk => latch[6].CLK
clk => latch[7].CLK
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_ix_lo
we => latch[0].ENA
we => latch[1].ENA
we => latch[2].ENA
we => latch[3].ENA
we => latch[4].ENA
we => latch[5].ENA
we => latch[6].ENA
we => latch[7].ENA
oe => db[0].OE
oe => db[1].OE
oe => db[2].OE
oe => db[3].OE
oe => db[4].OE
oe => db[5].OE
oe => db[6].OE
oe => db[7].OE
clk => latch[0].CLK
clk => latch[1].CLK
clk => latch[2].CLK
clk => latch[3].CLK
clk => latch[4].CLK
clk => latch[5].CLK
clk => latch[6].CLK
clk => latch[7].CLK
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_iy_hi
we => latch[0].ENA
we => latch[1].ENA
we => latch[2].ENA
we => latch[3].ENA
we => latch[4].ENA
we => latch[5].ENA
we => latch[6].ENA
we => latch[7].ENA
oe => db[0].OE
oe => db[1].OE
oe => db[2].OE
oe => db[3].OE
oe => db[4].OE
oe => db[5].OE
oe => db[6].OE
oe => db[7].OE
clk => latch[0].CLK
clk => latch[1].CLK
clk => latch[2].CLK
clk => latch[3].CLK
clk => latch[4].CLK
clk => latch[5].CLK
clk => latch[6].CLK
clk => latch[7].CLK
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_iy_lo
we => latch[0].ENA
we => latch[1].ENA
we => latch[2].ENA
we => latch[3].ENA
we => latch[4].ENA
we => latch[5].ENA
we => latch[6].ENA
we => latch[7].ENA
oe => db[0].OE
oe => db[1].OE
oe => db[2].OE
oe => db[3].OE
oe => db[4].OE
oe => db[5].OE
oe => db[6].OE
oe => db[7].OE
clk => latch[0].CLK
clk => latch[1].CLK
clk => latch[2].CLK
clk => latch[3].CLK
clk => latch[4].CLK
clk => latch[5].CLK
clk => latch[6].CLK
clk => latch[7].CLK
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_pc_hi
we => latch[0].ENA
we => latch[1].ENA
we => latch[2].ENA
we => latch[3].ENA
we => latch[4].ENA
we => latch[5].ENA
we => latch[6].ENA
we => latch[7].ENA
oe => db[0].OE
oe => db[1].OE
oe => db[2].OE
oe => db[3].OE
oe => db[4].OE
oe => db[5].OE
oe => db[6].OE
oe => db[7].OE
clk => latch[0].CLK
clk => latch[1].CLK
clk => latch[2].CLK
clk => latch[3].CLK
clk => latch[4].CLK
clk => latch[5].CLK
clk => latch[6].CLK
clk => latch[7].CLK
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_pc_lo
we => latch[0].ENA
we => latch[1].ENA
we => latch[2].ENA
we => latch[3].ENA
we => latch[4].ENA
we => latch[5].ENA
we => latch[6].ENA
we => latch[7].ENA
oe => db[0].OE
oe => db[1].OE
oe => db[2].OE
oe => db[3].OE
oe => db[4].OE
oe => db[5].OE
oe => db[6].OE
oe => db[7].OE
clk => latch[0].CLK
clk => latch[1].CLK
clk => latch[2].CLK
clk => latch[3].CLK
clk => latch[4].CLK
clk => latch[5].CLK
clk => latch[6].CLK
clk => latch[7].CLK
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_sp_hi
we => latch[0].ENA
we => latch[1].ENA
we => latch[2].ENA
we => latch[3].ENA
we => latch[4].ENA
we => latch[5].ENA
we => latch[6].ENA
we => latch[7].ENA
oe => db[0].OE
oe => db[1].OE
oe => db[2].OE
oe => db[3].OE
oe => db[4].OE
oe => db[5].OE
oe => db[6].OE
oe => db[7].OE
clk => latch[0].CLK
clk => latch[1].CLK
clk => latch[2].CLK
clk => latch[3].CLK
clk => latch[4].CLK
clk => latch[5].CLK
clk => latch[6].CLK
clk => latch[7].CLK
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_sp_lo
we => latch[0].ENA
we => latch[1].ENA
we => latch[2].ENA
we => latch[3].ENA
we => latch[4].ENA
we => latch[5].ENA
we => latch[6].ENA
we => latch[7].ENA
oe => db[0].OE
oe => db[1].OE
oe => db[2].OE
oe => db[3].OE
oe => db[4].OE
oe => db[5].OE
oe => db[6].OE
oe => db[7].OE
clk => latch[0].CLK
clk => latch[1].CLK
clk => latch[2].CLK
clk => latch[3].CLK
clk => latch[4].CLK
clk => latch[5].CLK
clk => latch[6].CLK
clk => latch[7].CLK
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_wz_hi
we => latch[0].ENA
we => latch[1].ENA
we => latch[2].ENA
we => latch[3].ENA
we => latch[4].ENA
we => latch[5].ENA
we => latch[6].ENA
we => latch[7].ENA
oe => db[0].OE
oe => db[1].OE
oe => db[2].OE
oe => db[3].OE
oe => db[4].OE
oe => db[5].OE
oe => db[6].OE
oe => db[7].OE
clk => latch[0].CLK
clk => latch[1].CLK
clk => latch[2].CLK
clk => latch[3].CLK
clk => latch[4].CLK
clk => latch[5].CLK
clk => latch[6].CLK
clk => latch[7].CLK
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_wz_lo
we => latch[0].ENA
we => latch[1].ENA
we => latch[2].ENA
we => latch[3].ENA
we => latch[4].ENA
we => latch[5].ENA
we => latch[6].ENA
we => latch[7].ENA
oe => db[0].OE
oe => db[1].OE
oe => db[2].OE
oe => db[3].OE
oe => db[4].OE
oe => db[5].OE
oe => db[6].OE
oe => db[7].OE
clk => latch[0].CLK
clk => latch[1].CLK
clk => latch[2].CLK
clk => latch[3].CLK
clk => latch[4].CLK
clk => latch[5].CLK
clk => latch[6].CLK
clk => latch[7].CLK
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|reg_control:reg_control_
ctl_reg_exx => bank_exx.IN1
ctl_reg_ex_af => bank_af.IN1
ctl_reg_ex_de_hl => SYNTHESIZED_WIRE_50.IN1
ctl_reg_ex_de_hl => SYNTHESIZED_WIRE_43.IN1
ctl_reg_use_sp => reg_sel_sp.IN1
ctl_reg_use_sp => SYNTHESIZED_WIRE_54.IN1
nreset => bank_exx.ACLR
nreset => bank_af.ACLR
nreset => bank_hl_de2.ACLR
nreset => bank_hl_de1.ACLR
ctl_reg_sel_pc => reg_sel_pc.IN0
ctl_reg_sel_ir => SYNTHESIZED_WIRE_37.IN1
ctl_reg_sel_ir => reg_sel_ir.DATAIN
ctl_reg_sel_wz => reg_sel_wz.DATAIN
ctl_reg_gp_we => reg_gp_we.DATAIN
ctl_reg_not_pc => reg_sel_pc.IN1
use_ixiy => SYNTHESIZED_WIRE_56.IN1
use_ixiy => SYNTHESIZED_WIRE_58.IN1
use_ix => reg_sel_ix.IN1
use_ix => reg_sel_iy.IN1
ctl_reg_sys_we_lo => reg_sys_we_lo_ALTERA_SYNTHESIZED.IN0
ctl_reg_sys_we_hi => reg_sys_we_hi.IN0
ctl_reg_sys_we => reg_sys_we_hi.IN1
ctl_reg_sys_we => reg_sys_we_lo_ALTERA_SYNTHESIZED.IN1
clk => bank_exx.CLK
clk => bank_hl_de1.CLK
clk => bank_hl_de2.CLK
clk => bank_af.CLK
ctl_sw_4d => reg_sw_4d_hi.IN1
ctl_sw_4d => reg_sw_4d_lo.DATAIN
nhold_clk_wait => bank_exx.ENA
nhold_clk_wait => bank_af.ENA
nhold_clk_wait => bank_hl_de2.ENA
nhold_clk_wait => bank_hl_de1.ENA
ctl_reg_gp_hilo[0] => reg_sel_gp_lo.DATAIN
ctl_reg_gp_hilo[1] => reg_sel_gp_hi.DATAIN
ctl_reg_gp_sel[0] => SYNTHESIZED_WIRE_59.IN0
ctl_reg_gp_sel[0] => SYNTHESIZED_WIRE_55.IN0
ctl_reg_gp_sel[0] => SYNTHESIZED_WIRE_61.IN0
ctl_reg_gp_sel[0] => SYNTHESIZED_WIRE_52.IN0
ctl_reg_gp_sel[1] => SYNTHESIZED_WIRE_61.IN1
ctl_reg_gp_sel[1] => SYNTHESIZED_WIRE_55.IN1
ctl_reg_gp_sel[1] => SYNTHESIZED_WIRE_59.IN1
ctl_reg_gp_sel[1] => SYNTHESIZED_WIRE_52.IN1
ctl_reg_sys_hilo[0] => reg_sel_sys_lo.DATAIN
ctl_reg_sys_hilo[1] => SYNTHESIZED_WIRE_37.IN1
ctl_reg_sys_hilo[1] => reg_sel_sys_hi.DATAIN
reg_sel_bc <= reg_sel_bc.DB_MAX_OUTPUT_PORT_TYPE
reg_sel_bc2 <= reg_sel_bc2.DB_MAX_OUTPUT_PORT_TYPE
reg_sel_ix <= reg_sel_ix.DB_MAX_OUTPUT_PORT_TYPE
reg_sel_iy <= reg_sel_iy.DB_MAX_OUTPUT_PORT_TYPE
reg_sel_de <= reg_sel_de.DB_MAX_OUTPUT_PORT_TYPE
reg_sel_hl <= reg_sel_hl.DB_MAX_OUTPUT_PORT_TYPE
reg_sel_de2 <= reg_sel_de2.DB_MAX_OUTPUT_PORT_TYPE
reg_sel_hl2 <= reg_sel_hl2.DB_MAX_OUTPUT_PORT_TYPE
reg_sel_af <= reg_sel_af.DB_MAX_OUTPUT_PORT_TYPE
reg_sel_af2 <= reg_sel_af2.DB_MAX_OUTPUT_PORT_TYPE
reg_sel_wz <= ctl_reg_sel_wz.DB_MAX_OUTPUT_PORT_TYPE
reg_sel_pc <= reg_sel_pc.DB_MAX_OUTPUT_PORT_TYPE
reg_sel_ir <= ctl_reg_sel_ir.DB_MAX_OUTPUT_PORT_TYPE
reg_sel_sp <= reg_sel_sp.DB_MAX_OUTPUT_PORT_TYPE
reg_sel_gp_hi <= ctl_reg_gp_hilo[1].DB_MAX_OUTPUT_PORT_TYPE
reg_sel_gp_lo <= ctl_reg_gp_hilo[0].DB_MAX_OUTPUT_PORT_TYPE
reg_sel_sys_lo <= ctl_reg_sys_hilo[0].DB_MAX_OUTPUT_PORT_TYPE
reg_sel_sys_hi <= ctl_reg_sys_hilo[1].DB_MAX_OUTPUT_PORT_TYPE
reg_gp_we <= ctl_reg_gp_we.DB_MAX_OUTPUT_PORT_TYPE
reg_sys_we_lo <= reg_sys_we_lo_ALTERA_SYNTHESIZED.DB_MAX_OUTPUT_PORT_TYPE
reg_sys_we_hi <= reg_sys_we_hi.DB_MAX_OUTPUT_PORT_TYPE
reg_sw_4d_lo <= ctl_sw_4d.DB_MAX_OUTPUT_PORT_TYPE
reg_sw_4d_hi <= reg_sw_4d_hi.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|address_latch:address_latch_
ctl_inc_cy => ctl_inc_cy.IN1
ctl_inc_dec => ctl_inc_dec.IN1
ctl_al_we => Q.OUTPUTSELECT
ctl_al_we => Q.OUTPUTSELECT
ctl_al_we => Q.OUTPUTSELECT
ctl_al_we => Q.OUTPUTSELECT
ctl_al_we => Q.OUTPUTSELECT
ctl_al_we => Q.OUTPUTSELECT
ctl_al_we => Q.OUTPUTSELECT
ctl_al_we => Q.OUTPUTSELECT
ctl_al_we => Q.OUTPUTSELECT
ctl_al_we => Q.OUTPUTSELECT
ctl_al_we => Q.OUTPUTSELECT
ctl_al_we => Q.OUTPUTSELECT
ctl_al_we => Q.OUTPUTSELECT
ctl_al_we => Q.OUTPUTSELECT
ctl_al_we => Q.OUTPUTSELECT
ctl_al_we => Q.OUTPUTSELECT
ctl_inc_limit6 => ctl_inc_limit6.IN1
ctl_bus_inc_oe => abus[0].OE
ctl_bus_inc_oe => abus[1].OE
ctl_bus_inc_oe => abus[2].OE
ctl_bus_inc_oe => abus[3].OE
ctl_bus_inc_oe => abus[4].OE
ctl_bus_inc_oe => abus[5].OE
ctl_bus_inc_oe => abus[6].OE
ctl_bus_inc_oe => abus[7].OE
ctl_bus_inc_oe => abus[8].OE
ctl_bus_inc_oe => abus[9].OE
ctl_bus_inc_oe => abus[10].OE
ctl_bus_inc_oe => abus[11].OE
ctl_bus_inc_oe => abus[12].OE
ctl_bus_inc_oe => abus[13].OE
ctl_bus_inc_oe => abus[14].OE
ctl_bus_inc_oe => abus[15].OE
clk => Q[0].CLK
clk => Q[1].CLK
clk => Q[2].CLK
clk => Q[3].CLK
clk => Q[4].CLK
clk => Q[5].CLK
clk => Q[6].CLK
clk => Q[7].CLK
clk => Q[8].CLK
clk => Q[9].CLK
clk => Q[10].CLK
clk => Q[11].CLK
clk => Q[12].CLK
clk => Q[13].CLK
clk => Q[14].CLK
clk => Q[15].CLK
ctl_apin_mux => ctl_apin_mux.IN1
ctl_apin_mux2 => ctl_apin_mux2.IN1
clrpc => abusz.IN1
clrpc => abusz.IN1
clrpc => abusz.IN1
clrpc => abusz.IN1
clrpc => abusz.IN1
clrpc => abusz.IN1
clrpc => abusz.IN1
clrpc => abusz.IN1
clrpc => abusz.IN1
clrpc => abusz.IN1
clrpc => abusz.IN1
clrpc => abusz.IN1
clrpc => abusz.IN1
clrpc => abusz.IN1
clrpc => abusz.IN1
clrpc => abusz.IN1
nreset => Q[0].ACLR
nreset => Q[1].ACLR
nreset => Q[2].ACLR
nreset => Q[3].ACLR
nreset => Q[4].ACLR
nreset => Q[5].ACLR
nreset => Q[6].ACLR
nreset => Q[7].ACLR
nreset => Q[8].ACLR
nreset => Q[9].ACLR
nreset => Q[10].ACLR
nreset => Q[11].ACLR
nreset => Q[12].ACLR
nreset => Q[13].ACLR
nreset => Q[14].ACLR
nreset => Q[15].ACLR
address_is_1 <= address_is_1.DB_MAX_OUTPUT_PORT_TYPE
abus[0] <> abus[0]
abus[1] <> abus[1]
abus[2] <> abus[2]
abus[3] <> abus[3]
abus[4] <> abus[4]
abus[5] <> abus[5]
abus[6] <> abus[6]
abus[7] <> abus[7]
abus[8] <> abus[8]
abus[9] <> abus[9]
abus[10] <> abus[10]
abus[11] <> abus[11]
abus[12] <> abus[12]
abus[13] <> abus[13]
abus[14] <> abus[14]
abus[15] <> abus[15]
address[0] <= address_mux:b2v_inst7.out
address[1] <= address_mux:b2v_inst7.out
address[2] <= address_mux:b2v_inst7.out
address[3] <= address_mux:b2v_inst7.out
address[4] <= address_mux:b2v_inst7.out
address[5] <= address_mux:b2v_inst7.out
address[6] <= address_mux:b2v_inst7.out
address[7] <= address_mux:b2v_inst7.out
address[8] <= address_mux:b2v_inst7.out
address[9] <= address_mux:b2v_inst7.out
address[10] <= address_mux:b2v_inst7.out
address[11] <= address_mux:b2v_inst7.out
address[12] <= address_mux:b2v_inst7.out
address[13] <= address_mux:b2v_inst7.out
address[14] <= address_mux:b2v_inst7.out
address[15] <= address_mux:b2v_inst7.out


|spectrum|z80_top_direct_n:z80_|address_latch:address_latch_|address_mux:b2v_inst7
select => SYNTHESIZED_WIRE_2[0].IN0
select => SYNTHESIZED_WIRE_2[1].IN0
select => SYNTHESIZED_WIRE_2[2].IN0
select => SYNTHESIZED_WIRE_2[3].IN0
select => SYNTHESIZED_WIRE_2[4].IN0
select => SYNTHESIZED_WIRE_2[5].IN0
select => SYNTHESIZED_WIRE_2[6].IN0
select => SYNTHESIZED_WIRE_2[7].IN0
select => SYNTHESIZED_WIRE_2[8].IN0
select => SYNTHESIZED_WIRE_2[9].IN0
select => SYNTHESIZED_WIRE_2[10].IN0
select => SYNTHESIZED_WIRE_2[11].IN0
select => SYNTHESIZED_WIRE_2[12].IN0
select => SYNTHESIZED_WIRE_2[13].IN0
select => SYNTHESIZED_WIRE_2[14].IN0
select => SYNTHESIZED_WIRE_2[15].IN0
select => SYNTHESIZED_WIRE_1[0].IN0
select => SYNTHESIZED_WIRE_1[1].IN0
select => SYNTHESIZED_WIRE_1[2].IN0
select => SYNTHESIZED_WIRE_1[3].IN0
select => SYNTHESIZED_WIRE_1[4].IN0
select => SYNTHESIZED_WIRE_1[5].IN0
select => SYNTHESIZED_WIRE_1[6].IN0
select => SYNTHESIZED_WIRE_1[7].IN0
select => SYNTHESIZED_WIRE_1[8].IN0
select => SYNTHESIZED_WIRE_1[9].IN0
select => SYNTHESIZED_WIRE_1[10].IN0
select => SYNTHESIZED_WIRE_1[11].IN0
select => SYNTHESIZED_WIRE_1[12].IN0
select => SYNTHESIZED_WIRE_1[13].IN0
select => SYNTHESIZED_WIRE_1[14].IN0
select => SYNTHESIZED_WIRE_1[15].IN0
in0[0] => SYNTHESIZED_WIRE_1[0].IN1
in0[1] => SYNTHESIZED_WIRE_1[1].IN1
in0[2] => SYNTHESIZED_WIRE_1[2].IN1
in0[3] => SYNTHESIZED_WIRE_1[3].IN1
in0[4] => SYNTHESIZED_WIRE_1[4].IN1
in0[5] => SYNTHESIZED_WIRE_1[5].IN1
in0[6] => SYNTHESIZED_WIRE_1[6].IN1
in0[7] => SYNTHESIZED_WIRE_1[7].IN1
in0[8] => SYNTHESIZED_WIRE_1[8].IN1
in0[9] => SYNTHESIZED_WIRE_1[9].IN1
in0[10] => SYNTHESIZED_WIRE_1[10].IN1
in0[11] => SYNTHESIZED_WIRE_1[11].IN1
in0[12] => SYNTHESIZED_WIRE_1[12].IN1
in0[13] => SYNTHESIZED_WIRE_1[13].IN1
in0[14] => SYNTHESIZED_WIRE_1[14].IN1
in0[15] => SYNTHESIZED_WIRE_1[15].IN1
in1[0] => SYNTHESIZED_WIRE_2[0].IN1
in1[1] => SYNTHESIZED_WIRE_2[1].IN1
in1[2] => SYNTHESIZED_WIRE_2[2].IN1
in1[3] => SYNTHESIZED_WIRE_2[3].IN1
in1[4] => SYNTHESIZED_WIRE_2[4].IN1
in1[5] => SYNTHESIZED_WIRE_2[5].IN1
in1[6] => SYNTHESIZED_WIRE_2[6].IN1
in1[7] => SYNTHESIZED_WIRE_2[7].IN1
in1[8] => SYNTHESIZED_WIRE_2[8].IN1
in1[9] => SYNTHESIZED_WIRE_2[9].IN1
in1[10] => SYNTHESIZED_WIRE_2[10].IN1
in1[11] => SYNTHESIZED_WIRE_2[11].IN1
in1[12] => SYNTHESIZED_WIRE_2[12].IN1
in1[13] => SYNTHESIZED_WIRE_2[13].IN1
in1[14] => SYNTHESIZED_WIRE_2[14].IN1
in1[15] => SYNTHESIZED_WIRE_2[15].IN1
out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= out.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= out.DB_MAX_OUTPUT_PORT_TYPE
out[4] <= out.DB_MAX_OUTPUT_PORT_TYPE
out[5] <= out.DB_MAX_OUTPUT_PORT_TYPE
out[6] <= out.DB_MAX_OUTPUT_PORT_TYPE
out[7] <= out.DB_MAX_OUTPUT_PORT_TYPE
out[8] <= out.DB_MAX_OUTPUT_PORT_TYPE
out[9] <= out.DB_MAX_OUTPUT_PORT_TYPE
out[10] <= out.DB_MAX_OUTPUT_PORT_TYPE
out[11] <= out.DB_MAX_OUTPUT_PORT_TYPE
out[12] <= out.DB_MAX_OUTPUT_PORT_TYPE
out[13] <= out.DB_MAX_OUTPUT_PORT_TYPE
out[14] <= out.DB_MAX_OUTPUT_PORT_TYPE
out[15] <= out.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec
carry_in => carry_in.IN1
limit6 => SYNTHESIZED_WIRE_47.IN1
decrement => SYNTHESIZED_WIRE_41.IN0
decrement => SYNTHESIZED_WIRE_40.IN0
decrement => SYNTHESIZED_WIRE_50.IN0
decrement => SYNTHESIZED_WIRE_12.IN0
decrement => SYNTHESIZED_WIRE_52.IN0
decrement => SYNTHESIZED_WIRE_53.IN0
decrement => SYNTHESIZED_WIRE_16.IN0
decrement => SYNTHESIZED_WIRE_42.IN0
decrement => SYNTHESIZED_WIRE_45.IN0
decrement => SYNTHESIZED_WIRE_44.IN0
decrement => SYNTHESIZED_WIRE_43.IN0
decrement => SYNTHESIZED_WIRE_5.IN0
decrement => SYNTHESIZED_WIRE_48.IN0
decrement => SYNTHESIZED_WIRE_46.IN0
decrement => SYNTHESIZED_WIRE_49.IN0
d[0] => d[0].IN1
d[1] => d[1].IN1
d[2] => d[2].IN1
d[3] => d[3].IN1
d[4] => d[4].IN1
d[5] => d[5].IN1
d[6] => SYNTHESIZED_WIRE_5.IN1
d[6] => address_ALTERA_SYNTHESIZED.IN1
d[7] => d[7].IN1
d[8] => d[8].IN1
d[9] => d[9].IN1
d[10] => d[10].IN1
d[11] => SYNTHESIZED_WIRE_12.IN1
d[11] => address_ALTERA_SYNTHESIZED.IN1
d[12] => d[12].IN1
d[13] => d[13].IN1
d[14] => SYNTHESIZED_WIRE_16.IN1
d[14] => address_ALTERA_SYNTHESIZED.IN1
d[15] => address_ALTERA_SYNTHESIZED.IN1
address[0] <= inc_dec_2bit:b2v_dual_adder_0.d0_out
address[1] <= inc_dec_2bit:b2v_dual_adder_0.d1_out
address[2] <= inc_dec_2bit:b2v_dual_adder_2.d0_out
address[3] <= inc_dec_2bit:b2v_dual_adder_2.d1_out
address[4] <= inc_dec_2bit:b2v_dual_adder_4.d0_out
address[5] <= inc_dec_2bit:b2v_dual_adder_4.d1_out
address[6] <= address_ALTERA_SYNTHESIZED.DB_MAX_OUTPUT_PORT_TYPE
address[7] <= inc_dec_2bit:b2v_dual_adder_7.d0_out
address[8] <= inc_dec_2bit:b2v_dual_adder_7.d1_out
address[9] <= inc_dec_2bit:b2v_dual_adder_9.d0_out
address[10] <= inc_dec_2bit:b2v_dual_adder_9.d1_out
address[11] <= address_ALTERA_SYNTHESIZED.DB_MAX_OUTPUT_PORT_TYPE
address[12] <= inc_dec_2bit:b2v_dual_adder_10.d0_out
address[13] <= inc_dec_2bit:b2v_dual_adder_10.d1_out
address[14] <= address_ALTERA_SYNTHESIZED.DB_MAX_OUTPUT_PORT_TYPE
address[15] <= address_ALTERA_SYNTHESIZED.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_0
carry_borrow_in => SYNTHESIZED_WIRE_0.IN0
carry_borrow_in => carry_borrow_out.IN1
carry_borrow_in => d0_out.IN0
d1_in => d1_out.IN1
d0_in => d0_out.IN1
dec1_in => carry_borrow_out.IN0
dec0_in => SYNTHESIZED_WIRE_0.IN1
dec0_in => carry_borrow_out.IN1
carry_borrow_out <= carry_borrow_out.DB_MAX_OUTPUT_PORT_TYPE
d1_out <= d1_out.DB_MAX_OUTPUT_PORT_TYPE
d0_out <= d0_out.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_10
carry_borrow_in => SYNTHESIZED_WIRE_0.IN0
carry_borrow_in => carry_borrow_out.IN1
carry_borrow_in => d0_out.IN0
d1_in => d1_out.IN1
d0_in => d0_out.IN1
dec1_in => carry_borrow_out.IN0
dec0_in => SYNTHESIZED_WIRE_0.IN1
dec0_in => carry_borrow_out.IN1
carry_borrow_out <= carry_borrow_out.DB_MAX_OUTPUT_PORT_TYPE
d1_out <= d1_out.DB_MAX_OUTPUT_PORT_TYPE
d0_out <= d0_out.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_2
carry_borrow_in => SYNTHESIZED_WIRE_0.IN0
carry_borrow_in => carry_borrow_out.IN1
carry_borrow_in => d0_out.IN0
d1_in => d1_out.IN1
d0_in => d0_out.IN1
dec1_in => carry_borrow_out.IN0
dec0_in => SYNTHESIZED_WIRE_0.IN1
dec0_in => carry_borrow_out.IN1
carry_borrow_out <= carry_borrow_out.DB_MAX_OUTPUT_PORT_TYPE
d1_out <= d1_out.DB_MAX_OUTPUT_PORT_TYPE
d0_out <= d0_out.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_4
carry_borrow_in => SYNTHESIZED_WIRE_0.IN0
carry_borrow_in => carry_borrow_out.IN1
carry_borrow_in => d0_out.IN0
d1_in => d1_out.IN1
d0_in => d0_out.IN1
dec1_in => carry_borrow_out.IN0
dec0_in => SYNTHESIZED_WIRE_0.IN1
dec0_in => carry_borrow_out.IN1
carry_borrow_out <= carry_borrow_out.DB_MAX_OUTPUT_PORT_TYPE
d1_out <= d1_out.DB_MAX_OUTPUT_PORT_TYPE
d0_out <= d0_out.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_7
carry_borrow_in => SYNTHESIZED_WIRE_0.IN0
carry_borrow_in => carry_borrow_out.IN1
carry_borrow_in => d0_out.IN0
d1_in => d1_out.IN1
d0_in => d0_out.IN1
dec1_in => carry_borrow_out.IN0
dec0_in => SYNTHESIZED_WIRE_0.IN1
dec0_in => carry_borrow_out.IN1
carry_borrow_out <= carry_borrow_out.DB_MAX_OUTPUT_PORT_TYPE
d1_out <= d1_out.DB_MAX_OUTPUT_PORT_TYPE
d0_out <= d0_out.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_9
carry_borrow_in => SYNTHESIZED_WIRE_0.IN0
carry_borrow_in => carry_borrow_out.IN1
carry_borrow_in => d0_out.IN0
d1_in => d1_out.IN1
d0_in => d0_out.IN1
dec1_in => carry_borrow_out.IN0
dec0_in => SYNTHESIZED_WIRE_0.IN1
dec0_in => carry_borrow_out.IN1
carry_borrow_out <= carry_borrow_out.DB_MAX_OUTPUT_PORT_TYPE
d1_out <= d1_out.DB_MAX_OUTPUT_PORT_TYPE
d0_out <= d0_out.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|address_latch:address_latch_|address_mux:b2v_mux
select => SYNTHESIZED_WIRE_2[0].IN0
select => SYNTHESIZED_WIRE_2[1].IN0
select => SYNTHESIZED_WIRE_2[2].IN0
select => SYNTHESIZED_WIRE_2[3].IN0
select => SYNTHESIZED_WIRE_2[4].IN0
select => SYNTHESIZED_WIRE_2[5].IN0
select => SYNTHESIZED_WIRE_2[6].IN0
select => SYNTHESIZED_WIRE_2[7].IN0
select => SYNTHESIZED_WIRE_2[8].IN0
select => SYNTHESIZED_WIRE_2[9].IN0
select => SYNTHESIZED_WIRE_2[10].IN0
select => SYNTHESIZED_WIRE_2[11].IN0
select => SYNTHESIZED_WIRE_2[12].IN0
select => SYNTHESIZED_WIRE_2[13].IN0
select => SYNTHESIZED_WIRE_2[14].IN0
select => SYNTHESIZED_WIRE_2[15].IN0
select => SYNTHESIZED_WIRE_1[0].IN0
select => SYNTHESIZED_WIRE_1[1].IN0
select => SYNTHESIZED_WIRE_1[2].IN0
select => SYNTHESIZED_WIRE_1[3].IN0
select => SYNTHESIZED_WIRE_1[4].IN0
select => SYNTHESIZED_WIRE_1[5].IN0
select => SYNTHESIZED_WIRE_1[6].IN0
select => SYNTHESIZED_WIRE_1[7].IN0
select => SYNTHESIZED_WIRE_1[8].IN0
select => SYNTHESIZED_WIRE_1[9].IN0
select => SYNTHESIZED_WIRE_1[10].IN0
select => SYNTHESIZED_WIRE_1[11].IN0
select => SYNTHESIZED_WIRE_1[12].IN0
select => SYNTHESIZED_WIRE_1[13].IN0
select => SYNTHESIZED_WIRE_1[14].IN0
select => SYNTHESIZED_WIRE_1[15].IN0
in0[0] => SYNTHESIZED_WIRE_1[0].IN1
in0[1] => SYNTHESIZED_WIRE_1[1].IN1
in0[2] => SYNTHESIZED_WIRE_1[2].IN1
in0[3] => SYNTHESIZED_WIRE_1[3].IN1
in0[4] => SYNTHESIZED_WIRE_1[4].IN1
in0[5] => SYNTHESIZED_WIRE_1[5].IN1
in0[6] => SYNTHESIZED_WIRE_1[6].IN1
in0[7] => SYNTHESIZED_WIRE_1[7].IN1
in0[8] => SYNTHESIZED_WIRE_1[8].IN1
in0[9] => SYNTHESIZED_WIRE_1[9].IN1
in0[10] => SYNTHESIZED_WIRE_1[10].IN1
in0[11] => SYNTHESIZED_WIRE_1[11].IN1
in0[12] => SYNTHESIZED_WIRE_1[12].IN1
in0[13] => SYNTHESIZED_WIRE_1[13].IN1
in0[14] => SYNTHESIZED_WIRE_1[14].IN1
in0[15] => SYNTHESIZED_WIRE_1[15].IN1
in1[0] => SYNTHESIZED_WIRE_2[0].IN1
in1[1] => SYNTHESIZED_WIRE_2[1].IN1
in1[2] => SYNTHESIZED_WIRE_2[2].IN1
in1[3] => SYNTHESIZED_WIRE_2[3].IN1
in1[4] => SYNTHESIZED_WIRE_2[4].IN1
in1[5] => SYNTHESIZED_WIRE_2[5].IN1
in1[6] => SYNTHESIZED_WIRE_2[6].IN1
in1[7] => SYNTHESIZED_WIRE_2[7].IN1
in1[8] => SYNTHESIZED_WIRE_2[8].IN1
in1[9] => SYNTHESIZED_WIRE_2[9].IN1
in1[10] => SYNTHESIZED_WIRE_2[10].IN1
in1[11] => SYNTHESIZED_WIRE_2[11].IN1
in1[12] => SYNTHESIZED_WIRE_2[12].IN1
in1[13] => SYNTHESIZED_WIRE_2[13].IN1
in1[14] => SYNTHESIZED_WIRE_2[14].IN1
in1[15] => SYNTHESIZED_WIRE_2[15].IN1
out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= out.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= out.DB_MAX_OUTPUT_PORT_TYPE
out[4] <= out.DB_MAX_OUTPUT_PORT_TYPE
out[5] <= out.DB_MAX_OUTPUT_PORT_TYPE
out[6] <= out.DB_MAX_OUTPUT_PORT_TYPE
out[7] <= out.DB_MAX_OUTPUT_PORT_TYPE
out[8] <= out.DB_MAX_OUTPUT_PORT_TYPE
out[9] <= out.DB_MAX_OUTPUT_PORT_TYPE
out[10] <= out.DB_MAX_OUTPUT_PORT_TYPE
out[11] <= out.DB_MAX_OUTPUT_PORT_TYPE
out[12] <= out.DB_MAX_OUTPUT_PORT_TYPE
out[13] <= out.DB_MAX_OUTPUT_PORT_TYPE
out[14] <= out.DB_MAX_OUTPUT_PORT_TYPE
out[15] <= out.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|bus_control:bus_control_
ctl_bus_ff_oe => SYNTHESIZED_WIRE_0.IN0
ctl_bus_ff_oe => db[0].DATAIN
ctl_bus_ff_oe => db[1].DATAIN
ctl_bus_ff_oe => db[2].DATAIN
ctl_bus_ff_oe => db[3].DATAIN
ctl_bus_ff_oe => db[4].DATAIN
ctl_bus_ff_oe => db[5].DATAIN
ctl_bus_ff_oe => db[6].DATAIN
ctl_bus_ff_oe => db[7].DATAIN
ctl_bus_zero_oe => SYNTHESIZED_WIRE_0.IN1
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|bus_switch:bus_switch_
ctl_sw_1u => bus_sw_1u.DATAIN
ctl_sw_1d => bus_sw_1d.DATAIN
ctl_sw_2u => bus_sw_2u.DATAIN
ctl_sw_2d => bus_sw_2d.DATAIN
ctl_sw_mask543_en => bus_sw_mask543_en.DATAIN
bus_sw_1u <= ctl_sw_1u.DB_MAX_OUTPUT_PORT_TYPE
bus_sw_1d <= ctl_sw_1d.DB_MAX_OUTPUT_PORT_TYPE
bus_sw_2u <= ctl_sw_2u.DB_MAX_OUTPUT_PORT_TYPE
bus_sw_2d <= ctl_sw_2d.DB_MAX_OUTPUT_PORT_TYPE
bus_sw_mask543_en <= ctl_sw_mask543_en.DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|data_switch:sw2_
sw_up_en => db_up[0].OE
sw_up_en => db_up[1].OE
sw_up_en => db_up[2].OE
sw_up_en => db_up[3].OE
sw_up_en => db_up[4].OE
sw_up_en => db_up[5].OE
sw_up_en => db_up[6].OE
sw_up_en => db_up[7].OE
sw_down_en => db_down[0].OE
sw_down_en => db_down[1].OE
sw_down_en => db_down[2].OE
sw_down_en => db_down[3].OE
sw_down_en => db_down[4].OE
sw_down_en => db_down[5].OE
sw_down_en => db_down[6].OE
sw_down_en => db_down[7].OE
db_down[0] <> db_down[0]
db_down[1] <> db_down[1]
db_down[2] <> db_down[2]
db_down[3] <> db_down[3]
db_down[4] <> db_down[4]
db_down[5] <> db_down[5]
db_down[6] <> db_down[6]
db_down[7] <> db_down[7]
db_up[0] <> db_up[0]
db_up[1] <> db_up[1]
db_up[2] <> db_up[2]
db_up[3] <> db_up[3]
db_up[4] <> db_up[4]
db_up[5] <> db_up[5]
db_up[6] <> db_up[6]
db_up[7] <> db_up[7]


|spectrum|z80_top_direct_n:z80_|data_switch_mask:sw1_
sw_up_en => db_up[0].OE
sw_up_en => db_up[1].OE
sw_up_en => db_up[2].OE
sw_up_en => db_up[3].OE
sw_up_en => db_up[4].OE
sw_up_en => db_up[5].OE
sw_up_en => db_up[6].OE
sw_up_en => db_up[7].OE
sw_down_en => db_down[3].OE
sw_down_en => db_down[4].OE
sw_down_en => db_down[5].OE
sw_down_en => db_down[0].OE
sw_down_en => db_down[1].OE
sw_down_en => db_down[2].OE
sw_down_en => db_down[6].OE
sw_down_en => db_down[7].OE
sw_mask543_en => SYNTHESIZED_WIRE_1[0].IN1
sw_mask543_en => SYNTHESIZED_WIRE_1[1].IN1
sw_mask543_en => SYNTHESIZED_WIRE_2[0].IN1
sw_mask543_en => SYNTHESIZED_WIRE_2[1].IN1
sw_mask543_en => SYNTHESIZED_WIRE_2[2].IN1
db_down[0] <> db_down[0]
db_down[1] <> db_down[1]
db_down[2] <> db_down[2]
db_down[3] <> db_down[3]
db_down[4] <> db_down[4]
db_down[5] <> db_down[5]
db_down[6] <> db_down[6]
db_down[7] <> db_down[7]
db_up[0] <> db_up[0]
db_up[1] <> db_up[1]
db_up[2] <> db_up[2]
db_up[3] <> db_up[3]
db_up[4] <> db_up[4]
db_up[5] <> db_up[5]
db_up[6] <> db_up[6]
db_up[7] <> db_up[7]


|spectrum|z80_top_direct_n:z80_|address_pins:address_pins_
clk => DFFE_apin_latch[0].CLK
clk => DFFE_apin_latch[1].CLK
clk => DFFE_apin_latch[2].CLK
clk => DFFE_apin_latch[3].CLK
clk => DFFE_apin_latch[4].CLK
clk => DFFE_apin_latch[5].CLK
clk => DFFE_apin_latch[6].CLK
clk => DFFE_apin_latch[7].CLK
clk => DFFE_apin_latch[8].CLK
clk => DFFE_apin_latch[9].CLK
clk => DFFE_apin_latch[10].CLK
clk => DFFE_apin_latch[11].CLK
clk => DFFE_apin_latch[12].CLK
clk => DFFE_apin_latch[13].CLK
clk => DFFE_apin_latch[14].CLK
clk => DFFE_apin_latch[15].CLK
bus_ab_pin_we => DFFE_apin_latch[0].ENA
bus_ab_pin_we => DFFE_apin_latch[1].ENA
bus_ab_pin_we => DFFE_apin_latch[2].ENA
bus_ab_pin_we => DFFE_apin_latch[3].ENA
bus_ab_pin_we => DFFE_apin_latch[4].ENA
bus_ab_pin_we => DFFE_apin_latch[5].ENA
bus_ab_pin_we => DFFE_apin_latch[6].ENA
bus_ab_pin_we => DFFE_apin_latch[7].ENA
bus_ab_pin_we => DFFE_apin_latch[8].ENA
bus_ab_pin_we => DFFE_apin_latch[9].ENA
bus_ab_pin_we => DFFE_apin_latch[10].ENA
bus_ab_pin_we => DFFE_apin_latch[11].ENA
bus_ab_pin_we => DFFE_apin_latch[12].ENA
bus_ab_pin_we => DFFE_apin_latch[13].ENA
bus_ab_pin_we => DFFE_apin_latch[14].ENA
bus_ab_pin_we => DFFE_apin_latch[15].ENA
pin_control_oe => abus[0].OE
pin_control_oe => abus[1].OE
pin_control_oe => abus[2].OE
pin_control_oe => abus[3].OE
pin_control_oe => abus[4].OE
pin_control_oe => abus[5].OE
pin_control_oe => abus[6].OE
pin_control_oe => abus[7].OE
pin_control_oe => abus[8].OE
pin_control_oe => abus[9].OE
pin_control_oe => abus[10].OE
pin_control_oe => abus[11].OE
pin_control_oe => abus[12].OE
pin_control_oe => abus[13].OE
pin_control_oe => abus[14].OE
pin_control_oe => abus[15].OE
address[0] => DFFE_apin_latch[0].DATAIN
address[1] => DFFE_apin_latch[1].DATAIN
address[2] => DFFE_apin_latch[2].DATAIN
address[3] => DFFE_apin_latch[3].DATAIN
address[4] => DFFE_apin_latch[4].DATAIN
address[5] => DFFE_apin_latch[5].DATAIN
address[6] => DFFE_apin_latch[6].DATAIN
address[7] => DFFE_apin_latch[7].DATAIN
address[8] => DFFE_apin_latch[8].DATAIN
address[9] => DFFE_apin_latch[9].DATAIN
address[10] => DFFE_apin_latch[10].DATAIN
address[11] => DFFE_apin_latch[11].DATAIN
address[12] => DFFE_apin_latch[12].DATAIN
address[13] => DFFE_apin_latch[13].DATAIN
address[14] => DFFE_apin_latch[14].DATAIN
address[15] => DFFE_apin_latch[15].DATAIN
abus[0] <= abus[0].DB_MAX_OUTPUT_PORT_TYPE
abus[1] <= abus[1].DB_MAX_OUTPUT_PORT_TYPE
abus[2] <= abus[2].DB_MAX_OUTPUT_PORT_TYPE
abus[3] <= abus[3].DB_MAX_OUTPUT_PORT_TYPE
abus[4] <= abus[4].DB_MAX_OUTPUT_PORT_TYPE
abus[5] <= abus[5].DB_MAX_OUTPUT_PORT_TYPE
abus[6] <= abus[6].DB_MAX_OUTPUT_PORT_TYPE
abus[7] <= abus[7].DB_MAX_OUTPUT_PORT_TYPE
abus[8] <= abus[8].DB_MAX_OUTPUT_PORT_TYPE
abus[9] <= abus[9].DB_MAX_OUTPUT_PORT_TYPE
abus[10] <= abus[10].DB_MAX_OUTPUT_PORT_TYPE
abus[11] <= abus[11].DB_MAX_OUTPUT_PORT_TYPE
abus[12] <= abus[12].DB_MAX_OUTPUT_PORT_TYPE
abus[13] <= abus[13].DB_MAX_OUTPUT_PORT_TYPE
abus[14] <= abus[14].DB_MAX_OUTPUT_PORT_TYPE
abus[15] <= abus[15].DB_MAX_OUTPUT_PORT_TYPE


|spectrum|z80_top_direct_n:z80_|data_pins:data_pins_
bus_db_pin_oe => D[0].OE
bus_db_pin_oe => D[1].OE
bus_db_pin_oe => D[2].OE
bus_db_pin_oe => D[3].OE
bus_db_pin_oe => D[4].OE
bus_db_pin_oe => D[5].OE
bus_db_pin_oe => D[6].OE
bus_db_pin_oe => D[7].OE
bus_db_pin_re => SYNTHESIZED_WIRE_3[0].IN1
bus_db_pin_re => SYNTHESIZED_WIRE_3[1].IN1
bus_db_pin_re => SYNTHESIZED_WIRE_3[2].IN1
bus_db_pin_re => SYNTHESIZED_WIRE_3[3].IN1
bus_db_pin_re => SYNTHESIZED_WIRE_3[4].IN1
bus_db_pin_re => SYNTHESIZED_WIRE_3[5].IN1
bus_db_pin_re => SYNTHESIZED_WIRE_3[6].IN1
bus_db_pin_re => SYNTHESIZED_WIRE_3[7].IN1
bus_db_pin_re => SYNTHESIZED_WIRE_2.IN0
ctl_bus_db_we => SYNTHESIZED_WIRE_4[0].IN1
ctl_bus_db_we => SYNTHESIZED_WIRE_4[1].IN1
ctl_bus_db_we => SYNTHESIZED_WIRE_4[2].IN1
ctl_bus_db_we => SYNTHESIZED_WIRE_4[3].IN1
ctl_bus_db_we => SYNTHESIZED_WIRE_4[4].IN1
ctl_bus_db_we => SYNTHESIZED_WIRE_4[5].IN1
ctl_bus_db_we => SYNTHESIZED_WIRE_4[6].IN1
ctl_bus_db_we => SYNTHESIZED_WIRE_4[7].IN1
ctl_bus_db_we => SYNTHESIZED_WIRE_2.IN1
clk => dout[0].CLK
clk => dout[1].CLK
clk => dout[2].CLK
clk => dout[3].CLK
clk => dout[4].CLK
clk => dout[5].CLK
clk => dout[6].CLK
clk => dout[7].CLK
ctl_bus_db_oe => db[0].OE
ctl_bus_db_oe => db[1].OE
ctl_bus_db_oe => db[2].OE
ctl_bus_db_oe => db[3].OE
ctl_bus_db_oe => db[4].OE
ctl_bus_db_oe => db[5].OE
ctl_bus_db_oe => db[6].OE
ctl_bus_db_oe => db[7].OE
D[0] <> D[0]
D[1] <> D[1]
D[2] <> D[2]
D[3] <> D[3]
D[4] <> D[4]
D[5] <> D[5]
D[6] <> D[6]
D[7] <> D[7]
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]


|spectrum|z80_top_direct_n:z80_|control_pins_n:control_pins_
busack => pin_nBUSACK.DATAIN
CPUCLK => clk.DATAIN
pin_control_oe => pin_nWR.OE
pin_control_oe => pin_nRD.OE
pin_control_oe => pin_nIORQ.OE
pin_control_oe => pin_nMREQ.OE
in_halt => pin_nHALT.DATAIN
pin_nWAIT => mwait.DATAIN
pin_nBUSRQ => busrq.DATAIN
pin_nINT => intr.DATAIN
pin_nNMI => nmi.DATAIN
pin_nRESET => reset_in.DATAIN
nM1_out => pin_nM1.DATAIN
nRFSH_out => pin_nRFSH.DATAIN
nRD_out => pin_nRD.DATAIN
nWR_out => pin_nWR.DATAIN
nIORQ_out => pin_nIORQ.DATAIN
nMREQ_out => pin_nMREQ.DATAIN
nmi <= pin_nNMI.DB_MAX_OUTPUT_PORT_TYPE
busrq <= pin_nBUSRQ.DB_MAX_OUTPUT_PORT_TYPE
clk <= CPUCLK.DB_MAX_OUTPUT_PORT_TYPE
intr <= pin_nINT.DB_MAX_OUTPUT_PORT_TYPE
mwait <= pin_nWAIT.DB_MAX_OUTPUT_PORT_TYPE
reset_in <= pin_nRESET.DB_MAX_OUTPUT_PORT_TYPE
pin_nM1 <= nM1_out.DB_MAX_OUTPUT_PORT_TYPE
pin_nMREQ <= pin_nMREQ.DB_MAX_OUTPUT_PORT_TYPE
pin_nIORQ <= pin_nIORQ.DB_MAX_OUTPUT_PORT_TYPE
pin_nRD <= pin_nRD.DB_MAX_OUTPUT_PORT_TYPE
pin_nWR <= pin_nWR.DB_MAX_OUTPUT_PORT_TYPE
pin_nRFSH <= nRFSH_out.DB_MAX_OUTPUT_PORT_TYPE
pin_nHALT <= in_halt.DB_MAX_OUTPUT_PORT_TYPE
pin_nBUSACK <= busack.DB_MAX_OUTPUT_PORT_TYPE


