| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| z80_|control_pins_ |
15 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|data_pins_ |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
| z80_|address_pins_ |
19 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|sw1_ |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
| z80_|sw2_ |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
| z80_|bus_switch_ |
5 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|bus_control_ |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|address_latch_|b2v_mux |
33 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9 |
5 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7 |
5 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4 |
5 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2 |
5 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10 |
5 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0 |
5 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|address_latch_|b2v_inst_inc_dec |
19 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|address_latch_|b2v_inst7 |
33 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|address_latch_ |
10 |
0 |
0 |
0 |
17 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
| z80_|reg_control_ |
24 |
0 |
0 |
0 |
23 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|reg_file_|b2v_latch_wz_lo |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|reg_file_|b2v_latch_wz_hi |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|reg_file_|b2v_latch_sp_lo |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|reg_file_|b2v_latch_sp_hi |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|reg_file_|b2v_latch_pc_lo |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|reg_file_|b2v_latch_pc_hi |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|reg_file_|b2v_latch_iy_lo |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|reg_file_|b2v_latch_iy_hi |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|reg_file_|b2v_latch_ix_lo |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|reg_file_|b2v_latch_ix_hi |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|reg_file_|b2v_latch_ir_lo |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|reg_file_|b2v_latch_ir_hi |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|reg_file_|b2v_latch_hl_lo |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|reg_file_|b2v_latch_hl_hi |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|reg_file_|b2v_latch_hl2_lo |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|reg_file_|b2v_latch_hl2_hi |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|reg_file_|b2v_latch_de_lo |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|reg_file_|b2v_latch_de_hi |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|reg_file_|b2v_latch_de2_lo |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|reg_file_|b2v_latch_de2_hi |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|reg_file_|b2v_latch_bc_lo |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|reg_file_|b2v_latch_bc_hi |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|reg_file_|b2v_latch_bc2_lo |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|reg_file_|b2v_latch_bc2_hi |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|reg_file_|b2v_latch_af_lo |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|reg_file_|b2v_latch_af_hi |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|reg_file_|b2v_latch_af2_lo |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|reg_file_|b2v_latch_af2_hi |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|reg_file_ |
29 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
| z80_|alu_|b2v_prep_daa |
8 |
0 |
1 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|alu_|b2v_op2_latch_mux_low |
11 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|alu_|b2v_op2_latch_mux_high |
11 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|alu_|b2v_op1_latch_mux_low |
11 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|alu_|b2v_op1_latch_mux_high |
6 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|alu_|b2v_input_shift |
11 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|alu_|b2v_input_bit_select |
3 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|alu_|b2v_core|b2v_alu_slice_bit_3 |
6 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|alu_|b2v_core|b2v_alu_slice_bit_2 |
6 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|alu_|b2v_core|b2v_alu_slice_bit_1 |
6 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|alu_|b2v_core|b2v_alu_slice_bit_0 |
6 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|alu_|b2v_core |
12 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|alu_ |
27 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|alu_flags_|b2v_inst_mux_cf2 |
6 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| z80_|alu_flags_|b2v_inst_mux_cf |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|alu_flags_ |
30 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| z80_|alu_select_ |
17 |
0 |
0 |
0 |
17 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|alu_control_|b2v_inst_shift_mux |
11 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| z80_|alu_control_|b2v_inst_pf_sel |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|alu_control_|b2v_inst_cond_mux |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|alu_control_ |
29 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|sequencer_ |
7 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|memory_ifc_ |
13 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|resets_ |
6 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|pla_decode_ |
15 |
19 |
1 |
19 |
105 |
19 |
19 |
19 |
0 |
0 |
0 |
0 |
0 |
| z80_|pin_control_ |
9 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|ir_ |
12 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|interrupts_ |
12 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|execute_ |
128 |
0 |
19 |
0 |
111 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|decode_state_ |
15 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_|clk_delay_ |
9 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| z80_ |
6 |
2 |
0 |
2 |
24 |
2 |
2 |
2 |
8 |
0 |
0 |
0 |
0 |
| ula_|zx_keyboard_ |
28 |
0 |
9 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ula_|ps2_keyboard_ |
4 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ula_|video_ |
12 |
0 |
0 |
0 |
28 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ula_|i2s_intf_ |
35 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ula_|i2c_loader_ |
2 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
| ula_|clocks_ |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ula_|pll_|altpll_component|auto_generated |
2 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ula_|pll_ |
1 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ula_ |
40 |
2 |
3 |
2 |
47 |
2 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
| sdram_|sdram_clk_pll|altpll_component|auto_generated |
2 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_|sdram_clk_pll |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_ |
59 |
33 |
1 |
33 |
56 |
33 |
33 |
33 |
16 |
0 |
0 |
0 |
0 |
| ram1|altsyncram_component|auto_generated|mux2 |
34 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ram1|altsyncram_component|auto_generated|rden_decode |
2 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ram1|altsyncram_component|auto_generated|decode3 |
3 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ram1|altsyncram_component|auto_generated |
25 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ram1 |
25 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ram0|altsyncram_component|auto_generated|mux5 |
17 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ram0|altsyncram_component|auto_generated|mux4 |
17 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ram0|altsyncram_component|auto_generated|rden_decode_b |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ram0|altsyncram_component|auto_generated|rden_decode_a |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ram0|altsyncram_component|auto_generated|decode3 |
2 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ram0|altsyncram_component|auto_generated|decode2 |
2 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ram0|altsyncram_component|auto_generated |
47 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ram0 |
47 |
10 |
0 |
10 |
16 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| rom|altsyncram_component|auto_generated|mux2 |
17 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| rom|altsyncram_component|auto_generated|rden_decode |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| rom|altsyncram_component|auto_generated |
15 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| rom |
15 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |