--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_DECODES=6 LPM_WIDTH=3 data enable eq
--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ  VERSION_END


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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
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--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
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--  applicable agreement for further details.



--synthesis_resources = lut 8 
SUBDESIGN decode_psa
( 
	data[2..0]	:	input;
	enable	:	input;
	eq[5..0]	:	output;
) 
VARIABLE 
	data_wire[2..0]	: WIRE;
	enable_wire	: WIRE;
	eq_node[5..0]	: WIRE;
	eq_wire[7..0]	: WIRE;
	w_anode653w[3..0]	: WIRE;
	w_anode670w[3..0]	: WIRE;
	w_anode680w[3..0]	: WIRE;
	w_anode690w[3..0]	: WIRE;
	w_anode700w[3..0]	: WIRE;
	w_anode710w[3..0]	: WIRE;
	w_anode720w[3..0]	: WIRE;
	w_anode730w[3..0]	: WIRE;

BEGIN 
	data_wire[] = data[];
	enable_wire = enable;
	eq[] = eq_node[];
	eq_node[5..0] = eq_wire[5..0];
	eq_wire[] = ( w_anode730w[3..3], w_anode720w[3..3], w_anode710w[3..3], w_anode700w[3..3], w_anode690w[3..3], w_anode680w[3..3], w_anode670w[3..3], w_anode653w[3..3]);
	w_anode653w[] = ( (w_anode653w[2..2] & (! data_wire[2..2])), (w_anode653w[1..1] & (! data_wire[1..1])), (w_anode653w[0..0] & (! data_wire[0..0])), enable_wire);
	w_anode670w[] = ( (w_anode670w[2..2] & (! data_wire[2..2])), (w_anode670w[1..1] & (! data_wire[1..1])), (w_anode670w[0..0] & data_wire[0..0]), enable_wire);
	w_anode680w[] = ( (w_anode680w[2..2] & (! data_wire[2..2])), (w_anode680w[1..1] & data_wire[1..1]), (w_anode680w[0..0] & (! data_wire[0..0])), enable_wire);
	w_anode690w[] = ( (w_anode690w[2..2] & (! data_wire[2..2])), (w_anode690w[1..1] & data_wire[1..1]), (w_anode690w[0..0] & data_wire[0..0]), enable_wire);
	w_anode700w[] = ( (w_anode700w[2..2] & data_wire[2..2]), (w_anode700w[1..1] & (! data_wire[1..1])), (w_anode700w[0..0] & (! data_wire[0..0])), enable_wire);
	w_anode710w[] = ( (w_anode710w[2..2] & data_wire[2..2]), (w_anode710w[1..1] & (! data_wire[1..1])), (w_anode710w[0..0] & data_wire[0..0]), enable_wire);
	w_anode720w[] = ( (w_anode720w[2..2] & data_wire[2..2]), (w_anode720w[1..1] & data_wire[1..1]), (w_anode720w[0..0] & (! data_wire[0..0])), enable_wire);
	w_anode730w[] = ( (w_anode730w[2..2] & data_wire[2..2]), (w_anode730w[1..1] & data_wire[1..1]), (w_anode730w[0..0] & data_wire[0..0]), enable_wire);
END;
--VALID FILE
